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With the fast development of electronic skin, there is a great demand for wearable sensing devices. Herein, a piezoresistive sensor has been fabricated comprising a conductive film of Polydimethylsiloxane (PDMS)-carbon nanotubes (CNTs) sandwiched by two protection films of PDMS. A simple and low-cost manufacturing method has been proposed to wrap CNTs inside the flexible PDMS to obtain a soft sensor with excellent conductivity, high sensitivity, and fast response to various pressures. Additionally, films with different percentages of CNTs were compared. The results show that the film with 7% CNTs has higher conductivity and sensitivity. Moreover, the surface morphologies and microstructures of the superior PDMS-CNTs film were studied by scanning electron microscope, and sensing properties of the pressure sensor were tested. Furthermore, applications of single sensor and sensor array were studied. The results exhibit that the as-prepared pressure sensor successfully detected different human motions and recognized Morse code and words, indicating that the portable sensor can be potentially applied in wide areas such as smart devices and flexible robotics.

A supercell of a nanotube heterojunction formed by an (8, 0) carbon nanotube (CNT) and an (8, 0) silicon carbide nanotube (SiCNT) is established, in which 96 C atoms and 32 Si atoms are included. The geometry optimization and the electronic property of the heterojunction are implemented through the first-principles calculation based on the density functional theory (DFT). The results indicate that the structural rearrangement takes place mainly on the interface and the energy gap of the heterojunction is 0.31 eV, which is narrower than those of the isolated CNT and the isolated SiCNT. By using the average bond energy method, the valence band offset and the conduction band offset are obtained as 0.71 and −0.03 eV, respectively.

The carrier microscopic transport process of uniaxial strained Si n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) is analyzed under -ray radiation. The model of radiation-induced defect densities that are quantitative representations of trapped charges integrated across the thickness of the oxide (Not), and the number of interface traps at the semiconductor/oxide interface (Nit), is established. The variations of electrical characteristics of the uniaxial strained Si nanometer NMOSFET are also investigated under the total dose radiation. The device of uniaxial strained Si nanometer NMOSTET is irradiated by a 60Co -ray laboratory source at a constant dose rate of 0.5 Gy (Si)/s. The TID is deposited in several steps up to a maximum value of 2.5 kGy. Electrical measurements are performed at each TID step. All irradiated samples are measured using field test, and are required to finish measurement within 30 min, in order to reduce the annealing effect. Static drain-current ID vs. gate-voltage VGS electrical characteristics are measured with an HP4155B parametric analyzer. Some parameter extractions presented here come from these static measurements including the threshold voltage VTH, the trans-conductance gm, and the leakage current IOFF (ID at VGS=0 V and VDS=VDD). Irradiation bias:VG=+1 V, drain voltage VD is equal to source voltage VS (VD=VS=0). Measurement bias:VG=0-1 V, scanning voltage Vstep=0.05 V, VD=50 mV, and VS=0. The results indicate the drift of threshold voltage, the degradation of carrier mobility and the increase of leakage current because of the total dose radiation. Based on quantum mechanics, an analytical model of tunneling gate current of the uniaxial strained Si nanometer is developed due to the total dose irradiation effect. Based on this model, numerical simulation is carried out by Matlab. The influences of total dose, geometry and physics parameters on tunneling gate current are simulated. The simulation results show that when radiation dose and bias are constant, the tunneling gate current increases as the channel length decreases. When the structure parameters and the stress are fixed, the tunneling gate current increases with the increase of radiation dose. Whereas at a given the radiation dose, tunneling gate current will decrease due to the stress. When radiation dose and bias are kept unchanged, the tunneling gate current increases with the thickness of the gate oxide layer decresing. When the gate-source voltage, the thickness of oxide layer and stress are fixed, tunneling gate current is reduced with the increase of doping concentration in channel. When the structural parameters, the gate-source voltage and radiation dose are constant, the tunneling gate current decreases with increasing drain-source voltage. In addition, to evaluate the validity of the model, the simulation results are compared with experimental data, and good agreement is confirmed. Thus, the experimental results and proposed model provide good reference for research on irradiation reliability and application of strained integrated circuit of uniaxial strained Si nanometer n-channel metal-oxide-semiconductor field-effect transistor.

A GdxY1−xCa4O(BO3)3 (GdxY1−xCOB) crystal, which belongs to rare-earth calcium oxyborate family, is used for non-critical phase-matching of visible and ultraviolet (UV) light. We employ 2.8-MeV He+ ions to form optical waveguides in the Gd0.275Y0.725COB crystal at room temperature. The doses are varied from 1.5×1016 ions/cm2 to 5×1016 ions/cm2. A model 2010 prism coupler is used to measure the modes in Gd0.275Y0.725COB waveguides formed by MeV He+ ion implantation. The refractive index profile is fitted based on the reflectivity calculation method. The shape of refractive index profile is compared with one of nuclear energy loss obtained by TRIM'98 simulation.

The finite-element model of strained silicon PMOSFET was established based on the structure of small uniaxial strained silicon device. Using thermal strain method to simulate the parallel strain distribution of the channel through ANSYS simulation platform. The results present that: (1)the compressive strain on the channel surface is quite uniform along the direction parallel to the channel, the compressive strain in the center of channel decreases with the increasing distance from the channel surface, which transforms into tensile strain when the distance reaches or beyonds the etching depth of silicon-germanium source and drain. (2)the strain in the channel will correspondingly increase with the decreasing channel length or increasing etching depth of silicon-germanium source and drain or increasing germanium fraction of source and drain. The conclusion provides a design basis to improve the device performance by controlling the strain, in addition, the conclusion is in line with the relevant literature.

In this paper, based on the distribution of electric field in the channel which follows the Guass Law, an analytical expression of Quasi-2D threshold voltage model for strained Si nMOSFET with Polycrystalline SiGe gate was established. With this model, the variation threshold voltage with its design physical and geometric parameters can be predicted, such as Ge content, oxide thickness, doping concentration, gate length, and drain bias. The validity of the model was proved by ISE TCAD simulation. This model is significant for the design of high performance strained Si nMOSFET

With the scaling of transistor dimensions, thinner gate oxides results in exponential increases in gate tunneling current and static standby power consumption of CMOS circuits is severely affected by the presence of gate tunneling currents. In this paper, a theory gate tunneling current model in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness is presented and the simulation results in BSIM4 model well agree with the model proposed. The characteristics of current source inverter composed are also studied in detail to analyze its behavior and predict the trends of power dissipated with scaled technology nodes in the effects of gate tunneling current.

Ge has become a promising material for Si-based optoelectronic integrated circuits (OEIC) due to its pseudo-direct bandgap.In this paper we achieved tensilely strained Ge free-standing nanomembrane (NM) lightemitting diode (LED), using silicon nitride thin film with high stress.The tensile stress in the Ge layer can be controlled by adjustable process parameters.An expected redshift of electroluminescence (EL) in Ge NM LED is observed at room temperature, which has been attributed to the shrinking of its direct bandgap relative to its indirect bandgap.An EL with dramatically increased intensity was observed around 1876 nm at a tensile strain of 1.92%, which demonstrates the direct-band recombination in tensilely strained Ge NM.

The capacitance model is fundamental for the transient analysis, AC analysis and noise analysis of uniaxially strained Si MOSFET device and circuit. Firstly, the 16-differential capacitance model for uniaxially strained Si NMOSFET is developed. Secondly, the simulation results from that model match the experimental results well, which validates the accuracy of the model. Meanwhile the simulated relations of key gate capacitance Cgg to stress intensity, bias voltage，channel length and concentration of poly gate are obtained and analyzed, showing that the value of Cgg is a little larger than that of strainless bulk device while the changing tendency keeps the same.

Silicon-based reconfigurable antenna, which is fabricated by heterogeneous and lateral surface PiN (SPiN), is an effective technology to achieve antenna miniaturization and enhance radar and wireless communication system performance. In this paper, the heterogeneous and lateral Si/Ge/Si SPiN diode is presented, that can weaken the band gap narrowing of the P + and N + region to improve the injection ratio of PN junction. And the electrical properties of the solid state plasma within the intrinsic region are also studied. Based on the bipolar diffusion model and Fletcher boundary condition, the analytic models of the junction voltage, the current density and the solid state plasma concentration distribution are established for a large injection current, and the numerical simulation has been carried out. Results show that the junction voltage increases linearly with the increase of applied voltage and the solid state plasma concentration at the boundary; and the current density increases exponentially with increasing junction voltage and the applied voltage, respectively. And the applied voltage and the current density of heterogeneous SPiN diode is lower than that of homogeneous SPiN diode under the same condition due to the difference of barrier heights between the heterojunction and homojunction. In addition, results also show that the value of the concentration decreases with increasing length of the intrinsic region; otherwise, it increases with increasing applied voltage and the doping concentration in the P+ and N+ regions. Under the same conditions, the solid state plasma concentration of the heterogeneous SPiN diode is nearly seven times that of homogeneous diode, which is in excellent agreement with the data published, giving the evidence for the validity of our method. The proposed models provide an effective reference for the design and application of silicon-based reconfigurable antennas.

Hot carrier gate current is one of the factors that influence the power and reliability of metal-oxide-semiconductor field effect transistor (MOSFET). Based on the physical process of generation of the hot carrier effect, a model of hot carrier gate current for uniaxially strained Si NMOSFET is developed. With that model, the simulation results of hot carrier gate current against stress intensity, gate-source bias, channel doping concentration, and drain-source bias are obtained and analyzed. The relationship between life time of time-dependent dielectric break down (TDDB) and gate-source bias is simulated and analyzed. Results show that the uniaxially strained Si MOSFET not only has smaller hot carrier gate current, but also has more stable reliability as compared with the strainless bulk device. Meanwhile, the simulation results match the experimental results very well, which validates the accuracy of the model.

In this work, the carrier microscopic transport process of biaxial strained Si p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) under γ -ray radiation has been studied. Effect of γ-ray on devices and the relationship between the variation of device electrical characteristics and the total dose are investigated. A model for considering the degradation of threshold voltage and transconductance due to the total dose radiation is established. Based on this model, numerical simulation has been carried out. Results show that the threshold voltage of PMOSFET decreases with increasing radiation dose. At a lower total dose, the threshold voltage decreases linearly. However, at a higher total dose, it becomes saturated. The degradation can be explained by the generation of trapped charges which increase the impact possibility of carriers in the channel and induce the reduction of mobility and transconductance accordingly. Finally, the simulation results are compared with the experimental data. A good agreement is observed, indicating the validation of our proposed model.

Indirect bandgap Ge can be turned to a direct bandgap semiconductor by the alloy-modified technique, which can be applied to advanced photonic devices and electronic devices. Based on 8 bands Kronig-Penny Hamilton, this paper focuses on the physical parameters of direct bandgap Ge1-xSnx, such as conduction band effective density of states, valence band effective density of states and the intrinsic carrier concentration, and aims to provide valuable references for understanding the direct bandgap modified Ge materials and device physics as well as their applications. Results show that: conduction band effective density of states in direct bandgap Ge1-xSnx alloy decreases obviously with increasing Sn fraction, while its valence band effective density of states almost does not change with increasing Sn fraction. Compared with bulk Ge, the conduction band effective density of states and valence band effective density of states in direct bandgap Ge1-xSnx alloy are lower by two and one orders of magnitude respectively; the intrinsic carrier concentration in direct bandgap Ge1-xSnx alloy increases with increasing Sn fraction, and its value is an order of magnitude higher than that of bulk Ge.

We aim to establish a model of the averaged hole mobility of strained Si grown on (001), (101), and (111) relaxed Si1?x Gex substrates. The results obtained from our calculation show that their hole mobility values corresponding to strained Si (001), (101) and (111) increase by at most about three, two and one times, respectively, in comparison with the unstrained Si. The results can provide a valuable reference to the understanding and design of strained Si-based device physics.

The tunneling field-effect transistor (TFET) is a potential candidate for the post-CMOS era. In this paper, a threshold voltage model is developed for this new kind of device. First, two-dimensional (2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions. Then based on the physical definition of threshold voltage for the nanoscale TFET, the threshold voltage model is developed. The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data. It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper. This threshold voltage model provides a valuable reference to TFET device design, simulation, and fabrication.

Based on the structure of strained Si/SiGe NMOSFET, a unified drain current model is presented in this paper. The model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a smoothing function, and guarantees the continuities of the drain current and its derivatives.Furthermore, the model accuracy is enhanced by including carrier velocity saturation and channel length modulation effects. Comparisons between the model and the measured data show that the drain current model can describe the device characteristics well. The proposed model is useful for the design and simulation of digital and analogy circuits made of strained Si.

A new strained Si MOSFET structure with hetero-polycrystalline SiGe gate was studied, which combines the advantages of “gate engineering” and “strain engineering”. The new structure improved the carrier transport efficiency, suppressed the short-channel effects (SCE), and enhanced the performance on the basis of strain. Then a physically modeling strategy such as quasi-2D surface potential of strong inversion, threshold voltage, and channel current was presented for the strained Si NMOSFET. Finally, the above model was computed and the results were analyzed.

The development of strained-Si physical compact threshold voltage model is based on Poisson's equation, using the gradual channel approximation (GCA) and coherent quasi-two-dimensional (2D) analysis, as well as taking into account the effects of short channel effect (SCE), narrow channel effect (NCE), non-uniform doping effect, and drain-induced barrier lowering (DIBL) effect. Moreover, the threshold voltage parameters are extracted from the experimental results by software. Finally, the validity of our model is derived from the comparison of our simulation results. The proposed model may be useful for the design and simulation of very large scale integrated circuits (VLSI) made of strained-Si.

The gate capacitance-voltage (C-V) characteristic of strained SiGe pMOSFET is very different from that of bulk Si pMOSFET, and can be strongly affected by the channel doping. In this paper, we first study the formation mechanism of the "plateau" which can be observed in the gate C-V characteristics of strained SiGe pMOSFET, and then present a physics based analytical model to predict the gate C-V characteristic of strained SiGe pMOSFET. It is found that this plateau is channel doping dependent. The results from the model are compared with the experimental results and they are found to be in excellent agreement with each other, giving the evidence for its validity.

Accumulation MOS capacitor is more linear than inversion MOS capacitor and is almost independent of the operation frequency. In this paper, we present first the formation mechanism of the plateau, observed in the C-V characteristic of the strained-Si NMOS capacitor, and then a physical model for strained-Si NMOS capacitor in accumulation region. The results from the model show to be in excellent agreement with the experimental data. The proposed model can provide valuable reference for the strained-Si device design, and is has been implemented in the software for extracting the parameter of strained-Si MOSFET.

A fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated. By adjusting the thickness of graded SiGe, modifying the channel doping concentration, changing the Ge fraction of the relaxed SiGe layer and forming a p-well by multiple implantation technology, a surface strained Si-channel NMOSFET was fabricated, of which the low field mobility was enhanced by 140%, compared with the bulk-Si control device. Strained NMOSFET and PMOSFET were used to fabricate a strained CMOS inverter based on a SiGe virtual substrate. Test results indicated that the strained CMOS converter had a drain leakage current much lower than the Si devices, and the device exhibited wonderful on/off-state voltage transmission characteristics.

A high-performance PMOSFET based on silicon material of hybrid orientation is obtained. Hybrid orientation wafers, integrated by (100) and (110) crystal orientation, are fabricated using silicon-silicon bonding, chemical mechanical polishing, etching silicon and non-selective expitaxy. A PMOSFET with W/L = 50 μm/8 μm is also processed, and the measured results show that the drain-source current and peak mobility of the PMOSFET are enhanced by up to 50.7% and 150% at Vgs = −15 V and Vds = −0.5 V, respectively. The mobility values are higher than that reported in the literature.

A threshold voltage model is created by analyzing differents distributions of surface electric field and the condition of avalanche breakdown, based on the structure of a novel high speed semiconductor device p-IMOS in this paper. Model verification is carried out using the 2D device simulator ISE. By analyzing the model, the dependences of threshold voltage on drain-source voltage, Si layer thickness and gate length are studied. The results of the model are in good agreement with experimental results and ISE simulation results. The proposed model can also be easily used for the reasonable analysis and the design of p-IMOS.

An analytical expression for the collector resistance of a novel vertical SiGe heterojunction bipolar transistor (HBT) on thin film silicon-on-insulator (SOI) is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate—collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μm millimeter-wave SiGe SOI BiCMOS devices.

Silicon germanium (SiGe) heterojunction bipolar transistor (HBT) on thin silicon-on-insulator (SOI) has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base—collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiGe devices and circuits.

The SiGe heterojunction bipolar transistor (HBT) on thin film SOI is successfully integrated with SOI CMOS by folded collector. This paper deals with the collector depletion charge and the capacitance of this structure. An optimized model is presented based on our previous research. The results show that the charge model is smoother, and that the capacitance model with considering different current flow areas, is vertical and horizontal depletion capacitances in series, showing that the depletion capacitance is smaller than that of a bulk HBT. The charge and capacitance vary with the increase of reverse collector-base bias. This collector depletion charge and capacitance model provides valuable reference to the SOI SiGe HBT electrical parameters design and simulation such as Early voltage and transit frequency in the latest 0.13 m SOI BiCMOS technology.

By solving Poisson equation, models of voltage and electric field distribution are build respectively in collector junction depletion layer of SiGe HBT (heterojunction bipolar transistor) with intrinsic SiGe layer. On this basis, models of the collector junction depletion layer width and delay time are obtained. Applying MATLAB, the impact of physical and electrical parameters on SiGe HBT collector junction depletion layer width and depletion delay time are quantitatively analyzed. When base doping concentration and collector junction reverse bias are large, the depletion delay time is quite long. But, when base doping external diffusion depth and collector region doping are large, the depletion delay time is quite short.

For scaled metal-oxide semiconductor field effect transistor (MOSFET) devices, normal operation is seriously affected by the static gate tunneling leakage current due to the ultra-thin gate oxide of MOSFET, and the novel MOSFET devices based on strained Si are similar to bulk Si devices in the effects. To illustrate the impact of gate leakage current on performance of novel strained Si device, a theoretical gate tunneling current predicting model by integral approach following the analysis of quasi-two-dimensional surface potential is presented in this study. On the basis of theoretical model, performance of MOSFET device was quantitatively studied in detail using ISE simulator, including different gate voltages and gate oxide thickness. The experiments show that simulation results agree well with theoretical analysis, and the theory and experimental data will contribute to future VLSI circuit design.

The base—collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors (HBTs) on silicon on insulator (SOI) is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector—base bias—and shows a kink as the reverse collector—base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.

The model of nMOSFET threshold voltage was established based on study of voltage distribution in strained Si film,which was grown on relaxed SiGe virtual substrate.The model was analyzed with reasonable parameters, and the dependence of threshold voltage on Ge fraction and channel doping was revealed. The dependence of threshold voltage shift on Ge fraction was also obtained. The relationship between threshold voltage and strained Si layer thickness and doping was studied. The results indicates, the threshold voltage increases with increasing doping concentrations of relaxed SiGe layer, decreases with increasing Ge fraction of relaxed SiGe layer, and increases with increasing strained Si layer thickness. This threshold voltage model provides valuable reference to the strained-Si device design.

A SOI PMOSFET with SiGe quantum well channel was formed by growing the SiGe film on the Si SOI structure. Not only does the device have the advantage of SOI structure, but also the performance of the device is improved because the carrier mobility in SiGe quantum well is much higher than that in Si. In this paper, the threshold voltage model of strained SiGe SOI quantum well channel PMOSFET is established on the basis of general Si SOI MOSFET, also the model of voltage-current characterisfic is founded. The characteristic of voltage-current, transconductance and leak conductance were simulated and analyzed using MATLAB. The results of the simulation confirm that the strained SiGe SOI quantum well channel PMOSFET performs much better than the conventional PMOSFET.

To visualize the relationship between the collector current and source-drain voltage in the SiGe/Si chare injection transistor (CHINT), the mathematical model of this device is set up by using the tunnel model of two-dimensional hole gas(2DHG)in SiGe/Si quantum well. Then the model is simulated by MATLAB, the result shows that the drain current shows strong negative differential resistance when VDS is about 1.5V, which is in accordance with the results of the other papers.

In this work, the abnormal double-peak in the electroluminescence spectra of In xGa1-xN/GaN multiple quantum wells (MQWs) light emitting d iode s tructure materials with high indium contents was studied under different injecti on currents. The results show that the screening of internal electric field by i njection current plays an important role in the radiation recombination process of InxGa1-xN/GaN-MQWs materials.

The SiO2layer as a gate dielectric is grown on p_type 4H-SiC wafer by means of 3UCVD. Positive oxide charge density only has 1.6×1011cm-2, its result is superior to conventional thermally oxidized process. A new front tofront device with advantages over conventional test structure is used for high_frequ ency C-V measurement.

When SiGe HBT is in the case of normal operation, depleted approximation is not suited, and the influence of movable charge should be taken into account when c onsideri ng of their junction capacitance. Based on the analysis and study of the carr ier tr ansport of SiGe HBT, emitter junction capacitance model is developed by consider ing the carrier distribution, and the collector junction capacitance model is al so established for different current densities including base extending eff ect. The junction capacitance models are used to simulate frequency characteristics. The results of simulation show good agreements with the experimental data.