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Subwavelength grating (SWG) metamaterials have garnered a great interest for their singular capability to shape the material properties and the propagation of light, allowing the realization of devices with unprecedented performance. However, practical SWG implementations are limited by fabrication constraints, such as minimum feature size, that restrict the available design space or compromise compatibility with high-volume fabrication technologies. Indeed, most successful SWG realizations so far relied on electron-beam lithographic techniques, compromising the scalability of the approach. Here, we report the experimental demonstration of an SWG metamaterial engineered beam splitter fabricated with deep-ultraviolet immersion lithography in a 300-mm silicon-on-insulator technology. The metamaterial beam splitter exhibits high performance over a measured bandwidth exceeding 186 nm centered at 1550 nm. These results open a new route for the development of scalable silicon photonic circuits exploiting flexible metamaterial engineering.

In this work, we present an advanced heterogeneous integration scheme which consists in integrating a thin InP layer by wafer-bonding onto a silicon wafer (InPoSi) on which a regrowth step of III-V materials is implemented. Vertical p-i-n AlGaInAs lasers obtained from a single Selective Area Growth (SAG) step on InPoSi were fabricated. Thanks to SAG, the AlGaInAs-MQW structures successfully cover a PL range of 160 nm in the C+L band. Based on these structures, a 5- channel laser array was fabricated. The latter successfully covers a 155 nm-wide spectral band from 1515 nm to 1670 nm with a maximum output power of 20 mW under continuous-wave regime at 20°C. High thermal stability up to 70°C is demonstrated with a characteristic temperature of 69°C for the lasers emitting from 1515 nm to 1600 nm.

Roughness has always been a key detractor of the optical losses within the silicon photonics devices. With scaling at 300mm wafer, there is an introduction of new tools such immersion lithography scanner, OPC technique that can help to drive furthermore the optical losses reduction. This study will detail the work done on characterizing multiple steps of the process (Lithography, Etch, Annealing) and using roughness tools such LER (Line Edge Roughness), LWR (Line Width Roughness) and finally PSD (Power Spectral Density) to understand the main detractor of the optical losses at each step. These data will be extracted using SEM imaging from VeritySEM 6i.

Vertical p-i-n lasers integrated by wafer-bonding and regrowth on a heterogeneous InP-on-SOI wafer are presented. We demonstrate for the first time lasers based on regrown III-V active regions efficiently coupled to Si-photonic DBR cavities.

Vertical p-i-n AlGaInAs lasers obtained from a single Selective Area Growth (SAG) step on a thin InP layer bonded to silicon wafers are presented. A PL extension from 1490 nm to 1645 nm was demonstrated on InP-SOI wafer. Based on this result, a record of 155 nm wide spectral range was obtained for FP lasers on InP-SiO 2 /Si wafer.

In this work, we present the fabrication process of a $3~\mu \text{m}$ -thick AlGaInAs-based vertical p-i-n laser diode structure grown on a directly bonded InP-SiO2/Si (InPoSi) substrate. High-quality epitaxial growth on InPoSi is reported. Based on these structures, the fabrication process of Fabry-Perot broad lasers is presented. Device performance is compared to the ones obtained from the same growth run on an InP substrate as a reference. High electrical properties of the n and p contacts are demonstrated. Lasing operation in the pulse regime is shown up to 50°C. Threshold current densities as low as 0.4 kA/cm 2 at 20°C are obtained for the laser on InPoSi, comparable to the ones obtained for the reference on InP substrate.

We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.

Hybrid integration of III-V materials onto silicon by direct bonding technique is a mature and promising approaches to develop advanced photonic integrated devices into the silicon photonics platform. In this approach, the III-V material stack is grown on an InP wafer in a unique epitaxial step prior to the direct bonding process onto the silicon-on-insulator wafer. Currently, no additional epitaxial regrowth steps are implemented after bonding. This can be seen as a huge limitation as compared to the III-V on III-V wafer mature technology where multi-regrowth steps are most often implemented. In this work, we have studied the material behavior of an InP membrane on silicon (InPoSi) under epitaxial regrowth conditions by metal-organic vapor phase epitaxy (MOVPE). MOVPE requires high-temperature elevation, typically above 600 °C. We show for the first time the appearance of voids at 400 °C in an InP seed (100 nm) directly-bonded onto a thermally oxidized Si substrate despite the use of a thick SiO2 oxide (200 nm) at the bonding interface. This phenomenon is explained by a weakening of the bonding interface while high-pressurized hydrogen is present. A kinetic study of the hydrogen lateral diffusion is carried out, enabling the assessment of its lateral diffusion length. To overcome the void formation, highly efficient outgassing trenches after bonding are demonstrated. Finally, high-quality AlGaInAs-based multi-quantum well (MQW) heterostructure surrounded by two InP layers was grown by MOVPE on InPoSi template patterned with outgassing trenches. This process is not only compatible with MOVPE regrowth conditions (650 °C under PH3) but also with conventional fabrication processes used for photonic devices.

Silicon nanophotonics represents a scalable route to deploy complex optical integrated circuits for multifold applications, markets, and end-users. Most recently, applications such as optical communications and interconnects, sensing, as well as quantum-based technologies, among others, present additional opportunities for integrated silicon nanophotonics to expand its frontiers from laboratories to industrial product development. Within a wide set of functionalities that silicon nanophotonic chips can afford, the availability of low-loss optical input/output interfaces has been regarded as a major practical obstacle that hampers long-term success of integrated photonic platforms. Indeed, fiber-chip interfaces based on diffraction gratings are an attractive solution to resonantly couple the light between planar waveguide circuits and standard single-mode optical fibers. Surface grating couplers provide much more alignment tolerance in fiber attach compared with most conventional edge-coupled alternatives, while retaining the much-needed control of the fiber placement on the chip surface and wafer-level-test capability that the in-plane convertors lack. Here, we report on our recent advances in the development of high-performance fiber-chip grating couplers that exploit the blazing effect. This is achieved with well-established dual-etch processing in interleaved teeth-trench arrangements or using L-shaped grating-teeth-profile geometries. The first demonstration of the L-shaped-based grating coupler yielded a coupling loss of -2.7 dB, seamlessly fabricated into a 300-mm foundry manufacturing process using 193-nm deep-ultraviolet stepper lithography. Moreover, silicon metamaterial L-shaped fiber couplers may promote robust sub-decibel coupling of light, reaching a simulated coupling loss of -0.25 dB, while featuring device layouts (>120 nm) compatible with lithographic technologies in silicon semiconductor foundries., SPIE OPTO 2020 - Smart Photonic and Optoelectronic Integrated Circuits XXII, February 3-6, 2020, San Francisco, California, Series: Proceedings of SPIE

Fabry-Perot laser arrays based on vertical p-i-n laser diode structures grown on InP layer directly bonded to Si wafer is presented. Lasing emission covering the C+L bands is achieved by means of a single-epitaxy Selective Area Growth (SAG) technology.

International audience

Epitaxial growth of high material quality $1.55\boldsymbol{\mu} \mathbf{m}$ AlGaInAs Multiquantum Wells Heterostructure on a directly-bonded InPoSi substrate has been developed for datacom applications.

Monolithic two‐terminal III‐V on Si dual‐junction solar cells, designed for low concentration applications, were fabricated by means of surface‐activated direct wafer bonding. The III‐V top cell is a heterojunction formed by an n‐Ga₀.₅In₀.₅P emitter and a p‐Al₀.₂Ga₀.₈As base. An efficiency of 21.1 ± 1.5% at one sun and 23.7 ± 1.7% at 10 suns is demonstrated, which to our knowledge is the best dual‐junction two‐terminal III‐V on Si tandem cell efficiency reported to date under verified reference conditions. The I‐V characterization of these 1‐cm² tandem cells under concentration required the development of a new method using a single‐source multiflash solar simulator and not perfectly matched component cells, also known as pseudo‐isotypes, formed by Si single‐junction cells and optical filters. In addition, the spectrum of the pulsed solar simulator was measured using a high‐speed CMOS spectrometer, allowing the calculation of the spectral mismatch correction factor. Merging these two techniques results in the hybrid corrected pseudo‐isotype (HCPI) characterization method, which shows a fast and accurate performance with a simplified procedure based on a single‐source solar simulator. Pseudo‐isotypes are easily adaptable to new cell designs by simply using a different filter, hence allowing the characterization of new multijunction solar cell architectures.

MOVPE regrowth of III-V materials on a directly-bonded InP-SiO2/Si (InPoSi) membrane is of particular interest to transpose the III-V mature multi-regrowth technologies [1][2][3] from the InP substrate classical platform into the hybrid III-V on Si platform [4]. MOVPE requires high-temperature elevation, typically above 600°C. We have shown for the first time void formation in a directly bonded InPoSi membrane at high temperature (400°C) despite the use of a thick oxide at the bonding interface [5]. The demonstration of highly efficient outgassing trenches under high temperature annealing as well as MOVPE regrowth of a high-quality III-V heterostructure was obtained. Subsequent improvements in the treatments of the bonded surfaces allowed to achieve MOVPE regrowth of high-quality III-V material without the use of any outgassing methods [6]. In particular, a compressive strain of 400 ppm at growth temperature was shown for the first time by curvature measurements carried out during growth. The latter is due to the difference of thermal coefficients between InP and Si [7]. Despite this thermal strain, a 3 μm-thick laser structure was successfully grown on InPoSi and compared to the same structure on InP as a reference [8]. Device performance are similar for both structures showing that there is no penalty induced by regrowing μm-thick structures onto InPoSi in spite of the thermal strain. References [1] V. Rustichelli et al., “Monolithic integration of buried-heterostructures in a generic integrated photonic foundry process,” IEEE J. Sel. Top. Quantum Electron., vol. 25, no. 5, Sep. 2019 [2] N. Dupuis et al., “10-Gb/s AlGaInAs Colorless Remote Amplified Modulator by Selective Area Growth for Wavelength Agnostic Networks,” IEEE Photonics Technol. Lett., vol. 20, no. 21, pp. 1808–1810, 2008. [3] H. Debregeas et al., “TWDM-PON Burst Mode Lasers with Reduced Thermal Frequency Shift,” J. Light. Technol., vol. 36, no. 1, pp. 128–134, Jan. 2018. [4] B. Szelag et al., “Hybrid III–V/Silicon Technology for Laser Integration on a 200-mm Fully CMOS-Compatible Silicon Photonics Platform,” IEEE J. Sel. Top. Quantum Electron., vol. 25, no. 5, pp. 1–10, Mar. 2019. [5] C. Besancon et al., “Kinetic study of hydrogen lateral diffusion at high temperature in a directly-bonded InP-SiO2/Si substrate,” Nanotechnology, vol. 31, no. 13, p. 135205, Mar. 2020. [6] C. Besancon et al., “Epitaxial Growth of High-Quality AlGaInAs-Based Active Structures on a Directly Bonded InP-SiO2/Si Substrate,” Phys. Status Solidi Appl. Mater. Sci., vol. 217, no. 3, Feb. 2020. [7] K. Takeda, S. Matsuo, T. Fujii, K. Hasebe, T. Sato, and T. Kakitsuka, “Epitaxial growth of InP to bury directly bonded thin active layer on SiO2/Si substrate for fabricating distributed feedback lasers on silicon,” IET Optoelectron., vol. 9, no. 4, pp. 151–157, 2015. [8] C. Besancon et al., “Comparison of AlGaInAs-Based Laser Behavior Grown on Hybrid InP-SiO₂/Si and InP Substrates,” IEEE Photonics Technol. Lett., vol. 32, no. 8, pp. 469–472, Apr. 2020.

This paper reports novel characteristic features of thermally-passivated Si nanoelectromechanical (NEM) beams fabricated via SOI-CMOS compatible processes with top-down hybrid EB/DUV lithography. Considerable difference of the resonance frequencies between the measurement results of the NEM beams with various lengths and the finite element simulation results suggests that effects of the undercut of the beam supports are serious for sub-micron beams. The resonance frequency of 332.57 MHz observed for an 800-nm-long beam is, to our knowledge, the highest ever as the fundamental resonance mode of lithographically-defined Si NEM beams. Clear change of the temperature dependence of the resonance frequencies with the varied beam lengths, observed for the first time, can be explained by considering effects of thermally-induced strain on the longer beams at higher temperatures.

In this study, fabrication of monolithic triple junction (3J) GaInP/AlGaAs/Si solar cells is reported by different wafer bonding approaches: (i) the most straightforward, direct GaAs/Si wafer bonding; (ii) an innovative 2-step approach combining epitaxy of GaAs bonding layer on Si cell followed by GaAs/GaAs direct wafer bonding; and (iii) Surface-Activated GaAs/Si wafer Bonding (SAB). Bonding interfaces properties are comparatively studied, and the performance of resulting III-V on Si triple junction devices is examined. Open-circuit voltages close to 2.9V are obtained in all cases, but large differences in fill factors between the bonding methods are observed, probably due to the presence of an oxide layer.

session poster (I43); International audience; Monolithic two-terminal III-V on Si dual-junction (2J) solar cells were fabricated by means of Surface-Activated direct wafer Bonding (SAB). Al 0.2 Ga 0.8 As single-junction cells are grown on GaAs substrate by Metal-Organic Vapor Phase Epitaxy (MOVPE) and bonded at room temperature to independently fabricated Si solar cells. The n+-GaAs//n+-Si bonding interface is characterized by Transmission Electron Microscopy (TEM) revealing a 2-3 nm thick amorphous interlayer. The performance of the 1 cm 2 tandem cells, designed for low concentration applications, was studied by External Quantum Efficiency (EQE) and J-V measurements showing a power conversion efficiency of 17% under one-sun AM1.5G spectrum. To our knowledge, this is the highest efficiency ever reported for a wafer-bonded 2J III-V on Si solar cell. Limitations to performance have been identified and therefore higher efficiencies are expected.

Tandem GaInP/GaAs//Si(inactive) solar cells were manufactured by direct wafer bonding under vacuum. At this early stage, an inactive silicon substrate was used (i.e. n+ Si substrate instead of an active n-p Si junction). Bonded devices presented an S-shaped J-V curve with a kink close to Voc caused by a built-in potential barrier at the III-V//Si interface that reduces the fill factor and therefore the efficiency of the device by 7% compared to the stand-alone GaInP/GaAs tandem cells. Nevertheless, losses in Jsc and Voc caused by the bonding process, account for less than 10%. AlGaAs single junction cells, designed to be bonded on a silicon cell for low concentrator photovoltaics (LCPV), were also manufactured reaching an efficiency of 15.9% under one sun AM1.5G spectrum for a 2cm2 cell.

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations associated to such devices integration as well as their potential applications.

This article highlights some aspects associated with the fabrication of stacked nanowire metal oxide semiconductor field effect transistors (MOSFETs) and more precisely the active area conception. These novel architectures, with gate-all-around or independent gates (ΦFET), are promising solutions to improve electrostatic control with high on-current (Ion) and to reduce power consumption for sub-32-nm transistors. Their fabrication is highly complex regarding lithography and etching. For this study, stacked nanowires were achieved by using hybrid lithography (e-beam/deep ultraviolet) combined with anisotropic and isotropic etchings of a Si∕SiGe multilayer to form suspended silicon nanowires. Therefore, we needed high aspect ratio resist features in order to perform the anisotropic etch of the Si∕SiGe multilayer (thickness: 250nm). For this purpose, we compared two ways to pattern the sub-32-nm silicon stacked nanowires. On one hand, a resist trimming was performed on thick large critical dimension patterns...

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.

International audience; We report here the first realization of top-down silicon nanowires (SiNW) transduced by both junction-less field-effect transistor (FET) and the piezoresistive (PZR) effect. The suspended SiNWs are among the smallest top-down SiNWs reported to date, featuring widths down to ~20 nm. This has been achieved thanks to a 200 mm-wafer-scale, VLSI process fully amenable to monolithic CMOS co-integration. Thanks to the very small dimensions, the conductance of the silicon nanowire can be controlled by a nearby electrostatic gate. Both the junction-less FET and the previously demonstrated PZR transduction have been performed with the same SiNW. These self-transducing schemes have shown similar signal-to-background ratios, and the PZR transduction has exhibited a relatively higher output signal. Allan deviation (σA) of the same SiNW has been measured with both schemes, and we obtain σA ~ 20 ppm for the FET detection and σA ~ 3 ppm for the PZR detection at room temperature and low pressure. Orders of magnitude improvements are expected from tighter electrostatic control via changes in geometry and doping level, as well as from CMOS integration. The compact, simple topology of these elementary SiNW resonators opens up new paths towards ultra-dense arrays for gas and mass sensing, time keeping or logic switching systems on the SiNW–CMOS platform.

This paper reports the design, fabrication and characterization of NEMS resonator arrays along with their associated readout scheme enabling the probing of all the resonators within an array. The successful monitoring of arrays of 20 NEMS in both air and vacuum is presented and the significant advantage these arrays provide over individual resonators for mass and gas sensing is discussed. Arrays of 20, 49 and 100 resonators have been designed and characterized in terms of Signal to Background Ratio (SBR) of the NEMS frequency response and Allan Deviation (ADEV) for the frequency stability of the resonators. While probing an array in closed loop, mass additions onto the NEMS were simulated by electrostatically-induced frequency shifts. These shifts were applied simultaneously on the entire array to demonstrate the ability of this system to track the complete array in real time. On the other hand, a noise reduction at short integration times by a factor close to √N, where N is the number of resonators, has been obtained by averaging all the resonators' signal. The ability to control arrays of NEMS with a simplified routing and a reduced number of electrical connections is demonstrated and the great potential of NEMS arrays for gas and mass sensing applications is highlighted.

This work reports on the realization of the smallest Pirani gauge ever, based upon highly-doped silicon nanowires. This paper details the fabrication process and the characterization of the thermal properties of Si nanowires, such as thermal conductivity and thermal coefficient of resistivity for various working temperatures in the 300K-700K range. A dynamic transduction technique, based on the 3-omega measurement is described and the device performances (i.e. sensitivity and signal-to-noise ratio) are measured. With the tested devices a resolution below 5%/Hz1/2 is obtained in the 0.1mbar-1bar range.

A double-gate suspended silicon nanowire transistor (DGSSiNWT) is proposed for conduction-based chemical/biological sensing applications. The doping profile is uniform across the device without any junction. The suspended silicon nanowire (SiNW) provides a larger surface area that can be used to enhance the sensitivity. Two side gates, which work as the main gate and tuning gate, are separated from the SiNW by air gap and control the electrical conduction of the suspended structure. Using the tuning gate, we have optimized the operating point of device to achieve the highest sensitivity. The sensitivity, defined as the ratio of threshold voltage shift to tuning gate voltage variation, is observed to be up to 6.5. The estimated charge sensitivity of our devices is at least 20 times higher than the reported value for non-suspended SiNW transistors.

This paper reports on ultra-scaled single-crystal Si NEMS resonators (25–40nm thick) operating in the 10–100MHz frequency range. Their first monolithic integration at the front-end level with CMOS enables to extract the signal from background leading to possible implementation of direct/homodyne measurement, for high sensitivity sensing applications and portable systems.

Measurements of the gauge factor of suspended, top-down silicon nanowires are presented. The nanowires are fabricated with a CMOS compatible process and with doping concentrations ranging from 2 × 10 20 down to 5 × 10 17 cm −3 . The extracted gauge factors are compared with results on identical non-suspended nanowires and with state-of-the-art results. An increase of the gauge factor after suspension is demonstrated. For the low doped nanowires a value of 235 is measured. Particular attention was paid throughout the experiments to distinguishing real resistance change due to strain modulation from resistance fluctuations due to charge trapping. Furthermore, a numerical model correlating surface charge density with the gauge factor is presented. Comparison of the simulations with experimental measurements shows the validity of this approach. These results contribute to a deeper understanding of the piezoresistive effect in Si nanowires. (Some figures in this article are in colour only in the electronic version)

For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (L eff of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiple-level stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H 2 anneal), the extracted coulomb-limited mobility decreases whereas the surface roughness-limited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.

For the first time, interface properties between high-k and Si or SiGe nanowires (NWs) have been experimentally investigated by adapting charge pumping technique and low-frequency noise measurement. It is found that the interface state density (D it ) of circular Si NWs is ∼3 times higher than that of rectangular ones with a deleterious impact on the low field mobility. The oxide trap density in SiGe NWs is otherwise ∼3.5 times higher than that of Si NWs which limits the mobility enhancement for this material.

In this study, we have investigated the use of electron tomography for the characterisation of novel stacked Si nanowire 3D devices. There has been significant interest in recent years in applying this technique to semiconductor device structures[1]. As devices become non-planar, and features become smaller than TEM specimen thickness, 3D analysis is required.

A novel parameter extraction method is proposed to dissociate the current contributions of each channel in 3D Gate-All-Around multi-channel transistors. These devices, designed for CMOS low standby power architectures, exhibit well behaved characteristics and high performance. Our methodology is based on systematic measurements, numerical simulations and modeling. The substrate bias technique is used to turn ON and OFF the various channels and to remove the bottom channel contribution from the total measured current. Very high I ON / I OFF ratios (NMOS: 2.27 mA/μm for 16 pA/μm; PMOS: 1.32 mA/μm for 16 pA/μm) are obtained experimentally as a benefit from good short-channel mobility values in each type of channel. A mobility reduction is observed in long-channel GAA transistors.

For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.

Both CMOS scaling and NEMS sensor devices scaling converge to the same type of sub 100 nm objects. This opens new fields of application for IC chips integrating both complex signal treatment and very highly sensitive sensing functionalities.

Three level stacked Si nanowires transistors with HfO 2 /TiN/poly-Si gate all around stacks (transistors called hereafter 3NWG) were processed, thanks to a self-aligned process. A current gain of 4.3 for NMOS and 4.7 for PMOS compared to planar SOI was demonstrated for V D = 1.2 V and V G − V T = 0.8 V, thanks to a 3D integration scheme (stacked and aligned nanowires). Those 3NWG devices revealed a current gain of 4.9 for NMOS and 4.2 for PMOS for V D = 50 mV when getting rid of the access resistance impact. Thanks to capacitance measurements, we found an expected inversion charge gain per plan-view surface of 6.4, highlighting the potentiality of the 3NWG device. The split-CV technique was used to extract electron and hole effective mobilities. The transport in 3NWG (on etched surfaces) was compared to the one in planar SOI devices.

Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed

Suspended, stacked and rounded nanowires with diameters as small as 5nm have been obtained thanks to thermal oxidation. Those structures can be used for novel 3D Gate-All-Around Field Effect Transistor (GAAFET) architectures. As the oxidation rate is strongly affected by the nature of the oxidant, the temperature and the wire curvature, both wet and dry oxidations (at 950{degree sign}C and at 1100{degree sign}C, respectively) have been investigated. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) were used to characterize the shape and the oxidation kinetic of the oxidized Si nanowires compared to planar references.

Based on electrical measurements and transmission electron microscopy imaging we propose in this paper a possible explanation for the measured mobility degradation with gate length reduction in short-channel MOSFETs. The carrier mobility in end-of-range implantation regions was investigated in Silicon-On-Insulator (SOI) and tensily-strained Silicon-On- Insulator (sSOI) substrates. Wafers with ultrathin films (from 8 to 35 nm) were Ge implanted at various concentrations, then annealed. The Pseudo-MOSFET measurements showed a mobility decrease (from 5 to 34%) as the implantation dose increased. The results are relevant for the optimization of the sources and drains regions of advanced nano-scale SOI transistors.

We demonstrate the first implementation of a highly doped silicon nanowire electromechanical resonator that exploits the depletion charge modulation in a junctionless FET to transduce mechanical motion on-chip. The resonator, with a typical length between 1 and 2 µm, a total height of 44 nm and a total width of 65 nm, is coupled via two lateral 60 nm air-gap gate electrodes. A fundamental resonance frequency of 226 MHz is detected in the drain current. This device, showing full transistor functionality, is integrated in an SOI-CMOS platform using conventional 8″ inch wafer technology, which offers unique opportunities for ultra-low power sensing and signal processing platforms interfaced with CMOS on a single chip.