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Application of atop-surface imaging(TSI) process by silylation to ArF lithography is desirable for ULSI production with minimum feature size for sub-120nm. We evaluated lithographic performances of non-chemically amplified positive TSI photoresist and chemically amplified negative TSI photoresist, both based on phenolic polymer. When off-axis illumination was used, 120nm and 110nm L/S patterns were obtained with non-chemically amplified resist(non-CAR) and chemically amplified resist(CAR) respectively. 100nm L/S patterns of CAR were obtained with strong off-axis illumination using binary intensity mask. CAR was superior to non-CAR in terms of lithographic performances, but inferior to non-CAR in terms of resist pattern collapse. Line edge roughness(LER) of CAR was sufficiently minimized by optimizing silylation bake temperature and it was comparable to that of single layer resist. For the prevention of resist pattern collapse in dry development process, the property of adhesion and resist rigidity is impor ant. This results can help the design of matrix resin of TSI resist for sub-100nm lithography.

We report that, based on our experimental data, lens heating (LH) impact on wafer image can be effectively controlled by using a computational method (cASCAL) on critical device layers with no request on tool time. As design rule shrinks down, LH control plays a key role in preventing the image deterioration caused by the LH-induced wavefront distortion during exposure. To improve LH prediction accuracy, 3-dimension structure of mask stack (M3D) is considered in calculating the electro-magnetic (EM) field that passes through the mask for full chip. Additionally, lens specific calibration (LSC) is performed on individual scanners to take the lens-to-lens variation into account. In data comparisons, we show that cASCAL performs very well as an ASCAL substitute, and that M3D and LSC improve the LH prediction accuracy of cASCAL.

The combination of off-axis illumination (OAI) schemes with ‘weak’ phase shifting techniques is promising to improve the process latitudes of both dense and isolated features. In this paper, the performance of this combination to print 0.25 μm poly levels for logic circuits is investigated experimentally and by simulations, using DUV stepper ( λ = 0.248 μm , 0.42 NA ). Various resist types have been addressed, mainly with respect to proximity issues.

Patterning of contact hole using KrF lithography system for the sub 90nm technology node is one of the most challenging tasks. Contact hole pattern can be printed using Off-Axis Illumination(OAI) such as dipole or Quasar or Quadrupole at KrF lithography system. However this condition usually offer poor image contrast and poor Depth Of Focus(DOF), especially isolated contact hole. Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip CD variation reduction. The insertion of SRAF in a contact design is mostly done using rule based scripting. However the rule based SRAF strategy that has been followed historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow sustainable manufacturing. Especially in case of random contact hole, rule-based SRAF placement is almost impossible task. We have used an inverse lithography technique to treat random contact hole. In this paper we proved the impact of SRAF configuration. Inverse lithography technique was successfully used to treat random contact holes. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described. As a conclusion, we suggest methodology to set up optimum SRAF configuration with rule and inverse lithography technology.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Source Mask Optimization techniques are gaining increasing attention as RET computational lithography techniques in sub-32nm design nodes. However, practical use of this technique requires careful considerations in the use of the obtained pixilated or composite source and mask solutions, along with accurate modeling of mask, resist, and optics, including scanner scalar and vector aberrations as part of the optimization process. We present here a theory-to-practice case of applying ILT-based SMO on 22nm design patterns.

As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.

The lithographic performance of phase shifting and transmission masks are compared. This paper describes the ultimate resolution and process latitudes, that can be obtained by combining a phase shift mask with the DESIRE process at 248 nm. Special emphasis is put on the influence of coherence. Both simulation and experimental results are given.

Multiple focus exposures[1], optimization of the partial coherence[2–4] of the stepper and the use of surface imaging[5] have been studied as possible ways to improve depth of focus and exposure latitude for deep-UV lithography at sub-0.5 μm dimensions. Simulation and experimental results are compared. The multiple focus technique gives a marginal improvement in depth of focus, but at the expense of resolution and exposure latitude. Surface imaging combined with higher coherence factors gives the best resolution with the widest latitude.

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

As mask feature size decreases, etch bias control during Cr and shifter etch becomes more critical factor in Embedded Phase Shifter Mask (EPSM) mask making processes. Since the etching characteristics of the shifter materials, Molybdenum Silicide (MoSi), are sensitive to etching surface condition, Critical Dimension (CD) performance of the shifter layer strongly depends on incoming surface condition from Cr etch. In this paper, lateral etch component of MoSi etch was investigated as a function of various substrate conditions so that a new in-situ plasma treatment was suggested to control the CD bias during MoSi etch. The CD performance was characterized within the surface treatment plasmas and also correlated with some plasma parameters and substrate temperature. As a result, it was found that plasma surface modification could be an in-situ technique to better control the shifter CD in EPSM process and an essential option for redundancy tools in mask production environment.

Evaluation of lithography process or stepper involves very large quantity of CD measurements and measurement time. In this paper, we report on a application of Scatterometry based metrology for evaluation of binary photomask lithography. Measurements were made on mask level with ODP scatterometer then on wafer with CD-SEM. 4 to 1 scaling from mask to wafer means 60nm line on wafer translates to 240nm on mask, easily measurable on ODP. Calculation of scatterometer profile information was performed by a in-situ library-based analysis (5sec/site). We characterized the CD uniformity, linearity, and metal film thickness uniformity. Results show that linearity measured from fixed-pitch, varying line/space ratio targets show good correlation to top-down CD-SEM with R 2 of more than 0.99. ODP-SEM correlation results for variable pitch shows that careful examination of scatterometer profile results in order to obtain better correlation to CD SEM, since both tools react differently to the target profile variation. ODP results show that global CD distribution is clearly measurable with less outliers compared to CD SEM data. This is thought to be due to 'averaging' effect of scatterometer. The data show that Scatterometry provides a nondestructive and faster mean of characterizing lithography stepper performanceprofiles. APSM 1st level (before Cr removal) 'dual-space' CDs and EPSM rectangular contacts were also measured with and results demonstrates that Scatterometer is capable of measuring these targets with reasonable correlation to SEM.

As lithography mask process moves toward 45nm and 32nm node, phase control is becoming more important than ever. Both attenuated and alternating PSMs (Phase Shift Masks) need precise control of phase as a function of both pitch and target sizes. However conventional interferometer-based phase shift measurements are limited to large CD targets and requires custom designed target in order to function properly, which limits phase measurement. Imaging simulations, both, in a rigorous and a Kirchhoff regime, show the dependency of the phase in the image plane of a microlithography exposure tool on numerical aperture, polarization, and on the so-called balancing of the mask for features close to the size of the used wavelength. For these feature sizes, the image phase does not coincide with the etch depth equivalent phase calculated from the nominal depth and optical constants of the shifter material. Additionally, for PSMs generating phase jumps deviating from 180°, the resulting phase in the image plane of a microlithography exposure tool depends on the transmitted diffraction orders through the aperture of the imaging system. Consequently Zeiss, in collaboration with Intel, has started the development of a laterally resolving Phase Metrology Tool (Phame) for in-die phase measurements. In this paper we present this optical metrology tool capable of phase measurement on individual line/spaces down to 120nm half pitch. Alternating PSM, Attenuated PSM, Cr-less masks were measured on various target sizes and simulations were performed to further demonstrate the capability and implication of this new method to measure the scanner relevant phase in-die, taking into account NA, polarization, and rigorous effects.

Scatterometers are widely used for line/space or 2D structure measurements in both wafer and mask industries. This technology is now gaining more acceptance and is being applied 3D structures such as contacts and pads. Contact CDs and trench depth in photomasks are critical monitoring parameters in mask industry and are discussed here. We are reporting contact CDs and profile results measured from targets from Binary, PSM, and Crless plates. The strategies of model creation such as using simple trapezoid versus more advanced shapes affect how well SWA and footings can be measured and reported from these structures. We are reporting CD and profile information obtained with Scatterometer, and then comparing CD SEM, AFM, and cross section SEM. Multiple different modeling configurations were used with different levels of complexity, and we report on optimum modeling strategy to obtain profile information from 3D structures. The relationship between the modeling strategy versus cross correlation between different parameters is discussed. CD linearity, uniformity, and other correlation parameters to the reference CD SEM tool are reported. Target CDs ranged from 60nm up to 600nm. CD uniformity reported from Scatterometry is 20~30% less than that from CD SEMs. This CD uniformity improvement is due to the fact that scatterometer beam samples dozens to hundreds of samples and 'averages' profile parameters, thus eliminating local effect such as line edge roughness. Contact depth are also measur ed and compared to AFM, in which the bias between the two tools are usually around 3nm or less. In terms of smallest target CD measurable, in this paper we report routine measurement of small contacts with middle CD down to 65nm (bottom CD close to 50nm) with both RP and SE mode. Application of scatterometry method to mask contacts and pads leads to accurate and fast measurement of 3D profiles, and opens up possibility of in-line monitoring of profile information due to the higher runrate compared to traditional metrology tools. Keywords: contacts, scatterometry, metrology, binary, PSM, Crless.

Linewidth and etch depth control on the photomask is rapidly becoming a major concern in mask processing. In this paper, we report on a Scatterometry based metrology system that provides line width and etch profile measurements on Embedded PSMs on Intel's 65nm and 45nm node test masks. Measurements were made with Nanometric's Atlas-M reticle measurement system. Spectrum data obtained from plates were analyzed using Timbre Technologies’ ODP analysis software. We characterized the CD uniformity, linearity, sidewall angle and thickness uniformity. Significant reduction in time per measurement is achieved when compared to CD-SEM. ODP Scatterometry reported a 2x reduction in the CD Uniformity compared to that reported from the SEM. This reduction is typically due to outliers reported by the CD-SEM that is averaged out in ODP Scatterometry. Good correlation to top-down CD-SEM and cross-sectional SEM is reported. R-squared correlation of >0.99 (ODP scatterometry to top down CD-SEM) is reported. Profile measurements from ODP show excellent match to cross-section SEM. The data show that Scatterometry provides a nondestructive way to monitor basic etch profile combined with relatively little CD metrology lag.

Control of line width and profile is gaining more importance in photomask processes as the industry moves toward 45nm node and beyond. In this paper we report scatterometer measurements of CD and profile data from chrome-less mask profile processed using Intel's 65nm and 45nm node technology. As opposed to the highly charging nature of chrome-less plate during CD SEM measurements, scatterometry provides a non-charging optical alternative to measure critical CDs. As for trench depth measurement, scatterometry has big advantage over AFM with its much higher throughput (about 5 seconds vs. >2min). Since quartz plate is very transmittive to lights, we use eliipsometer-based scatterometry instead of conventional reflective-photometer based one. Parameters characterized in this study include line/space CD, contact CD, and trench depth. Correlation to top-down CD-SEM, cross-sectional SEM, and AFM is reported. Line CD uniformity reduction is more than 30% compared to that from CDSEM, due to averaging effect of scatterometry as well less lack of charging during measurements. Depth bias to AFM was around 3nm in both DCCD and FCCD height measurements we performed. The data show that Scatterometry provides a nondestructive way to monitor basic etch profile combined with relatively little time loss from measurement step.

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography. As the requirement on critical dimension (CD) and side wall profile control becomes ever stringent as minimum feature sizes keep shrinking following the Semiconductor Industry Association (SIA) roadmap, the patterning of the EUV mask absorber material, cost of ownership (COO) of mask, and the capability for defect free EUV masks become the crucial path in enabling the overall success of EUV lithography. The purpose of this study is to understand the etch characteristics in TaN-based EUV mask absorber etch, which will enable us to determine robust process condition in terms of CD performance and profile control. In this paper, CD bias performance in TaN-based EUV mask absorber etching is investigated within inductively coupled plasma (ICP) of fluorine-containing and chlorine-containing gas chemistries. The effects of etch parameters, such as plasma source power, bias power, and pressure, on the CD bias are evaluated through design of experiments (DOE). Some other etching characteristics like etch rate and selectivity are also correlated to the CD performance and etch profile to understand the basic etch mechanism in TaN etch. Latest etch results of the TaN-based absorber are also presented.

High resolution etching of MoSi for photomask processing places new requirementson etching processes. As resist features are sized to 100nm and below, it is firstnecessary to duplicate these features first into a chrome over-layer. After resist isstripped, this chrome over-layer is used for etching MoSi. Both chrome and MoSietched profiles require near-vertical sidewalls, good CD (critical dimension)uniformity, good linearity, and CD mean-to-target (MTT). Additional requirementsof etched MoSi include minimal roughness on exposed quartz, selectivity to chromeand quartz, phase angle target and phase angle uniformity, etch depth globaluniformity, and etch depth uniformity as a function of feature size.An ETEC integrated process is used for the application of resist, patterning, and allsubsequent processing. Chemically amplified resist is patterned with the 50kVMEBES ® Quadra ™ or MEBES eXara ™ raster scan electron beam writer, allowing forpatterning of small features with vertical resist profiles. Plates are etched in a Tetra

Electron beam (e-beam) proximity effect correction (PEC) has become a critical consideration with the reduction of feature sizes and the increasing use of optical proximity effect correction (OPC). PEC is accomplished on the 50kV MEBES eXara system with the embedded PEC (emPEC) technique, which is an automated version of GHOST. This method equalizes the background exposure by writing a fifth pass in the reverse tone of the four primary exposure passes. This compensates for the dose differences in the background due to backscattered electrons. The result is feature size control independent of the proximity and density of surrounding features, and independent of feature size. The method is simple and does not require additional computations for raster scan systems. A description of the method and its results for both coverage proximity effect correction (feature size deviation as a function of the surrounding exposure density) and CD linearity (deviation of different feature sizes) is presented.

Photo mask etching for the 100nm technology node places new requirements on dry etching processes. As the minimum-size features on the mask, such as assist bars and optical proximity correction (OPC) patterns, shrink down to 100nm, it is necessary to produce etch CD biases of below 20nm in order to reproduce minimum resist features into chrome with good pattern fidelity. In addition, vertical profiles are necessary. In previous generations of photomask technology, footing and sidewall profile slope were tolerated, since this dry etch profile was an improvement from wet etching. However, as feature sizes shrink, it is extremely important to select etch processes which do not generate a foot, because this will affect etch linearity and also limit the smallest etched feature size. Chemically amplified resist (CAR) from TOK is patterned with a 50keV MEBES® eXara e-beam writer, allowing for patterning of small features with vertical resist profiles. This resist is developed for raster scan 50 kV e-beam systems. It has high contrast, good coating characteristics, good dry etch selectivity, and high environmental stability. Chrome etch process development has been performed using Design of Experiments to optimize parameters such as sidewall profile, etch CD bias, etch CD linearity for varying sizes of line/space patterns, etch CD linearity for varying sizes of isolated lines and spaces, loading effects, and application to contact etching. Etch processes have been developed specifically for etching small features, but these are also applicable to etching of larger feature sizes. Etch processes are capable of patterning of chrome features below 100nm with vertical sidewalls, 1μm. Excellent uniformity and reproducibility are also demonstrated. SEM micrographs illustrate processes applicable to small feature etching, along with processes that are limited to large feature etching. In this paper, we will discuss CD uniformity, sidewall profile, etching bias, loading effects, and linearity and how these relate to small-feature chrome etching.

This paper describes that attenuated phase shift masks (APSM) improve process margin compared to binary mask (BIM) in KrF and ArF lithography. We present the real problems to occur in the mask fabrication, process and mask error factor (MEF). As a result, sub-120nm cell patterns were delineated with 8% exposure latitude (EL) and ~0.6 ?m local depth of focus (LDOF) using 0.70NA KrF and APSM. The performance of ArF lithography (NA=0.63) shows the similar process margin with 10% EL and -0.6 ?m LDOF. Using APSM, we could obtain 14.4% EL and -0.6 ?m LDOF. We obtained process enhancement of 30% by using APSM. However, process instability is analyzed in a viewpoint of mask making and process issue such as mask fabrication capability, CD uniformity, and MEF. In simulation and experiment, 0.63NA ArF lithography shows resolution improvement compared to 0.70NA KrF. It is possible to obtain lOOnm pattern using ArF and APSM. Also, one of common issues is to reduce the MEF, which is decided by exposure and resist process condition. MEF is increased to about 4 or more in the sub-120nm range. This effect has influence on CD uniformity and EL margin. Reducing the MEF on the wafer, we have to optimize exposure tool, process, and mask. Shorter wavelength and APSM are one of candidates to minimize MEF. Therefore, ArF APSM is looking forward to high performance lithography.

The patterning potentialities of sub-100nm pattern for ArF lithography was evaluated with conventional alternating PSM (alt-PSM) for dense lines and spaces (L/S) and phase edge PSM (PE-PSM) for isolated lines of memory device. In dense L/S pattern,110nm pattern was defined with relatively small depth of focus(DOF) window(~ 0.2 ?m) due to phase error of mask. As pattern sizes was changed from 130nm to 200nm, critical dimension (CD) difference between two neighboring spaces was varied and it was assumed that micro loading effect was occurred in Qz etching. The linearity was guaranteed to dense L/S of 110nm and isolated line of 90nm, and Iso-Dense bias was controlled within 15nm. The 60nm and 70nm isolated lines of PE-PSM ware defined with good process windows in the case of OA_X size(X-direction size of Cr open area) of 0.5 ?m. The 55nm isolated line was also defined. The pattern shift of isolated lines was occurred with 4~7nm as phase of mask was varies within 190 ~ 200 ° . Though the alt-PSM with high numerical aperture (NA) for ArF lithography was strong candidates for sub-1 OOnm lithography of memory device, the issues of mask fabrication such as tighter phase control and minimizing etch loading effect would be big obstacles. On the contrary, there were many possibilities of sub-100nm patterning in PE-PSM with good process windows, however tighter control of pattern shift due to phase error must be studied intensively.

Optical lithography at resolution limit is a non-linear pattern transfer. One of the important issue is a mask critical dimension control because of nonlinear amplification of mask critical dimension error during image transferring on wafer. This amplification of mask error is called the MEF. This mask error factor has been widely used as an important parameter for indicating tighter CD control for the photomask for low-kl lithography generation.

We estimated the process margins of various cell structures and process problems for full chip process under extremeresolution limit of exposure tool. Therefore, optimizing off axis illumination (OAI) condition for various structures obtainedthe fme pattern and wider process margin using simulation and experiment. From our experiment, we should use as highernumerical aperture (NA), smaller R and smaller r as possible to reduce critical dimension (CD) difference between denseand isolated patterns. Process margins are obtained more than 8% exposure latitude (EL) and 0.5 tin depth of focus (DOF)for each cell. However, we can consider using of attenuated phase shift mask (PSM) to improve the exposure and DOFmargin. We fmd that real full chip process induces the critical problems such as isolated line (I/L) and space (L'S) patternvariation due to lens aberration, partial coherence effect, mask error effect, and optical proximity effect. These effects playa role to determine the design rule of cell and periphery structures. In spite of good lens quality, variation of I/L and USpattern for various exposure conditions is almost 4Onm or more compared to line and space (L/S) pattern. These phenomenaare becoming the critical issue to fulfill the full chip process of l3Onm lithography. By optimizing mask error effect,isolated and dense pattern bias (ID bias), and OAI, we can achieve l3Onm technology with 248nm KrF lithography.KEYWORDS : KrF, Design rule, ID bias, OAI, Full chip process, High NA, Process margin

In this paper we investigated the feasibility of printing sub-0.13 micrometers device patterns with ArF and KrF lithography by using experiment and simulation. To do this we evaluated various cell structures with different sizes from 0.26 micrometers to 0.20 micrometers pitch. In experiment 0.60NA ArF and 0.70NA KrF exposure tools, commercial and in house resists and bottom anti-reflective coating (BARC) materials are used. To predict and compare with experimental data we also used our developed simulation tool HOST base don diffused aerial iamge model. We found that ArF lithography performance is a little bit better than KrF and therefore 0.70NA KrF lithography can be used up to 0.12 micrometers design rule device and 0.60NA ArF lithography can be used up to 0.11 micrometers . But to get more than 10 percent expose latitude, 0.13 micrometers with KrF and 0.12 micrometers with ArF are the minimum design rule size. However to obtain process margin we had to use extreme off-axis illumination (OAI) which results in large isolated- dense bias and poor linearity including isolated pattern. Using higher NA can reduce ID bias and mask error factor. For contact hole it is more effective to use KrF lithography because resist thermal flow process can be used to shrink C/H size. Our developed ArF resist and BARC shows good performance and we can reduce k1 value up to 0.34. Through this study we verified again that ArF lithography can be applied for sub-0.13 micrometers device through sub-0.10 micrometers with high contrast resist and 0.75NA exposure tool.

Ultimate limitation of lithography has been studied by using the diffused aerial image model (DAIM). Assuming that only the 0th and 1st order diffraction beams in the off-axis illumination technique contribute to the resist patterns, aerial image is calculated for dense line and space patterns. And then DAIM is applied to achieve final image. By using this diffused aerial image, exposure latitude and mask error effect can be analyzed quantitatively. In the case of perfect image, which can be achieved from, for example, diffraction free x-ray lithography or electron beam lithography without Coulomb repulsion and back scattering effect, same approaches are possible to get the exposure latitude and mask error effect. Under the validation of DAIM, most important parameter, which characterizes dense L/S patterns, is the diffusion length of acid. In order to realize sub-o.1 micrometers pattern with enough process margins, it is required to enlarge exposure latitude and to reduce mask error effect. Therefore, reducing h acid diffusion length of chemical amplification resist (CAR) or new conceptual resist instead of CAR will be needed for sub-0.1 micrometers era.

Recently, the miniaturization of the design rule of memory devices pushes the minimum feature sizes down to sub- wavelengths of the exposure tools. The design of a memory device comprises not only the dense patterns with critical small size in the cell region but also the random patterns in the peripheral region; the latter also need sub- wavelength lithography technology as well as the former. And the optical proximity correction (OPC) has been strongly required for the random patterns in the peripheral region where the same energy is exposed as in the cell region. Therefore, the high accuracy of simulation model used in the OPC is necessary for the full chip OPC tools. However traditional aerial image simulation has a limitation to the application due to its lack of accuracy because it does not take into account a resist process. We introduced novel lithography simulation model in 1998, which describes resist process by diffusion and chemically amplification function.

ArF DUV ((lambda) equals 193 nm) lithography is rapidly emerging after 248 nm lithography because of the demand for further resolution improvement and wider Depth Of Focus (DOF). However, the 193 nm lithography requires innovative development in various areas, such as laser sources, resist chemistry, new PSM shifter materials, and optics materials. In this study, we evaluated TiSi-nitride based new attenuated PSM in terms of mask making process and its lithographic performance for ArF lithography. We used two kinds of TiSi- nitride based attenuated PSM blanks having 6% and 9% transmittance, respectively. Chemical durability of TiN/SiN film was evaluated. We selected optimal dry etching condition for mask making with good mask profile (side wall angle greater than or equal to 85 degrees) and Quartz (Qz) substrate roughness. The DOF margin at 9%-PSM was larger than those of others (6%-PSM and BIM) and Exposure Latitude (EL) of PSM was larger than that of BIM. Therefore, we concluded that TiSiN- based attenuated PSM was effective for ArF lithography.

Photomask is one of the most critical technologies for lithography. Optical lithography at resolution limit is a non- linear pattern transfer process. OPC (Optical Proximity Correction) technology has been used in the semiconductor industry for controlling the shape of pattern, and eliminating the line shortening and corner rounding effects for submicron feature. Therefore, OPC technology is an approach for improving lithography performance that has been received much attention recently. We investigated the lithographic performance in terms of EL (Exposure Latitude), DOF (Depth of Focus), and mask error effects for various mask fabrication. It was observed that mask error gave severe influence on the lithographic performance and the OPC simulation error also strongly depended upon the mask quality.

We have investigated the perfomiances of positive Chemically Amplified Resist (CAR) withHigh Acceleration Voltage System on mask fabrication, widely. As we had expected, the resolutionand pattern fidelity both after development and after etching were improved dramatically, because ofits high contrast and good dry etching durability. As a result, practical resolution limitation was O.2pmand CD linearity for O.2.tm 1.O}.xm pattern range was O.034pm with Proximity Effect Correction(PEC). We obtained CD uniformity of3 l55nm, to 120X120mm2 area.Keywords : Chemically Amplified Resist (CAR), High Acceleration Voltage E-beam System,Resolution Limitation, Linearity, Uniformity, Proximity Effect Correction (PEC),Optical Proximity Correction (OPC) 1. INTRODUCTION Even though the PBS process extends its life by applying thin resist coating, it is quite difficult to define sub-micron pattern on mask because of low contrast and wet etching requirements. As dry etching resistance is not so excellent' and data sizing (over process) isindispensable, ZEP resist process is not enough to apply it to technology below O.6tm, also.The most promising candidate for sub-micron pattern is combination2 of 1) CAR process,which has already been developed and adopted in wafer process in spite of severe process

Critical issues for 150nm DUV lithography using 0.70 NA KrF and 0.60 NA ArF had been investigated. Aberration, coherence variation, mask error effect, and process margin for each case had been analyzed. Current projection lens and illumination optics are getting better and better. However, for 150nm lithography using high NA scanner, a large portion of beam should be traced on the outside of lens pupil and traced on the resist surface with a large incident angle. In such a case, lens aberration effect was observed on field edge, even though strehl ratio of projection lens and coherence variation on field edge had been improved. These effects had been investigated. One other critical issue in high NA scanner is depth of focus. The common depth of focus between dense and isolated patterns in real process using high NA scanner is mainly affected by photoresist thickness. That issue had been also investigated. Another important issue for 150nm DUV lithography is mask error effect. In the case of same design rule, lower (lambda) /NA lens is more favored than higher (lambda) /NA. Mask error issue in high NA KrF and ArF was also analyzed. Total comparisons between high NA KrF and 0.60 NA ArF have been discussed.

With KrF and off-axis illumination (OAI) technique we should set up 150nm lithography process without using phase shift mask. But isolated-dense bias (ID bias) makes 150nm lithography process difficult. We investigated ID bias trend at different OAI condition and found that it could be reduced by optimizing OAI condition. We represent OAI as quadrupole center (sigma) R and pole size radius r. With high NA, small R and small r we can reduce ID bias but cannot eliminate completely at 150nm lithography. Also we found out that ID bias of duty patterns are more severe than that of dense and isolated patterns. Using OAI at a certain space width between lines, the width of lien has its minimum. This line thinning phenomena at this weak zone depends on OAI condition such as NA, R and coherence value. We compared simulation data with experimental result and could see the same phenomena at simulation data. Therefore OPC is necessary to avoid this weak zone. By experiment and simulation with NA higher than 0.65 and Optical Proximity Correction, we could set up 150nm lithography process with below 0.20micrometers periphery pattern design rule.

In order to improve the overlay accuracy in electron beam lithography, we have investigated the optimization of alignment key that included a ratio of alignment key according to scanning beam size, an optimum key depth/width, and material's dependency. The alignment repeatability of key, has the same ratio with scanning beam size, appears good results as compared with the other ratio. Scanning beam size also correlates with an alignment key width. As a process sequence of CMOS device, the key width of under layer is changed by the thickness of deposited materials, because of the deposition on side-wall. Therefore, the scanning beam size should be optimized for each step. In each material, there exists the critical thickness not affecting on the alignment reading repeatability. The standard deviation(3 σ), which is calculated by measurement of key position with critical thickness, is less than 20nm. We have results of the critical thickness of various materials. Si02 and Si3N4 do not affect on the alignment signal, but doped WSix, Al, and doped poly-silicon are very sensitive because of back-scattering electrons. Using the optimized align key of WSix/doped poly-Si, the standard deviation (3 σ) was less than 10nm. Otherwise, non-conducting layer must be etched more than 7000A. In this case, the standard deviation(3 σ) is larger than that of conducting materials, as more than 20 nm. We have results of optimum condition of alignment key in order to enhance the overlay accuracy. The standard deviation(3 σ) of total overlay accuracy is less than 50nm which corresponds to 150nm design rules device fabrication.

We have investigated the effect of line edge roughness (LER) of active patterns used for shallow trench isolation to the electrical performance of MOS transistor applicable for 1 giga-bit DRAM. Three different processes for resist patterning were applied for comparative analysis to form the active pattern in MOS transistor; the first method applied a conventional single layer resist (SLR) process, the second TIPS with two step dry development, and the third another TIPS with three step dry development. The third process adopted an additional step to break-through thin silicon dioxide which may contribute to the LER. The LER data of an active pattern before and after nitride substrate etching and their profiles were investigated among these processes. The third method shows the almost same LER and CD uniformity of the active pattern as those of SLR. The electrical properties. Only, threshold voltage variation of MOS transistor by the second method shows the worse results than those of SLR. Considering the ratio of LER in isolated active pattern with channel width of 0.3 micrometers to its average CD value, we think that its ratio should be controlled well below 7 percent for TIPS to make an useful technology for real device. Based on these studies, we believed that the well-controlled TIPS process using three step dry development is a strong candidate for device production of ArF and EUV lithography, if the advantages of TIPS technology over the SLR process are considered in the respect of lithography.

Optical proximity correction technique has been studied. The occurrence of proximity effect in the optical lithography is composed of an element caused by diffraction of light, which can be explained by aerial image simulation, and an element caused by resist process, in which acid diffusion is a major factor causing non-linearity. In the case of very thin resist, absorbed energy that generates the acid can be described by two-dimensional instead of three-dimensional distribution. Under this simple assumption, acid diffusion by post exposure bake is equivalent to the diffusion of aerial image, and chemical amplification can be analytically described also. Modified aerial image including diffusion and chemical amplification, we call it diffused aerial image, can give the information for patterning status directly. Therefore, diffused aerial image model can explain experimental results very well compared to the expectation by using aerial image only without loss of simplicity and calculation speed.

Causes of intra field critical dimension variation using KrF scanner for 0.18 micrometer lithography have been investigated. Scanner is different from traditional stepper system. Scanner might have synchronization error, which results in degrading contrast over full intra field. Aberration of illumination optics brings about coherence difference between field center and edge. In a scanner system, vertical patterns (cross scan direction) are geometrically tangential, and horizontal patterns are sagittal. Such a H/V different ray tracing results in horizontal pattern having better contrast than vertical one under diffraction limited design rule patterning. Mask error can be a very critical issue in 4X system. Focus drift and exposure dose change during scan exposing result in intra field CD variation, and some stray light is a cause of intra field CD variation also.

The most critical issues for lithographers, resolution, depth of focus, exposure latitude and proximity effect, have been frequently discussed. In addition to those issues, lens aberration effects such as astigmatism, coma, field curvature and distortion have been emphasized in view of process stabilization. Deep UV lenses have undergone improvements in the field curvature, distortion, and other aberrations to the point that they can be implemented for near quarter micron patterning. KrF excimer laser stepper and scanner have made Deep UV technology as a practical choice for lithographers to develop their own DRAM processes. In order to adopt process development beyond the region of ultimate resolution limit, precise lens aberration analyses are necessary. KrF excimer laser stepper (NA equals 0.55), used for 0.18 micrometers design rule patterning, is examined. Several types of real device pattern, such as word and bit line, active, storage node, contact hole patterns, are tested under various illumination conditions (conventional, various partial coherence, off-axis illumination). These results are compared with simulation results.

Modified illumination scheme such as off-axis illumination or low partial coherence illumination in combination with phase shift mask is very reliable technique even to the manufacturing stage. In spite of its benefit of drastic improvements in resolution and depth of focus, it has several well known drawbacks. Those are pattern structure dependency, increased proximity effect and significant degradation of illumination power. Furthermore, several studies are reported about the distortion-like registration error between each illumination aperture while various apertures are mix-used. However, the origin of this distortion-like overlay errors is still uncertain and just considered as having some relationship with lens aberration probably, coma. In this study, we investigated the nonlinear character of the registration errors and try to find out the implicit relations of its to the lens aberration character through experiments and simulations.

In order to develop 1 G bit DRAM of 0.18 micrometers design rule, it is required to generate 0.2 micrometers contact hole patterns with local DOF over 1.0 micrometers . One of good candidates is DUV attenuated phase shift mask (PSM), which improves the lithographic process margin such as depth of focus (DOF), especially in contact hole patterns due to edge enhancement effect. In the case of DUV attenuated PSM, the optimum condition for contact hole patterns near 0.2 micrometers has been investigated by simulations and experiments using chromium- based attenuated PSM with the transmittance of 6% at 248 nm wavelength. We obtained local DOF of 1.2 micrometers for 0.2 micrometers contact hole of 1 G bit DRAM with printing bias of -0.046 micrometers using KrF laser system (0.31 (sigma) , 0.55 NA). We evaluated the characteristics of contact hole with various duty ratios and defect printability using programmed defects.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

An attenuated phase shift mask (PSM) is the most promising candidate for the high volume production lithography process among the various PSM types. It has been shown that attenuated PSM improves the lithographic performance such as depth of focus, especially in contact window by its edge enhancement. In this paper, the side lobe effect that restricts the lithographic performance of attenuated PSM and the light intensity distribution have been examined on changing the pattern density and the transmittance by experimental and simulation. The side lobe effect caused by proximity effect is very severe when pitch sizes are in the range of 0.7-0.9 micrometers for 0.35-0.45 micrometers contact hole on mask and it is enlarged by defocus exposure condition. The side lobe effect in this range of pitch size may forms the additional pattern in wafer, which restricts the application of attenuated PSM. The side lobe effect can be removed by additional pattern positioning at the center of four contact hole patterns, but simulation result of Exposure-Defocus tree (E-D tree) shows that lithographic performance of attenuated PSM is decreased by an auxiliary pattern. In the application of attenuated PSM in dense pattern, the relation between performance and side lobe effect is mutually contradictory.

The optical lithography is extending its life by combining high numerical aperture (NA) optics and shorter wavelength. The shorter wavelength lithography has required the new developments of related technologies. In particular, DUV resists require an entirely different resist chemistry. Much progress has been demonstrated in the field of transparent chemically amplified resists with high sensitivity. However, this DUV lithography ((lambda) equals 248 nm) has been delayed for mass production due to their limitations, such as (i) delay time effects, (ii) high cost ownership due to expensive resist materials and laser maintenance, and (iii) critical dimension (CD) variation over topography caused by multireflection of topographic features. On the other hand, i- line lithography ((lambda) equals 365 nm) has apparently been applied to 64M DRAM of 0.35 micrometers design rule, and attempted to 0.30 micrometers technology which corresponds to 2nd generation 64M DRAM or 1st generation 256 M DRAM. It might be achieved by combination of off-axis illumination (OAI), phase shift mask (PMS) and advanced resist process technique of i-line lithography. Therefore, i-line lithography can be more practical method rather than DUV lithography for the mass production. In this paper, we have optimized the i-line lithographic techniques for the various pattern shape and density for 0.30 micrometers design rule. Optimum duty ratio was tried to find for line and space, contact hole patterns. The basic rule is to keep the minimum Cr width over 0.30 micrometers mask. OAI have been applied to get higher contrast of line and space, and even contact hole patterns, and achieve good pattern fidelities of island patterns. By the implementation of OAI, process latitudes were greatly improved compared to that of conventional techniques. In order to optimize the process over the actual topography, optimum numerical aperture (NA) and aperture of the OAI were selected. In conclusion, 0.30 micrometers design rule device was successfully fabricated by optimizing the advanced i-line lithographic techniques.

The global proximity effects of densed line, semi-isolated line are studied for conventional illumination, off-axis illumination, and finally off-axis illumination in combination with attenuated phase shift masks which have transmittance of 4% and 8%, respectively, by experiments and simulations. To analyze the behavior of proximity effects, the lithographic performances of the super resolution technique are investigated comparing the cross-sectional view of resist pattern profile, useful depth of focus, and the curves of linewidth vs. defocus for 0.30 micrometers , 0.35 micrometers , and 0.40 micrometers pattern size, respectively. The global proximity effect is quantitatively analyzed by fitting the curve for densed line and isolated line to 2nd order polynomials. Off- axis illumination with attenuated phase shift mask is very effective to minimize the proximity effects for the pattern size less than 0.40 micrometers , and have useful depth of focus of 1.0 micrometers for 0.30 micrometers patterns.

New developments in the field of embedded shifter materials look very promising for defect free phase shifting mask (PSM) manufacturing. Nevertheless, a good control of the shifter parameters (phase shift and absorber transmittance) remains of utmost importance. In this paper, a lithography sensitivity analysis to shifter deviations has been carried out. It was found that dark field masks require different tolerances than light fields. Because of a growing need for an accurate measurement method of the phase shift, an optical technique, based on measurement of the zero diffraction order of diffraction gratings, is investigated. Using this technique, an attenuated PSM manufacturing process has been optimized for deep-UV, in order to demonstrate the possibilities of quarter micron PSM lithography. As a result, 0.3 micrometers contact windows could be printed with sufficient process latitudes. Using modified illumination techniques in combination with the attenuated PSM, considerable gain in process latitudes was found for quarter micron gates as well, although proximity effects are still a concern.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

When printing at the resolution limit of the steppers, optical proximity effects become increasingly important and might limit the useful resist processing window. In this paper proximity effects have been studied for processes based on surface imaging and dry development. Proximity effect resulted in both linewidth and profile differences between dense and isolated lines at 0.35 micrometers and below. Proximity is partly due to optical effects (NA, (sigma) , wavelength, mask tonality) and partly due to processing conditions (silylation and development). To study the optical effects, aerial image simulations have been performed and a comparison with experimental results was carried out. Reduction in proximity is realized by a reduction in 'process offset', improvements in silylation contrast and a reduction in microloading effects during dry development. Positive tone resist processes show a reduced proximity effect as compared to negative tone resist processes and the feasibility for 0.30 micrometers dimensions has been shown. At 0.25 micrometers level, the process optimization should be accompanied with optical solutions in the form of selective mask biasing.

A simplified positive tone process using liquid phase silylation in DUV lithography is presented in this paper. The diffusion enhanced silylated resist (DESIRE) process has been demonstrated as an attractive solution not only to improve resolution and process latitudes but also to cope with linewidth variations over highly reflective topography. Traditionally the silylation process has been carried out using hexamethlydisilazane (HMDS) although more lately alternative gaseous agents such as tetramethyldisilazane (TMDS) have begun to exhibit certain advantages. This technique requires stringent control of silylation track and dry development equipment. Several new resists (which consist of a novolac based resin with a photo-crosslinker) have been formulated for deep-UV, allowing silylation at room temperature. By using this photo-crosslinker, the PSB (pre-silylation bake) step can be removed. In this way the process can be even more simplified. Characterization of the silylation reaction and mechanism have been performed using thickness measurements, CO emission spectroscopy, Fourier transform infrared absorption (FTIR), and Rutherford backscattering spectroscopy (RBS). In order to explore the limits, this process has also been evaluated using phase shifting masks. The influence of partial coherence on the resolution and process latitudes has also been studied.

A new technique has been developed for the illumination of a mask in a wafer stepper. A phase-shifting layer (a so-called kinoform) is introduced in the optical path of the projection system between the last lens of the illumination system and the mask absorber. This phase- layer interacts with the incident light in such a way, that the features on the mask get a specific optimized illumination. Therefore the phase distribution has to be generated under consideration of the feature size and distribution on the mask. In that sense a mask feature customized illumination is obtained. In a first application phase, the phase layer is created on the glass side of the mask. Linear as well as chessboard phase gratings are applied. With a chessboard phase grating, a quadrupole-like illumination is generated, which can be optimized to the mask feature distribution by choosing the correct grating frequency, phase-shift and tilt.

To extend the limitation of KrF lithography into the 110 nm design rule region, dipole off-axis illumination (OAI) is suggested. We have investigated the availability of the 1st-order efficiency as a method of optimization and confirmed it in the conventional OAI. By the 1st-order-efficiency method, we have designed two dipole apertures that are capable of resolving horizontal and vertical dense patterns, and have evaluated the basic performance of the modified dipole apertures. To verify the applicability of the modified dipole apertures to memory devices, we tested a variety of patterns and obtained fine patterns with the help of optical proximity correction (OPC). In this study, we found that the optimized dipole OAI can serve as an extension method of KrF lithography for 110 nm devices.

The critical dimension (CD) uniformity of an isolated-dense pattern has been the most critical issue in optical lithography below the wavelength of the illumination source and much effort has been exerted to improve it. The CD difference between isolated and dense patterns (ID bias), which is caused by proximity effects, is known to be one of the key factors leading to the deterioration of CD uniformity. Because ID bias is such a complicated phenomenon and affected by many factors, it would be very difficult to control it even though we understand all the factors that lead to it. Much research on ID bias has been conducted; however, the effect of resist thickness on ID bias has not yet been clearly studied. From our investigations, we have investigated the effects of resist thickness on ID bias and found that ID bias is strongly affected by resist thickness. ID bias changes periodically with resist thickness and the minimum ID bias is obtained by controlling the resist thickness for a specified pattern. We also found that the antireflective coating (ARC) process is an effective method for controlling ID bias.

In this article, we introduce the constraints of cell projection mask (CPM) design for application to sub-0.13 μm patterning and the modified fabrication technology for the highly accurate CPM. First, we investigated the constraints of CPM design such as Coulomb interaction and proximity effect. Especially, in order to reduce beam blur effect, we applied mask bias and optimized shot size that could be obtained by calculated space margin and experiment. Second, we made highly accurate CPM using modified fabrication technology, which included deep trench etching process with oxide barrier, the stacked protection layer, and effective cleaning process. The minimum feature size achievable in this technology is 1 μm, corresponding to 0.04 μm on a wafer due to 1/25 reduction ratio of cell projection e-beam lithography system. Using CPM made by above process, we successfully defined 0.08 μm lines-and-spaces and 0.1 μm contact hole patterns with a standard deviation of 0.005 μm. In addition, we also compared the l...

The characteristics and performance of the resist flow process (RFP), which is one of the contact hole (C/H) shrinking technologies, were investigated for sub-150 nm C/H patterns using KrF (λ=248 nm) lithography. A fine C/H pattern was defined by adopting optimized process parameters at a higher baking temperature than the glass transition temperature of the used matrix material. The shrinking limit of the C/H pattern was in the range of 40–50 nm without any deformation in profile from the original C/H size, however, the bowing profile of the C/H pattern was observed in the case of a shrinking bias larger than 50 nm. It was also found that the amount of shrinkage of the C/H pattern was strongly dependent on the baking temperature, total quantity of the resist surrounding the C/H pattern, and resist thickness. When the 150 nm C/H pattern was formed by RFP from a 180 nm C/H generated by an attenuated phase shifting mask (PSM), the depth of focus (DOF) and the energy latitude (EL) were 1.6 µm and 16%, respectively, and the critical dimension (CD) uniformity in an 8-inch wafer was less than 25 nm. In this study, in spite of baking to enable resist flow, the etch selectivity of resist on silicon substrates was not changed and the C/H pattern on silicon oxide after the etching process showed a vertical profile. Based on these results, it is believed that the RFP for a sub-150 nm C/H pattern will be a very promising candidate for the mass production of gigabit devices.