Optimization for full-chip process of 130-nm technology with 248-nm DUV lithography

We estimated the process margins of various cell structures and process problems for full chip process under extremeresolution limit of exposure tool. Therefore, optimizing off axis illumination (OAI) condition for various structures obtainedthe fme pattern and wider process margin using simulation and experiment. From our experiment, we should use as highernumerical aperture (NA), smaller R and smaller r as possible to reduce critical dimension (CD) difference between denseand isolated patterns. Process margins are obtained more than 8% exposure latitude (EL) and 0.5 tin depth of focus (DOF)for each cell. However, we can consider using of attenuated phase shift mask (PSM) to improve the exposure and DOFmargin. We fmd that real full chip process induces the critical problems such as isolated line (I/L) and space (L'S) patternvariation due to lens aberration, partial coherence effect, mask error effect, and optical proximity effect. These effects playa role to determine the design rule of cell and periphery structures. In spite of good lens quality, variation of I/L and USpattern for various exposure conditions is almost 4Onm or more compared to line and space (L/S) pattern. These phenomenaare becoming the critical issue to fulfill the full chip process of l3Onm lithography. By optimizing mask error effect,isolated and dense pattern bias (ID bias), and OAI, we can achieve l3Onm technology with 248nm KrF lithography.KEYWORDS : KrF, Design rule, ID bias, OAI, Full chip process, High NA, Process margin