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This article contains the results of research on the topical problem of highly sensitive express registration of biological objects using field-effect transistors with the surface open for analyte access, which are made based on silicon-on-insulator (SOI) films. The possibilities of dielectrophoretic effects for controlling the concentration of the analyte in the area of sensory elements are considered on the example of the indication of viruses of nuclear polyhedrosis and vaccinia. It is shown that the use of the dielectrophoresis (DEPh) effect makes it possible to solve (1) the key tasks for creating sensor systems: increasing the detecting ability, as well as exrtacting and verifying the signal from the target particles; and (2) the fundamental task: determining the charge state of the analyte in solutions without modifying the sensors’ surface. The problems and prospects of the mass application of nanowire (NW) biosensors, including those with the dielectrophoretic effect, in biotechnology, virology, etc., are discussed.

Gate-induced drain leakage (GIDL) is a serious problem in nanoscale transistors. In this paper, GIDL induced by longitude band-to-band tunneling (L-BTBT) in gate-all-around (GAA) nanowire transistors is investigated by 3D TCAD simulation. Effects of critical process parameters are analyzed, such as sidewall spacer characteristics, nanowire diameter, gate length and doping gradient in the source/drain extension region. The corner spacer and dual κ spacer are found to suppress L-BTBT current without degrading the dynamic performance. An underlap structure, a smaller nanowire diameter, and a gentle doping gradient at the source/drain extension are separately found as best choices, with regard to decreasing L-BTBT current. The underlying physical mechanisms are analyzed, and results indicate that increased L-BTBT width contributes to decreasing L-BTBT current. The results obtained here are reliable for optimizing the device structure, and help in low power circuit design based on nanoscale GAAFET.

Gate leakage current in lateral GaN wrap-gate nanowire transistors (WG-NWT) was investigated using current density–voltage (Jg–Vg) characteristics at room temperature. We found that the gate leakage current is strongly dependent on the top corner angle of the gate architecture. This leakage current was characterized by considering hopping (Poole–Frenkel emission) and trap-assisted thermionic emission mechanisms. Despite its smaller gate area, the gate leakage current of the lateral GaN WG-NWT without a 2DEG channel was higher than that of the device with a 2DEG channel for all applied gate biases. The reason for this is that the lateral GaN WG-NWT without 2DEG channel has a triangular cross-section with a sharp top corner angle resulting in a strong electric field due to geometrical field enhancement.

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.

This project is to study about characteristics of nanowire transistor. The simulation is done by SILVACO software to find the characteristics of nanowire transistors. Here simulation is more important to understand the device physics and performance limits of the nanowire transistors. By the support of the simulation tools experimental work can be done for nanowire transistor. With the help of simulation, we can know the weakness and strength of nanowire transistors. That will help to reduce the fabrication cost. As we go for the smaller size for the transistor then nanowire transistor comes into the picture. For electronic device Silicon, Germanium and Gallium Arsenide semiconductor materials are generally used. Here production of Silicon simple as compare to Gallium Arsenide but when high speed device is required then we go for Gallium Arsenide material.

Low-dimensional electronic systems such as silicon nanowires exhibit weak screening which is detrimental to the performance and scalability of nanodevices, e.g., tunnel field-effect transistors. By atomistic quantum transport simulations, we show how bound charges can be engineered at interfaces of Si and low-κ oxides to strengthen screening. To avoid compromising gate control, low-κ and high-κ oxides are used in conjunction. In Si nanowire tunnel field-effect transistors, we demonstrate that bound charge engineering increases the on-state current by orders of magnitude, and the combination of oxides yields minimal subthreshold swing. We conclude that the proposed bound-charge engineering paves a way toward improved low-power transistors.

In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

The low-frequency noise behavior of junctionless (JL) gate-all-around (GAA) nanowire (NW) FETs has been investigated and compared with similar inversion-mode (IM) devices. It is shown that the predominant 1/f-like noise is governed by carrier number fluctuation (CNF) around threshold voltage operation, while for the p-channel transistors, a pronounced increase in the noise power spectral density is observed at higher gate voltage overdrives. This is due to the impact of the access region to the flicker noise. While the CNF noise is roughly one decade higher for the n-channel than for the p-channel transistors, the opposite holds for the access-related component for both IM and JL GAA NWFETs. It is, finally, observed that the CNF noise is on the average slightly lower in the JL devices compared with their IM counterparts; the origin of this trend will be discussed.

Sustaining Moore's law requires the design of new materials and the construction of FET. Herein, we investigated theoretically the electronic transport properties of PbSi nanowire Schottky-clamped transistors with a surrounding metal-insulator gate by employing MD simulations and the NEGF method within the extended Hückel frame. The conductance of PbSi nanowire transistors shows ballistic and symmetrical features because of the Schottky contact and the resonance transmission peak, which is gate-controlled. Interestingly, the PbSi(8,17) nanowire FET shows a high ON/OFF ratio and proves to be a typical Schottky contact between atoms as described by the EDD and EDP metrics.

The aim of this work is to propose a compact analytical model for the Low Frequency Noise (LFN) in Junctionless Nanowire Transistors (JNTs). Since JNTs work differently from inversion mode transistors, the noise is also expected to behave differently. To the best of our knowledge, no analytical models have been presented for LFN in these devices. The proposed model is validated through numerical simulations. Experimental results are also used to demonstrate its applicability.

Gate-all-around (GAA) cylindrical channel Si nanowire field effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3-D TCAD simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3nm gate length. The performance of n-type silicon nanowire transistors is benchmarked using predictive TCAD device simulation.

The ballistic hole transport properties in rectangular cross-sectional germanium nanowire transistors with various geometries were studied based on the “Top of the Barrier” model. Then, by an extension of this model, the quasi-ballistic hole transport was discussed taking into account phonon and surface roughness scattering in the channel and source-to-drain direct tunneling. Among several nanowire geometries targeted in this study, the [1 1 0]-oriented nanowire with large height along [1 1 ¯ 0] ([1 1 0]/(1 1 ¯ 0) NW) exhibited the largest ballistic current. This was understood from its large density of states and resulting high hole density. Large density of states, however, enhances backscattering in the channel. An approximation analysis of quasi-ballistic transport suggested that the [1 1 0]/(0 0 1) NW with higher mobility can outperform [1 1 0]/(1 1 ¯ 0) NW when scattering and tunneling are considered.

Through advanced electro-thermal simulations we demonstrate that self-heating effects play a significant role in ultrascaled nanowire field-effect transistors, that some crystal orientations are less favorable than others (⟨111⟩ for n-type applications, ⟨100⟩ for p-type ones), and that Ge might outperform Si at this scale. We further establish a relationship between the dissipated power and the electrical mobility and another one between the current reduction induced by self-heating and the phonon thermal conductivity.

We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from Id-Vg to Id-Vd characteristics with liner and saturation region. Dependence of source/drain parasitic resistances on nanowire width and gate sidewall thickness can be observed on the extracted parameters. Furthermore, parasitic capacitance was extracted from three-dimensional TCAD simulation with our fabricated device structure. Single sets of parameters can reproduce I-V characteristics with Lg down to 35nm for n-channel nanowire transistors. It was found that the extracted parameters will be a useful tool for characterizing the circuit performance of nanowire transistor. Therefore, this procedure is applicable to extract the BSIM4 model parameters for NW Tr. as well as other multi-gate FETs. SPICE parameters of BSIM4 were successfully extracted for tri-gate NW Tr.Dependence of Rsd on Tr. geometry and process can be observed on the parameter.Single sets of parameters for Lg down to 35nm were obtained.The parameters will be a useful tool for characterizing the circuit performance.

The fabrication of biologically inspired solid-state devices has attracted tremendous attention for decades, and the hardware implementation of artificial synapses using individual ionic/electronic hybrid devices is very important for neuromorphic applications. Herein, electric double-layer (EDL) synaptic transistors coupled by proton neurotransmitters with a multiple in-plane gate structure were successfully fabricated using SnO2 nanowires. Not only the important synaptic functions were mimicked in these devices, but also the synaptic behaviors can be modulated over a dynamic range via the multi-terminal regulation of synaptic inputs. Furthermore, a light source was used to illuminate the SnO2 nanowire synaptic transistors, which were used as the light-modulating terminals. The observed neuromorphic functions were also dynamically modulated via the light density. These excellent nanoscale synaptic transistors may find significant applications in synaptic electronics.

In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases.

We present experimental results for junctionless nanowire transistors (JNTs) with different gate alignments to the nanowire. Devices with nanowire source/drain extensions (NSDE) show high series source/drain resistance due to the low doped nanowire extensions, which causes lower drive current and larger device performance variations comparing with devices in which the gate electrode overlaps with the source/drain contact pads (GSD). Due to the improved on-current GSD devices exhibit much higher cutoff frequency. The high fringing field in the NSDE JNT results in degradation of SS. An optimized “dumbbell” shape JNT structure is proposed to further improve the device performance. Our preliminary simulations demonstrate higher on-currents but also larger parasitic capacitances for the dumbbell JNT. However, the RF performance of the dumbbell JNT is still improved with a factor similar to our experiments. Much smaller fringing field for the dumbbell JNT is expected from the simulation, which can cause less device variations.

Compound contacts, formed by thermal annealing of metal-semiconductor nanowires (NWs), are prescribed for lithography-free self-aligned gate processes. Investigations of nanoscale contact metallization have revealed distinctive behaviors from their bulk counterparts, evoking reevaluation of the thermodynamics, kinetics, and resultant phases in alloyed and compound nanoscale contacts. In this chapter, we focus on several critical semiconductor materials of practical importance for devices, e.g., Si, Ge, and III–V NWs, and provide in-depth discussions on the phases of compound contacts, their reaction kinetics, and electrical properties. In Sect. 5.2, we introduce the phase selection rules that lead to multiphase coexistence in low-dimensional NW semiconductor channels. In Sect. 5.3, we discuss the kinetic processes during these solid-state reactions and present a model that can be used to distinguish the rate-limiting steps and to extrapolate the reaction kinetic parameters. In Sect. 5.4, we will introduce electrical properties of NW transistors with these compound contacts and summarize different applications of these contacts including ultrashort channel devices. This entire chapter is organized to demonstrate the promise of compound contacts in nanoscale electronics.

Silicon junctionless nanowire transistors with the typical nanowire section of 18 nm width and 30nm height are fabricated and the current-voltage characteristics are measured at low temperatures in this paper. We demonstrate the one-dimension electronic transport behavior from the quantized current steps and transconductance oscillation. Moreover, the Coulomb interaction related transport behaviors are observed below the temperature of about 30 K, supporting by the double sub-peaks in the transconductance characteristics.

The electrical characteristics of n/p Ge nanowire transistors (NWTs) with the cross section of $6\times 6\mathrm{n}\mathrm{m}^{2}$ have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic $\Lambda$-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic I ON is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.

This paper discusses the occurrence of self-heating in Junctionless Nanowire Transistors, observed through drain current degradation in the transient regime. The analysis is made by performing experimental measurements using the Pulsed IV method in transistors with varied dimensions. It is shown that the junctionless nanowire’s susceptibility to self-heating is not high enough to significantly affect the transistor’s characteristics, where for all cases current degradation lower than 4.5% is seen.

The compositional dependence of electronic band structure in relaxed and biaxially strained Ge 1−x Sn x alloy is investigated with the first principles method. Based on energy band dispersion along the [100] crystal orientation, hole effective mass is extracted via parabolic line fit. Calculation results indicate Sn composition dependence of the hole effective mass for relaxed alloy is much less pronounced than biaxially strained alloy. And then the electronic structure of Ge 1−x Sn x -Si core-shell nano wire along the [110] direction is studied from first-principles calculation.

Ever since Intel launched its successful 22-nm Ivy Bridge CPU chip, establishing nonplanar finFET technology as a viable means of extending Moore’s law, variations of the basic finFET or the nanowire transistor have been introduced into nanoelectronics research and manufacturing efforts at an unprecedented rate.

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high ${I}_{\rm on} /{I}_{\rm off} $ current ratio of $7\times 10^{8} $ ( $V_{\rm G} = 4$ V and $V_{\rm D} = 1$ V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

The increase of hot carrier degradation with decreasing wire width in nanowire gate-all-around (GAA) MOSFETs has been investigated through experiment and device simulation. From the systematical analysis of measurement and simulation, it is found that the increase of device degradation in narrow devices is dominantly governed by the increased current density, the large lateral and vertical fields, and the increased interface state generation rather than by the reduced floating body effects. The more significant hot carrier degradation with decreasing wire width is likely to be proportional to the surface-to-volume ratio of nanowires.

This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.

This paper studies the effective mobility in n- and p-type junctionless nanowire transistors (JNT) with variable fin width from quasi-planar to nanowire devices. JNTs electrical parameters were analyzed and the results show that smaller fin width have higher mobility while the mobility decreases for quasi-planar devices. Simulations were used to analyze the mobility showing that small fin devices reach higher mobility for smaller gate bias variation above the threshold voltage and a higher mobility in the middle of the channel due to the better electrostatic coupling compared to larger devices.

We report experimental results of the N/PBTl (Negative/Positive Bias Temperature Instability) reliability of vertically stacked Gate-All-Around (GAA) silicon nanowire (NW) MOSFETs. We benchmark the lifetime of these novel devices against FinFETs with different widths and similar gate-stack. We do not only compare the average degradation, but also the time-dependent variability. At last, we predict the impact of the nanowire diameter on the reliability using TCAD simulations. Both the experimental results and the simulations indicate that BTI reliability is not negatively impacted down to a nanowire diameter of 6nm.

This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.

A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed.

We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices.

In this work we propose an analytical model for the threshold voltage ( V T ) of III–V cylindrical nanowires, that takes into consideration the two dimensional quantum confinement of the carriers, the Fermi–Dirac statistics, the wave-function penetration into the gate insulator and the non-parabolicity of the conduction band structure. A simple expression for V T is obtained assuming some suitable approximations. The model results are compared to those of a 2D self consistent Schrodinger–Poisson solver, demonstrating a good fit for different III–V materials, insulator thicknesses and nanowire sizes with diameter down to 5 nm. The V T dependence on the confinement effective mass is discussed. The different contributions to V T are analyzed showing significant variations among different III–V materials.

Device design for cylindrical Si nanowire field-effect-transistors is studied in short channel regime of 22 nm technology generations and beyond. A two-dimensional quasi-analytical model reveals that a critical minimum channel length is 1.5 times as long as a Si nanowire diameter to suppress the short channel effects. The quantum mechanical effect due to the structural carrier confinement in nanowire with narrow diameter deteriorates both the threshold voltage roll-offs and the subthreshold characteristics.

We compare the electronic characteristics of nanowire field-effect transistors made using single pure wurtzite and pure zincblende InAs nanowires with nominally identical diameter. We compare the transfer characteristics and field-effect mobility versus temperature for these devices to better understand how differences in InAs phase govern the electronic properties of nanowire transistors.

The paper presents a basis expansion scheme for atomistic transport simulations in nanowire MOSFETs. Two simple methods are formulated to calculate current carrying states using a low-dimensional device Hamiltonian in the scattering basis representation. The proposed methods are computationally very cheap and their utility is confirmed by test self-consistent calculations in a p-Si nanowire device.

session 5: Device Reliability; International audience; We present an extensive study of Hot Carrier reliability in N-Ωfet nanowires. For the first time 3 HC degradation modes were clearly evidenced as in planar technology and accurately modeled. Moreover HC reliability was proved to be width-independent. Finally it is shown that, although SH is important in nanowires, it has almost no implication on its HC reliability because of the weak temperature dependence of the HC mechanisms.

Research on nanoscale semiconductor devices will elicit a novel understanding of biological systems. First, we discuss why it is necessary to build interfaces between cells and semiconductor nanoelectronics. Second, we describe some recent molecular biophysics studies with nanowire field effect transistor sensors. Third, we present the use of nanowire transistors as electrical recording devices that can be integrated into synthetic tissues and targeted intra- or extracellularly to study single cells. Lastly, we discuss future directions and challenges in further developing this area of research, which will advance biology and medicine.

A continuous surface-field based modeling platform for heavily doped junctionless nanowire transistors is presented. By constructing specific transformation variables, a straightforward relation between the surface potential and field is identified to facilitate an efficient model for calculating the (long-channel) drain current from the oxide-interface boundary condition with no need of a surface-potential approach. Such a surface-field-based modeling platform may enable a paradigm shift in compact modeling strategy, which is also applicable to device doping optimization.

SSDM Young Researcher Award; International audience

If nanowire transistors are to be applied to next-generation electronic devices, controlling their characteristics is crucial. In particular, the threshold voltage (Vth) must be controlled because it determines the driving voltage of the transistors. In this research, we were able to control the Vth characteristics in both the negative and the positive directions by performing H2 and O2 gas treatments at room temperature; this control was achieved because oxygen vacancies on the surfaces of the oxide nanowire channel regions could be controlled with the treatments. The H2 treatment changed Vth in the negative direction with increasing processing time (−0.6 V at 10 min; −0.9 V at 30 min; and −1.4 V at 60 min), whereas the O2 treatment changed Vth in the positive direction regardless of the processing time (+0.73 V at 10 min; +0.85 V at 30 min; +0.84 V at 60 min). This method can be applied to display-pixel and digital-logic circuits, especially those that employ nanowire transistors and require Vth control.

The primary goal of this special issue is, therefore, to compile advances in different aspects of nanowire-based devices including device physics and modeling, device design, characterization techniques, technology, and applications so that this special issue will not only be of great archival value but also attract new researchers into this area for further accelerating the application of nanowires in building cheaper and higher performance electronic systems.

Organic nanowires self-assembled from small-molecule semiconductors and conducting polymers have attracted an enormous amount of interest for use in organic field-effect transistors. This new class of materials offers solution processability, the potential for elucidating transport mechanisms and structure-property relationships, and the realization of high-performance transistors that rival the performance of amorphous Si. We discuss the self-assembly of one-dimensional, single-crystalline organic nanowires, show the structures of commonly employed organic semiconductors, and review some of the advances in this field.

The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this paper, the major assets of NW field-effect-transistors in leading-edge technology nodes are explained in details. For this purpose, electron (hole) transport properties of Si (SiGe) NWs and the critical contribution of strain are discussed. A particular attention is given to the key technological integration challenges to be addressed, with emphasis on the practical implementation of 3D high-density stacked-NWs architectures.

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favourable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures., 18 pages, 5 figures, In press for Nano Letters (DOI below)

In this work, the performance of Ultra-Low-Power (ULP) Diodes implemented with Junctionless Nanowire Transistors (JNTs) is presented for the first time. Experimental data of ULP Diodes formed by Junctionless Nanowire CMOS Transistors show that nanowire width, length and doping concentration play an important role in the reverse current of the diodes, affecting the on-off current ratio.

We present a process for fabricating a field-effect transistor based on vertically standing InAs nanowires and demonstrate initial device characteristics. The wires are grown by chemical beam epitaxy at lithographically defined locations. Wrap gates are formed around the base of the wires through a number of deposition and etch steps. The fabrication is based on standard III–V processing and includes no random elements or single nanowire manipulation.

International audience; The less surface roughness scattering effects, owing to the unique operation principle, in junctionless nanowire transistors (JLT-NW) were shown by low-temperature characterization and 2D numerical simulation results. This feature could allow a better current drive under a high gate bias. In addition, the dominant scattering mechanisms in JLT-NW, with both a short (LM = 30 nm) and a long channel (LM = 10 μm), were investigated through an in-depth study of the temperature dependence of transconductance (gm) behavior and compared to conventional inversion-mode nanowire transistors.

In-plane-gate transparent SnO2 nanowire transistors gated by SnO2-based solid electrolytes are fabricated on glass substrate at room temperature. Low-voltage (1.0 V) operation of such device is realized due to the large electric-double-layer capacitance of 0.75 μF/cm2 at 20 Hz. The subthreshold slope, current on/off ratio, and field-effect mobility of the in-plane-gate transparent nanowire transistors are estimated to be 92 mV/decade, >; 105, and 106.8 cm2/V · s, respectively. Such low-voltage in-plane-gate transparent nanowire transistors are promising for portable invisible sensors.