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Atomic layer deposited (ALD) tantalum nitride (TaxNy) is evaluated as a barrier against aluminum inside gate metal stacks of metal-oxide-semiconductor field effect transistor (MOSFET) devices. When deposited on hygroscopic oxides, like HfO2, amorphous tantalum nitride (a-TaxNy) is obtained, while deposition on Si or TiN results in polycrystalline Ta3N5. The low conductivity of both phases is not attractive for gate metal applications; however, a-TaxNy is crystallized to bixbyite Ta2N3 at 500 °C, improving its conductivity to ∼130 Ω−1 cm−1. For thicknesses below 10 nm, crystallization did not happen, but thin a-TaxNy barriers still obtain conductivity improvements to ∼500 Ω−1 cm−1 when Al diffuses into the film. In metal gate stacks, a-TaxNy screens the low work function of ALD TiAl more effectively than TiN. A barrier thickness reduction of 50% is achieved for n-MOSFET devices with an effective work function at 4.2–4.3 eV and low gate leakage. Slower diffusion of Al into TaxNy is observed by secondary ion mass spectroscopy; however, the cause of EWF lowering as a result of Al diffusion could not be confirmed. Instead, restoration of high EWF after removal of TiAl occurs, enabling an NMOS-first process integration with the use of 1 nm thin TaxNy barriers. [ABSTRACT FROM AUTHOR]

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology. [ABSTRACT FROM AUTHOR]

The impact of wet versus dry dummy dielectric removal approaches on replacement metal gate (RMG) high- k last (RMG-HKL) pMOSFETs, with aggressively scaled high- k gate dielectric, has been studied by low-frequency noise. It is shown that excess generation–recombination noise, ascribed to random telegraph noise, causes a significant variability in the power spectral density (PSD). The best average PSD and the smallest device-to-device spread have been obtained by the remote-plasma dummy-gate removal followed by an in situ HF exposure prior to atomic layer deposition of \HfO2. [ABSTRACT FROM AUTHOR]

The change of the energy profile of the initially present HfSiO defects in nMOSFETs after Vth adjustment by As and Ar implantations is investigated. A fundamental correlation between the density of energetically deep traps and the initial Vth revealed, suggesting that the negative bulk charge in HfSiO controls the Vth. [ABSTRACT FROM AUTHOR]

Abstract: As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10nm reacts with Si substrate and forms TaSi2 at 650°C in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90nm contacts. Top-view SEM observation on the samples after 420°C sintering demonstrates that the Cu diffusion barrier is effective. I on–I off curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi2/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si. [Copyright &y& Elsevier]

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si1− x C x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750°C and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si1− x C x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides. [Copyright &y& Elsevier]