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Results from an extensive reliability characterization of HfLaSiO(N) devices, with TaN gate electrodes, are reported. It is shown that the effect of the lanthanum, initially deposited as La2O3, on a SiO2/HfSiO(N) stack, permeates the Si/SiO2 interface. A lower midgap interface state density is observed at this interface, but increased densities are seen towards the band edges. The presence of lanthanum in the dielectric results in defects in the interface layer and in the high-κ dielectric. A profile of defects in the gate stack is suggested, inferred from a combination of electrical measurements. From the location of the defects, it is argued that the reliability of lanthanum-incorporated devices is not compromised by its presence, thus enabling a reliable route to Vt tuning of n-type metal oxide semiconductor devices. [ABSTRACT FROM AUTHOR]

Low-frequency noise in strained Ge epitaxial layers, which are grown on a reverse-graded relaxed SiGe buffer layer, has been evaluated for different front-end processing conditions. It has been shown that the \1/f noise in strong inversion is governed by trapping in the gate oxide (number fluctuations) and not affected by the presence of compressive strain in the channel. However, some impact has been found from the type of halo implantation used, whereby the lowest noise spectral density and the highest hole mobility are obtained by replacing the standard As halo by P implantation. At the same time, omitting the junction anneal results in poor device characteristics, which can be understood by considering the presence of a high density of nonannealed implantation damage in the channel and the gate stack near the source and the drain. [ABSTRACT FROM PUBLISHER]

The pronounced high interfacial densities of states (Dit) commonly observed around the midgap energy of dielectric/GaAs interfaces are generally considered the culprit responsible for the poor electrical performance of the corresponding inversion-channel metal-oxide-semiconductor field-effect-transistors. In this work, comprehensive Dit spectra as the function of energy [Dit(E)] inside the In0.2Ga0.8As band gap were constructed by using the quasistatic capacitance-voltage and the temperature-dependent conductance method on n- and p-type ultrahigh vacuum (UHV)-Ga2O3(Gd2O3)/In0.2Ga0.8As and atomic-layer-deposited (ALD)-Al2O3/In0.2Ga0.8As metal-oxide-semiconductor capacitors. Unlike the ALD-Al2O3/In0.2Ga0.8As interface giving a Dit spectrum with a high midgap Dit peak, the UHV-Ga2O3(Gd2O3)/In0.2Ga0.8As interface shows a Dit spectrum that monotonically decreases from the valence band to the conduction band with no discernible midgap peak. [ABSTRACT FROM AUTHOR]

The low-frequency noise in strained and relaxed Ge pMOSFETs is characterized to investigate more closely the anomalously large current spectral density at low drain currents. As shown, the dominant Lorentzian spectrum found in weak inversion points to fluctuations by generation–recombination (GR) events at substrate defects. This is confirmed by the fact that strained Ge transistors, having a significantly lower threading dislocation density, also exhibit lower excess GR noise. The usual number-fluctuation \1/f noise becomes more pronounced above threshold and also for shorter gate lengths. [ABSTRACT FROM AUTHOR]

The change of the energy profile of the initially present HfSiO defects in nMOSFETs after Vth adjustment by As and Ar implantations is investigated. A fundamental correlation between the density of energetically deep traps and the initial Vth revealed, suggesting that the negative bulk charge in HfSiO controls the Vth. [ABSTRACT FROM AUTHOR]

Abstract: Ultrathin EOT-values are achieved by using optimized processing conditions and interface layer scavenging in metal-gated (TiN and TaN) based planar and bulk-FinFET devices. EOT values down to 4.5Å in the planar devices and in bulk-FinFETs are demonstrated. Improved EOT-leakage current scaling is observed with the use of chemical oxides as compared to thermally grown as interface layer for the . In contrast, the mobility is found independent of the compared interface layers, processing conditions and metal electrodes and follows one trend-line with EOT. The FinFET devices show decreased -values and improved mobility for more narrow fin widths. [Copyright &y& Elsevier]

Abstract: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si1− x C x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750°C and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si1− x C x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides. [Copyright &y& Elsevier]