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Enhancement-mode (E-mode) vertical $\beta $ -Ga2O3 metal–oxide–semiconductor (MOS) field-effect transistors featuring a current aperture were developed on a single-crystal $\beta $ -Ga2O3 (001) substrate. Nitrogen ions were implanted into a drift layer grown by halide vapor phase epitaxy to form current blocking layers (CBLs) for vertical source–drain isolation, while Si ions were implanted to form degenerately doped source contact regions and a top-gated lateral channel that was fully depleted at 0-V gate bias. The devices delivered a high output current on/off ratio of $2\times {10}^{{7}}$ despite a nonideal MOS interface that limited the maximum drain current density to

We found that nitrogen (N) and silicon (Si) were unintentionally co-doped in Ga2O3 layers grown by plasma-assisted molecular beam epitaxy (PAMBE), and that the ratio between N and Si could be controlled by O/Ga flux ratio during the growth. Note that N and Si act as a deep acceptor (theoretically predicted) and a shallow donor (experimentally confirmed) in Ga2O3, respectively. Taking advantage of this unique characteristic of PAMBE-grown Ga2O3, normally off operation of Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs) was demonstrated. The unintentionally-doped Ga2O3 channel layer of the MOSFETs had N and Si concentrations of $1\times 10^{18}$ and $2\times 10^{17}$ cm−3, respectively, and thus it was considered to behave as a p -type material. The MOSFETs showed a turn-on threshold gate voltage of larger than +8 V, implying formation of an inversion channel in the N-doped Ga2O3 layer. Although the ON-state drain current ( ${I}_{\mathrm{d}}$ ) remained in the subthreshold regime owing to limited gate voltage swing, the ${I}_{\mathrm{d}}$ ON/OFF ratio exceeded five orders of magnitude.

Depletion-mode vertical Ga2O3 metal-oxide-semiconductor field-effect transistors featuring a current aperture were developed on a halide vapor phase epitaxial drift layer grown on a bulk $\beta $ -Ga2O3 (001) substrate. Three ion implantation steps were employed to fabricate the ${n}^{++}$ source regions, lateral ${n}$ channel, and ${p}$ current blocking layers, where Si and N were selected as the donor and deep acceptor dopant species, respectively. The transistors delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 $\text{m}\Omega \cdot \text {cm}^{2}$ , and an output current on/off ratio of over 108. High-voltage performance of the present devices was hampered by a large gate oxide field in the off-state causing high gate leakage, a limitation that can be readily overcome through optimized doping schemes and an improved gate dielectric. The demonstration of a planar-gate vertical Ga2O3 transistor based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics.

$\beta $ -Ga2O3 is an attractive material for high-voltage applications and has the potential for monolithically integrated RF devices. A combination of Raman nano-particle thermometry measurement and thermal simulation has been used to measure the peak channel temperature due to self-heating in $\beta $ -Ga2O3 MOSFETs. The peak channel thermal resistance measured at the gate surface in the device center was $88~mm\,\! \cdot \, K/W$ . This value is higher than what has been previously reported using electrical methods, which determine an average temperature over the whole device area. Experimentally validated thermal simulations have been used to propose possible thermal management mitigation approaches.

Gallium oxide (Ga 2 O 3 ) is an attractive material for next-generation power device applications due to its large breakdown electric field $(> \mathbf{7\ MV}/\mathbf{cm})$ . This paper highlights current-aperture vertical Ga 2 O 3 metal-oxide-semiconductor field-effect transistors fabricated using silicon- and nitrogen-ion implantation processes.

Gallium oxide (Ga2O3) is an emerging material for power electronics. The final penetration in the market is limited by several issues, including a stable and effective isolation between different devices and between different regions of the same device. In this work, we analyze lateral and vertical isolation structures, obtained by Mg implantation and annealing at 1000°C in Halide Vapor Phase Epitaxy β-Ga2O3. By means of repeated current-voltage characterization, it is possible to detect a severe current collapse, which can be completely recovered by white light illumination. When a constant bias is applied, the current collapse increases in magnitude at higher bias, showing a stronger filling of the deep levels. The transients closely follow the stretched-exponential model, an indication that the charge trapping is originated by extended defects, mini-bands or surface states. From the recovery transients carried out at various temperatures, it is possible to extrapolate a dominant thermal activation energy of 0.34 eV. The results of the recovery transients under monochromatic illumination show gradual variation in a broad energy range, consistent with the presence of extended defects. Temperature-dependent current-voltage characterization highlights the good performance of the bulk isolation and the presence of a significant surface leakage. Long-term stability tests show that the lateral structure is able to withstand a higher voltage level before catastrophic failure, but is less stable and is affected by a time-dependent degradation process. Charge trapping at the surface may act as a field-limiting element and partially explain the experimental findings.

Ga2O3 has exploded onto the semiconductor landscape for next-generation power electronics because its enticing material properties, most notably a large critical field strength stemming from its ultrawide bandgap, promise miniaturized circuits and systems with high conversion efficiency. Intense pursuit of Ga2O3 power devices galvanized by the demonstration of a high-voltage Ga2O3 field-effect transistor (FET) in 2012 has brought about tremendous advancements in this new technology, whose strong radiation tolerance and high thermal stability also befit harsh-environment applications that impose stringent reliability requirements. This chapter reviews the designs and properties of various types of depletion- and enhancement-mode Ga2O3 FETs—which have predominantly been lateral devices—for power switching and radiation-hard electronics. The development of vertical Ga2O3 transistors based on a low-cost, highly manufacturable ion implantation doping process will also be presented.

Impact ionization has been seen to effect pinchoff in wafer-bonded aperture vertical electron transistors (BAVETs) comprising an InGaAs channel wafer-bonded to a III-nitride (III-N) drift region. The InGaAs-III-N junction is referred to as the wafer-bonded interface (WBI). Field plating can work well to manage the peak field and related impact ionization; however, it comes with a tradeoff of increased on-resistance. In this paper, another control knob to breakdown is explored in the critical field ( $\xi _{{\text{CRIT}\_\text{IMPCT}}}$ ) of a BAVET. Investigation focuses on the characteristics of devices that differ in their InAlAs doping profile, namely p-type, unintentional, or a combination of both. These devices are tested for the role of field plate, built-in voltage, and trap behavior on pinchoff. It is shown that the change of doping causes a dramatic change to the trap activity at WBI. These traps ionize and determine $\xi _{{\text{CRIT}\_\text{IMPCT}}}$ as ionization of traps that leads to an early onset of impact ionization in the channel, which weakens pinchoff in a BAVET. Passivating traps is proposed to be a method to improving pinchoff. Trap passivation of WBI is demonstrated if InAlAs is doped p-type rather than unintentionally. A consequent enhancement in pinchoff and breakdown voltage of a BAVET is also reported.

Gallium oxide $(\mathbf{Ga}_{2}\mathbf{O}_{3})$ is an emerging ultra-wide-bandgap semiconductor especially suitable for high-power and/or high-voltage switching device applications. In this paper, device fabrication process and characteristics of depletion-mode and enhancement-mode vertical $\mathbf{Ga}_{2}\mathbf{O}_{3}$ transistors fabricated by using a multiple ion-implantation doping process are discussed.

Wafer-bonded current aperture vertical electron transistors (BAVETs) aim to eliminate the present bottleneck of simultaneously achieving high frequency and high breakdown. BAVETs enable novel transistors with a high mobility III-As (mobility = 12000 cm2 V−1S−1) channel, and a wide-bandgap III-N (breakdown field = 3.3MV.cm-1) drift region. A BAVET device, based on a current aperture vertical electron transistor (CA VET), comprises source contacts to n-doped $\mathrm{In}_{0.53}\mathrm{Ga}_{0.47}\mathrm{As}$ channel, with $\mathrm{I}\mathfrak{n}_{0.52}\mathrm{Al}_{0.48}\mathrm{As}$ as the gate barrier, InGaN/GaN layers for the drift region, and n+GaN as the drain-contact layer (Fig. 1) [1]. The on-state DC performance in a BAVET has been traditionally affected by abnormally high on-current-saturation voltage, $V_{\mathrm{DS}_{-}\mathrm{SAT}}(> 12\mathrm{V})$ (Fig. 2) [2]–[4]. Herein, we investigate the cause of this abnormality and report a significant reduction in $\mathrm{V}_{\mathrm{DS}_{-}\mathrm{SAT}}(5\mathrm{V})$ .

Ga 2 O 3 is attractive for power electronics owing to its wide bandgap of 4.5 eV and the availability of economical melt-grown native substrates. Normally-off vertical power switches are highly sought-after since they allow for superior field termination and current drive at the device level while ensuring fail-safe operation and simplified designs at the system level. Capitalizing on ion-implantation technologies for donor (Si) [1] and deep acceptor (N) [2] doping of Ga 2 O 3 , we have demonstrated depletion-mode (D-mode) vertical Ga 2 O 3 MOSFETs [3] in which Si-ion (Si+) implanted top $n^{++}$ source contacts are electrically isolated from the bottom drain contact by a N-ion (N++) implanted current blocking layer (CBL) except at an aperture bounded by CBLs through which drain current $(I_{\mathrm{D}})$ is conducted. The CBL also serves as a back-barrier for a top-gated lateral channel defined by another Si+ implantation step. Based on this manufacturable all-ion-implanted structure, this paper presents accumulation-mode normally-off vertical Ga 2 O 3 MOSFETs by appropriately designing the channel doping to control the threshold voltage $(V_{\mathrm{T}})$ without requiring fundamental process modifications.

A normally-off lateral Ga 2 O 3 metal-oxide-semiconductor field effect transistor (MOSFETs) was fabricated on a single crystal $\beta$ -Ga 2 O 3 (010) substrate. The top Ga 2 O 3 layer forming a channel was grown by plasma-assisted molecular beam epitaxy, and the doping of N functioning as a deep acceptor was performed during the growth. Subsequently, Si ion implantation was employed to form ohmic contacts with source and drain electrodes, resulting in a clear linear region in the DC output characteristics of the MOSFET. Furthermore, the device showed a rise in the drain current at a gate voltage of over 5 V, indicating a positive threshold voltage. Consequently, the normally-off characteristic of the Ga 2 O 3 (010) MOSFET with N-doped channel was demonstrated.

$\beta$ -Ga 2 O 3 has captured attention in recent years for power electronics. Opportunities also exist for $\beta$ -Ga 2 O 3 transistors to operate as radio-frequency amplifiers. For highly-scaled devices, strong confinement of the channel is critical for mitigating short-channel effects. In this work, a depletion-mode $n$ -channel $\beta$ -Ga 2 O 3 MOSFET with a back-barrier formed by implantation of deep nitrogen acceptors was demonstrated. Despite being fabricated on a conductive base material, the device delivered a drain current density of 103 mA/mm commensurate with the channel charge density and a large output current on/off ratio of $4\times 10^{9}$ , both of which attested to the efficacy of back-barrier isolation. Pulsed current-voltage measurements revealed the presence of electron trapping under the gate manifested as a threshold voltage shift. The dominant charge trapping effect was mitigated instead of exacerbated by applying a large reverse gate bias - a behavior consistent with field-assisted trap emission. These results indicate a need for further process optimization to improve the speed and reliability of the device.

The reliability of field-plated $\beta$ -Ga 2 O 3 power MOSFETs is investigated by means of transient-current measurements. Both steady state and pulsed high bias, gate-drain stresses are applied to the devices and the change and recovery in RON, attributed to electron trapping, is monitored. Surprisingly, electron trapping is completely suppressed during pulsed-stress measurements, whereas long-duration, steady state bias stress leads to a dramatic increase in device RON. Long-duration bias stress is more representative of real-world device operation, and so this result highlights a key challenge to the commercialisation of this new technology.

Acceptor impurity doping is recognized as a functional tool to extend the capabilities and applications of β-Ga2O3. The effect of thermal annealing on photoexcited carriers was characterized by measuring the photocurrent spectra of nitrogen (N)-ion-implanted β-Ga2O3 crystals, where the N was found to cause less crystal damage to the crystal and much lower thermal diffusivity than Mg. The photocurrent intensity at 4.5–5.5 eV showed an increase with an increase in external bias, and the increase was attributed to the photo-generated non-equilibrium electrons and holes. The spectra under a positive external bias showed a distinct onset at 3.0–3.5 eV owing to optical transitions involving deep donor levels formed by the N-implantation. Spectrally integrated responsivity showed a significant change with the annealing temperature by reflecting the recovery of crystallinity and the thermal activation of N impurities. The results also indicate the formation of additional nonradiative recombination centers due to N-implantation.

An anomalous diode-like turn-on behavior was observed in the drain characteristics of current aperture vertical β-Ga2O3 transistors. This phenomenon was attributable to an electron barrier created by negative fixed charges in the aperture opening, through which electrons were funneled from the gated channel to the drift layer. Electrostatic analysis for deriving the turn-on voltage yielded effective sheet charge densities on the order of 1011–1012 cm−2. The charged species was conjectured to be acceptor-like point defects diffusing from nitrogen-implanted current blocking layers with an activation energy consistent with migration of gallium vacancies. These results alluded to a possible role of point-defect diffusion in the performance and reliability of ion-implanted Ga2O3 devices.

In this paper, we analyze the stability of the performance of β-Ga2O3 Schottky barrier diodes (SBDs) damaged by nitrogen implantation, based on electrical characterization and deep-level spectroscopy. We demonstrate that N-implanted SBDs show a high level of isolation, which can be further improved by electron trapping promoted by current flow and temperature. Charge trapping leads to a shift in the current–voltage curve to more positive bias, a positive effect lasting for hundreds of seconds at room temperature and fully recovered only after 200 s even at 350 K. This charge trapping process takes place in the depletion region of the Schottky diode, in a defect located 0.72 eV below the conduction band, possibly related to gallium vacancies. A model for explaining the trapping kinetics and processes is proposed, based on differential rate equations, highlighting two capture processes: charge injection from the n-type Ga2O3 into the space charge region and thermionic emission from the anode metal to the deep level.

The advent of acceptor-type doping of β-Ga2O3 through ion-implantation of nitrogen has opened a new design space for junction-type devices with estimated breakdown voltages in excess of a few kVs. However, the presence of deep states due to intrinsic defects in β-Ga2O3 and implantation damage could be detrimental to the performance and reliability of such devices. We give a phenomenological description and experimental demonstration of the effects of nitrogen implantation in a buried blocking layer on the performance of transistors. The partial activation of acceptor-like states in the buried implanted region has been revealed and estimated to be ∼20% through a junction spectroscopic technique involving substrate-bias and sub-bandgap illumination, which remains elusive to standard characterization techniques. The characterization technique, along with a space-charge model of the channel and band model of the buried implanted layer, has revealed the presence of photosensitive mid-bandgap (∼2.47 eV below the conduction band) and tail states near the valence band edge of nitrogen-implanted β-Ga2O3.

Ga2O3 has exploded onto the semiconductor landscape for next-generation power electronics because its enticing material properties, most notably a large critical field strength stemming from its ultra-wide bandgap of 4.5 eV, promise miniaturized circuits and systems with high conversion efficiency. High-quality native substrates produced by melt-growth methods offer an economical platform to this technology. Ga2O3 transistors reported to date have predominantly taken on a lateral geometry, yet vertical switching devices are desirable for applications that demand high voltage ratings and high power levels since they allow for large current drives, simplified thermal management, and superior field termination. Capitalizing on cost-effective ion implantation technologies for shallow donor (silicon) and deep acceptor (nitrogen) doping of Ga2O3 with efficient dopant activation at a low thermal budget, we developed both depletion-mode (D-mode) [1] and enhancement-mode (E-mode) [2] current aperture vertical Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs). The vertical Ga2O3 MOSFETs were fabricated on low-doped (~1016 cm-3) halide vapor phase epitaxial drift layers grown on single-crystal β-Ga2O3 (001) substrates [3]. In these devices, silicon ion-implanted top source contacts were electrically isolated from the bottom drain contact by a nitrogen ion-implanted current blocking layer (CBL) [4] except at an aperture bounded by CBLs through which drain current was conducted. The CBL simultaneously served as a back-barrier for a top-gated lateral channel defined by another silicon ion implantation step. D-mode devices delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and an output current on/off ratio of over 108. E-mode devices, whose positive threshold voltage was attained by appropriately designing the channel doping concentration such that the channel was fully depleted at 0-V gate bias, showed a high output current on/off ratio of 2×107 despite a nonideal MOS interface that limited the maximum drain current density to 2. Both D-mode and E-mode devices did not exhibit current collapse in pulsed measurements when subjected to off-state voltage stress; however, their hard breakdown occurred prematurely owing to leakage through the CBLs, a deficiency expected to be readily overcome with an optimized nitrogen implantation process. Further details regarding fabrication, performance, and physics of the devices, as well as potential directions for future development, will be discussed in the talk. The demonstration of planar-gate vertical Ga2O3 transistors based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics applications. [1] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, 431 (2019). [2] M. H. Wong, H. Murakami, Y. Kumagai, and M. Higashiwaki, Proc. 77th Device Research Conference (2019). [3] H. Murakami, K. Nomura, K. Goto, K. Sasaki, K. Kawara, Q. T. Thieu, R. Togashi, Y. Kumagai, M. Higashiwaki, A. Kuramata, S. Yamakoshi, B. Monemar, and A. Koukitu, Appl. Phys. Express 8, 015503 (2015). [4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).

Comparison between pulsed and CW large signal RF performance of field-plated $\beta $ -Ga2O3 MOSFETs has been reported. Reduced self-heating when pulse resulted in a power added efficiency of 12%, drain efficiency of 22.4%, output power density of 0.13 W/mm, and maximum gain up to 4.8 dB at 1 GHz for a 2- $\mu \text{m}$ gate length device. Increased power dissipation for higher ${V} _{\textsf {DS}}$ and ${I} _{\textsf {DS}}$ resulted in a degradation in performance, which, thermal simulation showed, could be entirely explained by self-heating. Buffer and surface trapping contributions have been evaluated using gate and drain lag measurements, showing minimal impact on device performance. These results suggest that $\beta $ -Ga2O3 is a good candidate for future RF applications.

Historically, the exploration of III-V compound semiconductors has begun with small bandgap materials and proceeded to large bandgap ones in recent years, that is, from GaAs-based compounds to GaN-based ones. We consider that gallium oxide (Ga 2 O 3 ) is no exception in following this history and is poised to become the next mainstream of compound semiconductor research due to its attractive material properties based on an extremely large bandgap of about 4.5 eV [1]. This bandgap energy is not only much larger than those of representative wide bandgap semiconductors such as GaN and SiC but also unique among single-crystal semiconductors. Furthermore, Ga 2 O 3 has another important advantage for commercialization over the other wide bandgap materials in that large-size, high-quality bulk single crystals can be synthesized by melt growth methods, thus allowing native substrates to be produced at a relatively low cost [2]. Recently, these two features have drawn much attention to Ga 2 O 3 , resulting in a rapid expansion of the Ga 2 O 3 community.

Gallium oxide (Ga2O3) has emerged as a new competitor to SiC and GaN in the race toward next-generation power switching and harsh environment electronics by virtue of the excellent material properties and the relative ease of mass wafer production. In this proceedings paper, an overview of our recent development progress of Ga2O3 metal-oxide-semiconductor field-effect transistors and Schottky barrier diodes will be reported.

In0.53Ga0.47As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In0.53Ga0.47As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III–V on Si sample and the control that perform similarly below $8.6 \times 10^{-10}$ cm $^{2}$ . The existence of a critical device area suggests the potential to utilize III–V on Si for other deeply scaled tunnel devices.

Gallium oxide (Ga 2 O 3 ) is attractive for power devices owing to its wide bandgap of 4.5 eV and the availability of economical device-quality native substrates. Research on Ga 2 O 3 Schottky barrier diodes and field-effect transistors (FETs) has seen rapid recent progress [1]. An unexplored area of immense interest is the radiation tolerance of these devices, whose high-voltage and high-temperature capabilities are expected to find applications in extreme radiation environments such as space and nuclear facilities that impose stringent reliability requirements to ensure stable operations. This paper reports the first investigation into the effects of ionizing radiation on Ga 2 O 3 metal-oxide-semiconductor FETs (MOSFETs). A gamma-ray (y-ray) tolerance as high as 230 kGy(SiO 2 ) was demonstrated for the bulk Ga2O3 channel by virtue of the MOSFETs' stable on-current, on-resistance (R on ), and threshold voltage (V t ) against irradiation. Hysteresis in the transfer characteristics remained negligible after exposure to the highest dose. Radiation-induced degradations in the gate insulation and surface passivation, which could be attributed to dielectric damage and interface trap generation, were found to limit the overall radiation resistance of these devices.

β-Ga 2 O 3 is being actively pursued for power devices owing to its wide bandgap of 4.5 eV and the availability of melt-grown native substrates for high quality epitaxy. Depletion and enhancement mode Ga 2 O 3 metal-oxide-semiconductor field-effect transistors (MOSFETS) reported to date have been implemented as lateral devices. For high voltage and high power ratings, vertical topologies are preferred since chip area utilization is more efficient and device operation is insensitive to surface effects. This paper presents the first experimental demonstration of a vertical Ga 2 O 3 MOSFET, wherein the source was electrically isolated from the drain by a current blocking layer (CBL) except at an aperture opening through which drain current (I DS ) was conducted [1]. Modulation of I DS was effected by gating a channel above the CBL. Similar to Si and SiC technologies, this planar device structure was fabricated with no regrowth steps. The buried CBL, which acted as a back barrier for the channel, was formed by Mg-ion (Mg++) implantation doping in light of the anticipated deep acceptor nature of Mg in β-Ga 2 O 3 . Despite large source-drain leakage due to an unoptimized CBL, successful transistor action was realized.

Within this paper, we report the first study on the reliability of isolation structures and surfaces for the gallium oxide material system. Even though insulation by Mg-doping implantation and diffusion is found to provide a stable electrical isolation at increasing temperature, a significant thermally-activated leakage flows through surface states. The vertical bulk material does provide a better stability of the isolation over stress time, but withstands a lower level of stress compared with the surface and the lateral structure, possibly due to the charge trapping at the surface of the latter that mitigates the peak electric field.

Ga2O3 has gained worldwide interests for next-generation power electronics because its large critical field strength stemming from an ultra-wide bandgap promises miniaturized circuits and systems with high conversion efficiency. Intense pursuit of Ga2O3 power devices stimulated by early demonstrations of high-voltage Ga2O3 field effect transistors (FETs) has brought about tremendous advancements in this new technology, whose strong radiation tolerance and high thermal stability also befit harsh-environment applications. In this paper, we review the various types of depletionand enhancement-mode Ga2O3 FETs — which have predominantly been lateral devices — for power switching and radiation-hard electronics. The development of vertical Ga2O3 transistors based on a low-cost, highly-manufacturable ion implantation doping process will also be discussed.

We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primary location of long time constant traps. We examine the impact of these trap states on threshold voltage engineering of the gate stack. Enhancement mode operation of HEMTs is demonstrated, and the stability of enhancement mode is discussed.

The channel temperature (T ch ) and thermal resistance (R th ) of Ga 2 O 3 metal-oxide-semiconductor field effect transistors were evaluated for the first time through electrical measurements complemented by device simulations that incorporated experimental Ga 2 O 3 thermal parameters. The analysis technique was based on a comparison between DC and pulsed drain currents (I DS ) at known applied drain biases (V DS ), where negligible self-heating under pulsed conditions enabled approximation of T ch to the ambient temperature (T amb ) and hence correlation of I DS to T ch over a range of V DS . Validation of the device model was achieved through calibration against the DC data. The experimental T ch was in good agreement with simulations for T amb between 20°C and 175°C. The large R th thus extracted highlights the value of thermal analysis for Ga 2 O 3 power devices.

An anomalous output conductance that resembled short-channel effects was observed in long-channel N-polar GaN-channel/AlGaN-back-barrier/GaN-buffer high electron mobility transistors. The phenomenon could not be reasonably explained by drain-induced barrier lowering, leakage currents, or impact ionization events. We propose that the output conductance was caused by the ionization of a donorlike hole trap state at the negatively polarized AlGaN-back-barrier/GaN-buffer interface that shifted the threshold voltage at the drain side of the gate, where a high-field depletion region developed beyond current saturation. No evidence of increased output conductance or related device performance degradation was apparent under small-signal high-frequency conditions. The output conductance was suppressed by introducing photogenerated holes that compensated the traps. The effect of several typical back-barrier designs on the dc output conductance was examined.

Compound semiconductors belong to the most important materials for optoelectronic applications. Many of them exhibit favorable optical properties, such as a direct energy band gap (in contrast to silicon) and high-absorption coefficients over a wide spectral range. Moreover, varying the composition of the compound or substituting some of its elements often allows for controlled band gap engineering and optimization for specific applications. Because many compound semiconductors enable efficient conversion of light into electricity and vice versa, they are commonly used materials for optoelectronic devices.

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj¬5x1019cm-3, ρc= 6 Ω.µm2 and Dit = 4 x 1012 eV-1.cm-2.

Deep acceptor doping of β-Ga2O3 with Mg and N was demonstrated by implantation of the impurity ions into n-type bulk substrates. Systematic physical and electrical characterizations were performed to demonstrate recovery of the implantation-damaged crystals and electrical activation of the dopant atoms by thermal annealing at 1000–1200 °C in an N2 atmosphere. N was found to exhibit much lower thermal diffusivity than Mg, thus enabling the use of higher annealing temperatures to maximize N activation efficiency without significantly altering the impurity profile. Consequently, an n-Ga2O3/Ga2O3:N/n-Ga2O3 structure was capable of sustaining a much larger voltage across its end terminals than its Mg-doped counterpart. The development of an ion implantation technology for acceptor doping of β-Ga2O3 creates unique opportunities for designing and engineering a variety of high-voltage β-Ga2O3 devices.

A vertical β-Ga2O3 metal–oxide–semiconductor field-effect transistor featuring a planar-gate architecture is presented. The device was fabricated by an all-ion-implanted process without requiring trench etching or epitaxial regrowth. A Mg-ion-implanted current blocking layer (CBL) provided electrical isolation between the source and the drain except at an aperture opening through which drain current was conducted. Successful transistor action was realized by gating a Si-ion-implanted channel above the CBL. Thermal diffusion of Mg induced a large source–drain leakage current through the CBL, which resulted in compromised off-state device characteristics as well as a reduced peak extrinsic transconductance compared with the results of simulations.

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

We present a high-performance SiN/AlGaN (cap)/GaN (channel)/AlN (barrier)/GaN (buffer) metal-insulator-semiconductor high-electron-mobility transistor grown on the N-face, in which the 2-D electron gas (2DEG) is induced at the top GaN/AlN interface. The use of AlN eliminates alloy disorder scattering to the 2DEG and provides strong back-barrier confinement of the 2DEG under high electric fields for device scaling. Devices with 0.7-mum gate length showed a current-gain cutoff frequency (fT) of 17 GHz and a power-gain cutoff frequency (f max) of 37 GHz. A continuous-wave output power density of 7.1 W/mm was measured at 4 GHz, with 58% power-added efficiency and a large-signal gain of 15.3 dB at a drain bias of 35 V.

N-polar (000) and Ga-polar (0001) GaN templates were patterned with holographic lithography and etched to form nanopillars (NP) and nanostripes (NS) arrays, upon which InGaN and GaN was subsequently regrown by metal organic chemical vapor deposition (MOCVD). A wide range of growth conditions were explored to determine the structural impact of the growth conditions. The results were evaluated by scanning electron microscopy (SEM), and transmission electron microscopy (TEM). It was observed that the initial polarity of the GaN template used to form the pillar or stripe nanostructures had a significant impact upon the results of the regrowth. The Ga-polar NP exhibited (0001), {010}, and {011} facets, while the N-polar NP exhibited (000) and {010} facets. The NS samples also exhibited different facet formation depending upon the initial polarity. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

N-polar (000-1) GaN templates were patterned using holographic lithography to create nanopillar (NP) and nanostripe (NS) arrays. InGaN and GaN was subsequently regrown on the patterned wafers by metalorganic chemical vapor deposition (MOCVD). The impact of changes in V/III ratio and growth temperature were investigated using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and photoluminescence (PL). Highly selective growth of InGaN and GaN on planes close to the {10-10} m-planes was observed over a wide range of growth conditions as well as different facet formation compared to regrowth on Ga-polar (0001) NP and NS arrays.

Gallium oxide (Ga2O3) possesses excellent material properties especially for power device applications. It is also attractive from an industrial viewpoint since large-size, high-quality wafers can be manufactured by using simple methods. These two features have drawn much attention to Ga2O3 as a new wide bandgap semiconductor following SiC and GaN. In this report, we describe the recent progress in development on fundamental technologies for Ga2O3 devices, covering wafer production from melt-grown bulk single crystals, homoepitaxial thin-film growth by halide vapor phase epitaxy, as well as device processing and characterization of metal-oxide-semiconductor field-effect transistors and Schottky barrier diodes.

High-electron-mobility transistor (HEMT) structures were regrown by molecular beam epitaxy on GaN-on-SiC templates and free-standing (FS) GaN substrates with very low threading dislocation density (TDD). To ensure a high buffer breakdown voltage, the thickness of the unintentionally doped (UID) GaN buffer layer, d UID, was reduced to 200 nm for the HEMTs regrown on FS GaN. A reduction in TDD entailed an increase in the three-terminal breakdown voltage for passivated HEMTs. With a low d UID, the proximity effects of the carbon-doped GaN buffer were evident. A power-added efficiency (PAE) of 37% and continuous-wave power output (P out) of 4.2 W/mm were measured at 4 GHz with a drain bias of 40 V for a HEMT on FS GaN without a back barrier. By including a 5 nm Al0.3Ga0.7N back barrier, PAE and P out improved to 50% and 6.7 W/mm, respectively, at a drain bias of 40 V.

ZnO nano-rods were grown on polycrystalline Zn foil by cathodic electrodeposition in an aqueous zinc chloride/calcium chloride solution at 80?C. Variations in the solution concentration and substrate surface preparation were explored to shed light on the nucleation of the nano-rods. It was found that the nano-rod diameter increased with increasing solution concentration. Rolling striations and native ZnO on the surface of the Zn appeared to enhance nucleation and allowed more highly aligned, dense structures to be grown. By using low solution concentrations (5.0 ? 10?4?M?ZnCl 2) and non-electropolished Zn substrates, well faceted, hexagonal nano-rod structures of dimension ~80?nm diameter and }1\ntilde \micmu {\mathrm {m}}$>>1??m length were obtained. X-ray studies showed the samples to be highly aligned but containing a Zn-oxychloride impurity phase. Annealing caused the impurity phase to disappear and resulted in the films having a sharp photoluminescence double peak at 380/396 nm.

A current aperture vertical electron transistor (CAVET) with a Mg-ion-implanted current blocking layer (CBL) and a channel regrown by plasma assisted molecular beam epitaxy (MBE), is successfully demonstrated on bulk GaN to work as a high voltage device. The fabrication of the device combined a drift region grown by metalorganic chemical vapor deposition (MOCVD), to hold the blocking voltage, with AlGaN/GaN layers regrown by plasma-MBE to conduct current. The device registered a maximum current of 4 kA· cm-2 under direct-current operation offering a specific on-state resistance Ron - A of 2.2 mΩ·cm2. With 80 μs pulses applied to the gate, the devices showed no dispersion. The increased aperture length Lap resulted in the decrease in specific Ron, as expected. The impact of the gate overlap to aperture Lgo on the leakage current was studied, where the leakage current was found to increase with a smaller overlap.

We report enhanced dc and small-signal RF performance of enhancement-mode (E-mode) metal-oxide-semiconductor heterojunction field-effect transistors (MOS-HFETs) in N-polar GaN technology with an ultrathin 5-nm GaN channel and graded AlGaN back-barrier structure with a record on-resistance (Ron) of 0.66 Ω·mm. The device has a maximum drain current (Id) of 1.15 A/mm, a peak transconductance (gm) of 510 mS/mm, and a peak current-gain cutoff frequency (ft) of 122 GHz, with a positive threshold voltage (Vth) of 1.6 V. The device shows improved saturation and pinchoff characteristics compared to the previously reported N-polar E-mode HFETs with a maximum Ion/Ioff ratio of 2.2 × 105.

Enhancement-mode β-Ga2O3 metal–oxide–semiconductor field-effect transistors with low series resistance were achieved by Si-ion implantation doping of the source/drain contacts and access regions. An unintentionally doped Ga2O3 channel with low background carrier concentration that was fully depleted at a gate bias of 0 V gave rise to a positive threshold voltage without additional constraints on the channel dimensions or device architecture. Transistors with a channel length of 4 µm delivered a maximum drain current density (I DS) of 1.4 mA/mm and an I DS on/off ratio near 106. Nonidealities associated with the Al2O3 gate dielectric as well as their impact on enhancement-mode device performance are discussed.

We report gate-first enhancement-mode (E-mode) N-polar GaN MISFET devices with self-aligned source/drain regions by molecular beam epitaxy regrowth and with a SiNx gate dielectric. E-mode operation at Vds = 4.0 V is demonstrated for devices with gate lengths >; 0.18 μm with a 20-nm GaN channel and a high-temperature SiNx gate dielectric. A high drain current of 0.74 A/mm was measured for an Lg = 0.62-μm device with a peak transconductance of 225 mS/mm and a positive threshold voltage of 1 V. The on resistance of the device was 2 Ω·mm. Devices show short-channel effect with decreasing gate lengths.

We present a deep-recessed nitrogen-polar AlGaN/GaN MIS-HEMT employing a V-gate structure recessed through a thick GaN cap to prevent dc-to-RF dispersion. A process for selectively dry etching N-polar GaN over AlGaN has been established to achieve repeatable etch depth for the gate recess. Devices with a drawn gate length of 0.7- μm showed a current-gain cutoff frequency (fT) of 15 GHz and a power-gain cutoff frequency (fmax) of 42 GHz. A continuous-wave output power density of 5.5 W/mm was measured at 4 GHz, with a record associated power-added efficiency of 74% and a large-signal gain of 14.5 dB at a drain bias of 24 V.

Depletion-mode Ga2O3 MOSFETs were fabricated on single-crystal β-Ga2O3 (010) substrates. We applied Si-ion implantation to the ohmic contacts for low contact resistance as well as to the channel layer for reliable doping. An Al2O3 gate dielectric film formed by atomic layer deposition passivated the device surface and significantly reduced gate leakage. The MOSFETs with a simple structure exhibited complete channel pinch-off with a breakdown voltage of 415 V and a drain current on/off ratio of ten orders of magnitude at room temperature. The devices also showed stable operation up to 250°C.

A high-performance N-face GaN metal-insulator-semiconductor high-electron-mobility transistor was fabricated. A dual-AlN back-barrier scheme was developed using polarization engineering to provide a large total dipole moment, which allowed enhanced modulation doping for a higher 2-D electron gas density without parallel conduction. Devices with 0.6-mum gate length showed an fT and f max of 17 and 58 GHz, respectively. A highest power-added efficiency (PAE) of 71% at 4 GHz was measured in these devices with 20-V drain bias. At 28 V, an output power density of 6.4 W/mm with 67% PAE was achieved.

We present a systematic study of the impact of CF4 plasma treatment on GaN. It was found that CF4 plasma etches GaN at a slow rate and yields a smooth etched surface. The effect of CF4 plasma on electrical characteristics of GaN metal-semiconductor field-effect-transistor structures shows that the CF4 plasma introduces acceptors into the near surface region of the GaN, which depletes mobile electrons. It was further demonstrated that leakage current of AlGaN/GaN (or GaN) Schottky diodes can be significantly suppressed by proper CF4 plasma treatment. These unique properties of CF4 plasma can be utilized for the advanced processing of GaN transistors.