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The triple heterojunction tunnel field-effect transistor (TFET) has been originally proposed to resolve the TFET’s low ON-current challenge. The carrier transport in such devices is complicated due to the presence of quantum wells and strong scattering. Hence, the full-band atomistic nonequilibrium Green’s function (NEGF) approach, including scattering, is required to model the carrier transport accurately. However, such simulations for devices with realistic dimensions are computationally unfeasible. To mitigate this issue, we have employed the empirical tight-binding mode-space approximation to simulate the triple heterojunction TFETs with the body thickness up to 12 nm. The triple heterojunction TFET design is optimized using the model to achieve a sub-60-mV/decade transfer characteristic under realistic scattering conditions.

Copper nanowires are widely used as on-chip interconnects due to their superior conductivity. However, with aggressive Cu interconnect scaling, surface scattering of electrons drastically increases the electrical resistivity. In this work, we have studied the electrical performance of Cu thin films deposited on different materials. By comparing the thickness dependence of Cu films' resistivity on MoS2 and SiO2, we have demonstrated that MoS2 can be used to enhance the electrical performance of ultrathin Cu films due to improved specular surface scattering by up to 40%. By fitting the experimental data with the theoretical Fuchs-Sondheimer (FS) model, we have determined the specularity parameter at the Cu/MoS2 interface to be p ≈ 0.4 at room temperature. Furthermore, first principle calculations based on density functional theory (DFT) indicate that the localized density of states (LDOS) at the Cu/amorphous SiO2 interface is larger than the LDOS at the Cu/MoS2 interface, which is believed to be responsible for the higher resistivity in the Cu thin films that are deposited on SiO2 substrates. Our results suggest that MoS2 may serve as a performance enhancer for future generations of Cu interconnects.

Being fundamentally limited to a current–voltage steepness of 60mV/dec, MOSFETs struggle to operate below 0.6 V. Further reduction in ${V}_{\text {DD}}$ and, consequently, power consumption can be achieved with novel devices, such as tunneling transistors (TFETs) that can overcome this limitation. TFETs, however, face challenges with low ON-current leading to slow performance. TFETs made from III-nitride heterostructures are quite promising in this regard. The lattice mismatch induces a piezoelectric polarization field in a nitride heterojunction that can boost the ON-current. However, it is shown here that the carrier thermalization at the heterointerface degrades the subthreshold characteristics. Therefore, a good design should minimize the number of confined quantum well (QW) states at the heterointerface so as not to degrade the subthreshold characteristics while maintaining the lattice mismatch induced polarization to boost the ON-current. We show here that an InAlN QW on an InGaN substrate alloy engineered TFET design is promising to fulfill these requirements. Proper engineering of the alloy mole fractions and the width of the well can eliminate (or at least minimize) the undesired thermalization effects and, at the same time, provide a lattice mismatch to induce a piezoelectric field for boosting the ON-current. We have used a suitable atomistic quantum transport model to simulate these devices. The model accounts for the different mechanisms that are involved, and captures realistic scattering thermalization effects. This model has been benchmarked in our earlier work with experimental measurements of nitride tunneling heterojunction diodes and is used here to optimize the alloy engineered nitride TFET.

Triple heterojunction (THJ) tunneling field-effect transistors (TFETs) have been proposed to resolve the low ON-current challenge of TFETs. However, the design space for THJ-TFETs is limited by fabrication challenges with respect to device dimensions and material interfaces. This work shows that the original THJ-TFET design with 12-nm body thickness has poor performance because its subthreshold swing (SS) is 50 mV/decade and the ON-current is only $6~\mu A/\mu m$ . To improve the performance, the doping profile of THJ-TFET is engineered to boost the resonant tunneling efficiency. The proposed THJ-TFET design shows an SS of 40 mV/decade over four orders of drain current and an ON-current of $325~\mu A/\mu m$ with ${V}_{\textit {GS}} =0.3$ V. Since THJ-TFETs have multiple quantum wells and material interfaces in the tunneling junction, quantum transport simulations in such devices are complicated. State-of-the-art mode-space quantum transport simulation, including the effect of thermalization and scattering, is employed in this work to optimize THJ-TFET design.

The metal-semiconductor contact resistivity has started to play a critical role for the overall device performance as Si is reaching 10-nm size ranges. The International Technology Roadmap for Semiconductors (ITRS) target predicts a requirement of $\text{10}^{-9} \; \Omega {\cdot} \text{cm}^{2}$ by 2023 which has been a challenging target to achieve. This paper explores the impact of doping concentration, Schottky barrier height, strain, and SiGe mole fraction on the resistivity of Si/SiGe p-type metal-oxide semiconductor (PMOS) contacts with 20-band atomistic tight binding quantum transport simulations. Commonly used simple effective mass approximation models are shown to overestimate the resistivity values. The predicted model results are compared with experimental data and the device parameters needed to achieve $\text{10}^{-9} \; \Omega {\cdot} \text{cm}^{2}$ are identified.

In this work, vertical tunnel field-effect transistors (v-TFETs) based on vertically stacked heretojunctions from 2D transition metal dichalcogenide (TMD) materials are studied by atomistic quantum transport simulations. The switching mechanism of v-TFET is found to be different from previous predictions. As a consequence of this switching mechanism, the extension region, where the materials are not stacked over is found to be critical for turning off the v-TFET. This extension region makes the scaling of v-TFETs challenging. In addition, due to the presence of both positive and negative charges inside the channel, v-TFETs also exhibit negative capacitance. As a result, v-TFETs have good energy-delay products and are one of the promising candidates for low power applications., Comment: didn't reach to co-author agreement

Controlled, tunable, and reversible negative-differential resistance (NDR) is observed in lithographically defined, atomically thin semiconducting graphene nanoribbon (GNR)-gated Esaki diode transistors at room temperature. Sub-10 nm-wide GNRs patterned by electron-beam lithography exhibit semiconducting energy bandgaps of ~0.2 eV extracted by electrical conductance spectroscopy measurements, indicating an atomically thin realization of the electronic properties of conventional 3D narrow-bandgap semiconductors such as InSb. A p–n junction is then formed in the GNR channel by electrostatic doping using graphene side gates, boosted by ions in a solid polymer electrolyte. Transistor characteristics of this gated GNR p–n junction exhibit reproducible and reversible NDR due to interband tunneling of carriers. All essential experimentally observed features are explained by an analytical model and are corroborated by a numerical atomistic simulation. The observation of tunable NDR in GNRs is conclusive proof of the existence of a lithographically defined bandgap and the thinnest possible realization of an Esaki diode. It paves the way for the thinnest scalable manifestation of low-power tunneling field-effect transistors (TFETs).

In this work, the performance of Tunnel Field-Effect Transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2D material based TFETs can have tight gate control and high electric fields at the tunnel junction, and can in principle generate high ON-currents along with a sub-threshold swing smaller than 60 mV/dec. Our simulations reveal that high performance TMD TFETs, not only require good gate control, but also rely on the choice of the right channel material with optimum band gap, effective mass and source/drain doping level. Unlike previous works, a full band atomistic tight binding method is used self-consistently with 3D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON-currents are explained with a simple analytic model, showing the related fundamental factors. Finally, the subthreshold swing and energy-delay of these TFETs are compared with conventional CMOS devices., 7 pages, 8 figures. The revised version is uploaded

New designs for vertical 2D-materials-based TFETs are proposed in this paper adopting asymmetric layer numbers for the top and bottom layer with undoped source/drain using Black Phosphorus as an example. The results show that abrupt turn-on and I on /I off > 105 can be sustained when the channel length is down to sub-5 nm. The results are benchmarked against other TFETs based on promising 2D materials homo-/hetero-structures, meanwhile, the limitations, as well as guidelines, are presented.

As interconnects become smaller, their conductivity increases along with the parasitic effects in MOSFET technologies [1] Therefore, investigating how to model the scattering effects on the nanoscale is important to determine how to engineer interconnects toreduce those parasitic effects. In this work, a fully atomistic method is studied to model the electronic transport properties of copper thin films. For this purpose, a tight binding basis previously benchmarked against first principles calculations [2] is used todescribe surface roughness and grain boundary effects on comparablepper thin films with a thickness comparable to the values suggested by ITRS roadmap [3]. In contrast with traditional models, the results show that the tight binding method can quantify those scattering effects at low temperature without fitting any experimental parameters [4], [5].

Artificial semiconductors with manufactured band structures have opened up many new applications in the field of optoelectronics. The emerging two-dimensional (2D) semiconductor materials, transition metal dichalcogenides (TMDs), cover a large range of bandgaps and have shown potential in high performance device applications. Interestingly, the ultrathin body and anisotropic material properties of the layered TMDs allow a wide range modification of their band structures by electric field, which is obviously desirable for many nanoelectronic and nanophotonic applications. Here, we demonstrate a continuous bandgap tuning in bilayer MoS2 using a dual-gated field-effect transistor (FET) and photoluminescence (PL) spectroscopy. Density functional theory (DFT) is employed to calculate the field dependent band structures, attributing the widely tunable bandgap to an interlayer direct bandgap transition. This unique electric field controlled spontaneous bandgap modulation approaching the limit of semiconductor-to...

Traditional thinking assumes that a light effective mass ( $m^*$ ), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light $m^*$ may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance ( $C_q$ ). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum $m^*$ for sub-12-nm nanowire down to channel length of 3 nm. Optimum $m^*$ are found to range between 0.2–1.0 $m_0$ and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. $m^*$ is no longer a material constant, but a geometry and strain dependent property of the channel material.

Full-band quantum transport simulations are performed to study the scaling of InGaAs MOSFETs. Short-channel effects evoke severe performance degradation in InGaAs MOSFETs and the tunneling leakage further deteriorates their performances. Reducing the body width is shown to suppress the short channel effects. Doping densities show big impacts on device performances. With inhomogeneous doping InGaAs could outperform Si at gate lengths below 15 nm with 5-nm body width. The density of state bottleneck does not affect InGaAs in simulated devices at 0.5 V supply voltage. At the ultrascaled dimensions the full band simulations are essential to capture strong nonparabolic dispersion. Comparison with a multivalley effective mass model shows that the population of higher conduction band valleys contributes to the total current at thin body widths.

The concept and simulated device characteristics of tunneling field-effect transistors (TFETs) based on III-nitride heterojunctions are presented for the first time. Through polarization engineering, interband tunneling can become significant in III-nitride heterojunctions, leading to the potential for a viable TFET technology. Two prototype device designs, inline and sidewall-gated TFETs, are discussed. Polarization-assisted p-type doping is used in the source region to mitigate the effect of the deep Mg acceptor level in p-type GaN. Simulations indicate that TFETs based on III-nitride heterojunctions can be expected to achieve ON/ OFF ratios of $10^{6}$ or more, with switching slopes well below 60 mV/decade, ON-current densities approaching 100 $\mu \text{A}/\mu \text{m}$ , and energy delay products as low as 67 aJ-ps/ $\mu \text{m}$ .

Atomistic quantum transport simulation of realistically large devices is computationally very demanding. The widely used mode space (MS) approach can significantly reduce the numerical cost but good MS basis is usually very hard to obtain for atomistic full-band models. In this work, a robust and parallel algorithm is developed to optimize the MS basis for atomistic nanowires. This enables tight binding non-equilibrium Green's function (NEGF) simulation of nanowire MOSFET with realistic cross section of $\rm 10nm\times10nm$ using a small computer cluster. This approach is applied to compare the performance of InGaAs and Si nanowire nMOSFETs with various channel lengths and cross sections. Simulation results with full-band accuracy indicate that InGaAs nanowire nMOSFETs have no drive current advantage over their Si counterparts for cross sections up to about $\rm 10nm\times10nm$., 8 pages (double column), 13 figures, 1 table

With continuous shrinking of devices in accordance with Moore's law, metal-semiconductor resistivity starts playing an important role for device performance. To meet ITRS target of 10−9 Ω·cm2 by 2023, it is important to evaluate the effect of different device parameters such as doping concentration, Schottky barrier height, strain and SiGe mole fraction on contact resistivity. In this work, such a resistivity study has been done on Si/SiGe PMOS contacts through 10-band atomistic tight binding quantum transport simulations. Optimum target values for barrier height as a function of doping concentration are obtained.

VLSI devices are constrained by CF dd 2/2 power dissipation. Low power dissipation requires low V dd , yet reducing V dd increases I off . Tunnel FETs (TFETs) have steep subthreshold swings (S.S.) and can operate at low V dd , yet their I on is limited by low tunneling probability. This low I on results in large CV dd /I delay and slow logic operation. For greatly increased Ion, we had proposed a triple-heterojunction (3HJ) TFET design incorporating source and channel heterojunctions (HJ) [1, 2]. The designs of [1, 2] have an InAlAsSb channel, yet no low-trap-density dielectric interfaces to InAlAsSb have been reported. In contrast, low-trap-density dielectric interfaces have been demonstrated to InAs, InGaAs, and InP [3, 4, 5]. Here we propose an InGaAs/GaAsSb/InAs/InP 3HJ TFET design, with growth lattice-matched to InP. The gated channel surface is InAs and InP, and thus can have low trap density. The p-type side of the tunnel junction is GaAsSb, instead of strained GaSb [6], as compressive strain increases the hole transport effective mass, reducing the tunneling probability. In ballistic simulations, with I off = 10 3 μA/μm and V dd =0.3V, I on is an extremely high 540μA/μm. Even when simulated assuming incoherent quantum transport, with acoustic and optical phonon scattering modelled, I on remains very high at 250μA/μm.

Steep transistors are crucial in lowering power consumption of the integrated circuits. However, the difficulties in achieving steepness beyond the Boltzmann limit experimentally have hindered the fundamental challenges in application of these devices in integrated circuits. From a sensitivity perspective, an ideal switch should have a high sensitivity to the gate voltage and lower sensitivity to the device design parameters like oxide and body thicknesses. In this work, conventional tunnel-FET (TFET) and negative capacitance FET are shown to suffer from high sensitivity to device design parameters using full-band atomistic quantum transport simulations and analytical analysis. Although Dielectric Engineered (DE-) TFETs based on 2D materials show smaller sensitivity compared with the conventional TFETs, they have leakage issue. To mitigate this challenge, a novel DE-TFET design has been proposed and studied.

In this paper, electrostatically configurable 2D tungsten diselenide (WSe2 ) electronic devices are demonstrated. Utilizing a novel triple-gate design, a WSe2 device is able to operate as a tunneling field-effect transistor (TFET), a metal-oxide-semiconductor field-effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band-to-band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self-consistent full-band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub-60 mV dec-1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low-power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.

Magnetotransport measurements on electron bilayer systems under low frequency continuous microwave irradiation reveal an anomalous magnetoresistance behavior. At low total imbalanced carrier densities, pronounced features in the longitudinal and Hall resistance emerge that show a surprisingly strong sensitivity to frequency, microwave power, and density. We suggest its origin to be related to resonantly induced capacitance oscillations of the two-layer system.Magnetotransport measurements on electron bilayer systems under low frequency continuous microwave irradiation reveal an anomalous magnetoresistance behavior. At low total imbalanced carrier densities, pronounced features in the longitudinal and Hall resistance emerge that show a surprisingly strong sensitivity to frequency, microwave power, and density. We suggest its origin to be related to resonantly induced capacitance oscillations of the two-layer system.

We report design of double-gate metal-oxide-semiconductor field-effect-transistors having InGaAs/InAlAs superlattices between the N+ source and a planar InGaAs channel. As with nanowire superlattice transistors, the 2-D superlattice bandgap reduces injection into the channel of electrons having energy above the source Fermi energy. Simulated ballistic transport characteristics of FETs using a three-well superlattice show 29-37.5-mV/decade minimum subthreshold swing and 390-A/m ON-current given 0.1-A/m OFF-current and a 0.2 V power supply.

The exact location of a single dopant atom in a nanostructure can influence or fully determine the functionality of highly scaled transistors or spin-based devices. We demonstrate here a noninvasive spatial metrology technique, based on the microscopic modeling of three electrical measurements on a single-atom (phosphorus in silicon) spin qubit device: hyperfine coupling, ground state energy, and capacitive coupling to nearby gates. This technique allows us to locate the qubit atom with a precision of +/- 2.5 nm in two directions and +/- 15 nm in the third direction, which represents a 1500-fold improvement with respect to the prefabrication statistics obtainable from the ion implantation parameters.

Molybdenum disulfide (MoS 2 ) is a promising 2D material since it has a finite band gap, and its electronic band structure depends on the layer thickness. The tunability of the gate voltage on band alignment of different MoS 2 layers is analyzed. For this purpose, the multipurpose nanodevice simulation tool NEMO5 was altered by several new features: electronic bandstructure calculations in maximally localized Wannier function (MLWF) representation and self-consistent charge calculations with subatomic electrostatic resolution.

As logic devices continue to downscale, interconnections are reaching the nanoscale where quantum effects are important. In this work we introduce a semi-empirical method to describe the resistance of copper interconnections of the sizes predicted by ITRS roadmap. The resistance calculated by our method was benchmarked against DFT for single grain boundaries. We describe a computationally efficient method that matches DFT benchmarks within a few percent. The 1000x speed up compared to DFT allows us to describe grain boundaries with a 30 nm channel length that are too large to be simulated by ab-initio methods. The electrical resistance of these grain boundaries has a probability density distribution as a function of the grain rotation angles. This approach allows us to quantitatively obtain the most likely resistance for each configuration.

Future ultra-scaled logic and low-power systems require fundamental advances in semiconductor device technology. Due to power constraints, device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade are essential if scaling of conventional computational architectures is to continue. Likewise, ultra low power systems also benefit from devices capable of maintaining performance under low-voltage operation. Towards this end, tunneling field effect transistors (TFETs) are one promising alternative. While much work has been devoted to realizing TFETs in Si, Ge, and narrow-gap III–V materials, the use of III-N heterostructures and the exploitation of polarization engineering offers some unique opportunities. From physics-based simulations, performance of GaN/InGaN/GaN heterostructure TFETs appear capable of delivering average SS approaching 20 mV/decade over 4 decades of drain current, and on-current densities exceeding 100 µA/µm in aggressively scaled nanowire configurations. Experimental progress towards realizing III-N based TFETs includes demonstration of GaN/InGaN/GaN backward tunnel diodes by both MOCVD and MBE, and nanowires grown selectively by MBE and used as the basis for device fabrication.

Strain has been widely used to engineer electronic devices by altering the material band structures. Recently it has also been employed to improve the performance of tunneling field-effect transistors (TFETs). A TFET is a steep subthreshold swing (SS) device that is very promising in building future low-power integrated circuits. But its drive current (I ON ) is usually limited leading to pronounced switching delay (CV/I). It has been shown that for InAs nanowire TFETs, strain can reduce the band gap and/or effective masses leading to improved I ON . We show that for the experimentally more favorable ultra-thin-body (UTB) InAs TFETs, certain types of strain improve I ON when channel length is long (30 nm). When channel length is short (15 nm), however, the improvement is marginal due to degraded SS as a result of increased ambipolar leakage. To mitigate this detrimental effect, we propose to apply the strain locally in an area around the source-channel tunnel junction. Since the band structures of the channel and the source remain unaffected, the ambipolar leakage does not increase and meantime the source Fermi degeneracy is removed. In this way we obtain a significant boost of SS and I ON . The simulations are performed by solving Poisson equation and open-boundary Schroedinger equation self-consistently within NEMO5 tool. The band structure of III–V materials is described by strained eight-band k·p Hamiltonian. Since tunneling current is very sensitive to band structures, we extract the k·p band parameters and deformation potentials from the corresponding atomistic tight binding calculations, whose parameters are fit to first-principles density functional theory (DFT) calculations with excellent match. We compare the confined band structures as well as I–V curves obtained from both methods and show that the accuracy of the k·p method is guaranteed.

It is critical to capture the effect due to strain and material interface for device level transistor modeling. We introduce a transferable $s{p}^{3}{d}^{5}{s}^{*}$ tight-binding model with nearest-neighbor interactions for arbitrarily strained group IV and III-V materials. The tight-binding model is parametrized with respect to hybrid functional (HSE06) calculations for varieties of strained systems. The tight-binding calculations of ultrasmall superlattices formed by group IV and group III-V materials show good agreement with the corresponding HSE06 calculations. The application of the tight-binding model to superlattices demonstrates that the transferable tight-binding model with nearest-neighbor interactions can be obtained for group IV and III-V materials.

2D transition metal dichalcogenides (TMDs) have attracted a lot of attention recently for energy-efficient tunneling-field-effect transistor (TFET) applications due to their excellent gate control resulting from their atomically thin dimensions. However, most TMDs have bandgaps (Eg) and effective masses (m*) outside the optimum range needed for high performance. It is shown here that the newly discovered 2D material, few-layer phosphorene, has several properties ideally suited for TFET applications: 1) direct Eg in the optimum range ~1.0–0.4 eV, 2) light transport m* (0.15 m0), 3) anisotropic m* which increases the density of states near the band edges and 4) a high mobility. These properties combine to provide phosphorene TFET outstanding ION ~ 1 mA/um, ON/OFF ratio ~ 106 for a 15 nm channel and 0.5 V supply voltage, thereby significantly outperforming the best TMD-TFETs and CMOS in many aspects such as ON/OFF current ratio and energy-delay products. Furthermore, phosphorene TFETS can scale down to 6 nm channel length and 0.2 V supply voltage within acceptable range in deterioration of the performance metrics. Full-band atomistic quantum transport simulations establish phosphorene TFETs as serious candidates for energy-efficient and scalable replacements of MOSFETs.

Future high-performance low-power integrated circuits require compact logic devices with both steep subthreshold swing (SS) and large drive current (I ON ). Tunneling field-effect transistors (TFETs) can meet the first requirement but their I ON is severely limited either by the low source-channel tunneling probability or by the high source-to-drain tunneling leakage. One of the methods that can be employed to boost I ON is doping engineering. In particular (1) lowering the drain doping density elongates the drain depletion region and thus suppresses the leakage leading to improved SS (and ION). This scheme, however, is not scalable as a long drain length is needed to reach charge neutrality [1]; (2) embedding an opposite N+ doping layer next to the P+ source, i.e., the source-pocket (SP) design [2], or inserting a δ doping layer [3], can enhance the electric field at the source-channel tunnel junction and improve ION. It can be shown that the improvement increases as the pocket doping density (Np) increases, but in practice doping density has an upper limit. In this paper, we show that, (1) embedding a P+ drain pocket can also improve the SS (and ION) and it is more scalable than lowering the drain doping; (2) by resorting to P+ channel, we can further improve I ON of the SP design without having to increase N p .

Future VLSI devices will require low CV dd 2/2 switching energy, large on-currents (I on ), and small off-currents (I off ). Low switching energy requires a low supply voltage V dd , yet reducing V dd typically increases /off and reduces the I on /I off ratio. Though tunnel FETs (TFETs) have steep subthreshold swings and can operate at a low V dd , yet their I on is limited by low tunneling probability. Even with a GaSb/InAs heterojunction (HJ), given a 2nm-thick-channel (001)-confined TFET, [100] transport, and assuming V dd =0.3V and I oFF =10−3A/m, the peak tunneling probability is on is only 24 A/m (fig. 1b) [1]. This low I on will result in large CV dd /I delay and slow logic operation. Techniques to increase /on include graded AlSb/AlGaSb source HJs [2,3] and tunneling resonant states [4]. We had previously shown that tunneling probability is increased using (11 0) confinement and channel heterojunctions [1], the latter increasing the junction built-in potential and junction field, hence reducing the tunneling distance. Here we propose a triple heterojunction TFET combining these techniques. The triple-HJ design further thins the tunnel barrier to 1.2 nm, and creates two closely aligned resonant states 57meV apart. The tunneling probability is very high, >50% over a 120meV range, and the ballistic I on is extremely high, 800A/m at 30nm Lg and 475 A/m at 15nm Lg, both with I off =10−3 A/m and V dd =0.3 V. Compared to a (001) GaSb/InAs TFET, the triple-HJ design increases the ballistic /on by 26:1 at 30nm L g and 19:1 at 15nm L g . The designs may, however, suffer from increased phonon-assisted tunneling.

We report the design and simulated performance of a GaAsSb/GaSb/InAs/InP n-type triple heterojunction (3-HJ) tunnel field-effect transistor (TFET). GaAsSb/GaSb source and InAs/InP channel HJs both increase the field imposed upon the tunnel junctions and introduce two resonant bound states. The tunneling probability, and hence the transistor on-current, are thereby greatly increased. The devices were simulated using a non-equilibrium Green function quantum transport approach and the k.p method within NEMO5. With 10−3 A/m (I OFF ) and a 0.3 V power supply V DD , we simulate 380 A/m ON-current (I ON ) at 30-nm gate length (L g ) and 275 A/m at 15-nm L g . Unlike a previously-reported high-current AlGaSb/GaSb/InAs/InGaAsSb 3-HJ design, the GaAsSb/GaSb/InAs/InP design employs channel materials to which high-quality, low-interface-state-density gate dielectrics have been demonstrated.

In this article we have investigated the electrical control of the exchange coupling (J) between donor-bound electrons in silicon with a detuning gate bias, crucial for the implementation of the two-qubit gate in a silicon quantum computer. We found that the asymmetric 2P–1P system provides a highly tunable exchange curve with mitigated J-oscillation, in which 5 orders of magnitude change in the exchange coupling can be achieved using a modest range of electric field (3 MV/m) for ~15-nm qubit separation. Compared with the barrier gate control of exchange in the Kane qubit, the detuning gate design reduces the gate density by a factor of ~2. By combining large-scale atomistic tight-binding method with a full configuration interaction technique, we captured the full two-electron spectrum of gated donors, providing state-of-the-art calculations of exchange energy in 1P–1P and 2P–1P qubits. Researchers in the United States and Australia propose an improved design for quantum computing in silicon. The team, led by researchers at Purdue University, found that a design consisting of two paired phosphorous donor atoms in silicon interacting with another nearby phosphorous atom provides a stable and easy-to-control way to realize highly integrated qubits in silicon. Although donor atoms in silicon promise a high density integration similar to the integrated electronic circuits in conventional silicon electronics, conventional qubits based on two interacting phosphorous atoms are vulnerable to fabrication errors. In contrast, the proposed system based on pairs of two plus one phosphorous atoms provides greater stability against fabrication errors, as well as an enhanced tunability of their interactions, supporting the practical realization of quantum computing architectures in silicon.

GaSb/InAs heterojunction tunnel field-effect transistors are strong candidates in building future low-power integrated circuits, as they could provide both steep subthreshold swing and large ON-state current ($I_{\rm{ON}}$). However, at short channel lengths they suffer from large tunneling leakage originating from the small band gap and small effective masses of the InAs channel. As proposed in this article, this problem can be significantly mitigated by reducing the channel thickness meanwhile retaining a thick source-channel tunnel junction, thus forming a design with a non-uniform body thickness. Because of the quantum confinement, the thin InAs channel offers a large band gap and large effective masses, reducing the ambipolar and source-to-drain tunneling leakage at OFF state. The thick GaSb/InAs tunnel junction, instead, offers a low tunnel barrier and small effective masses, allowing a large tunnel probability at ON state. In addition, the confinement induced band discontinuity enhances the tunnel electric field and creates a resonant state, further improving $I_{\rm{ON}}$. Atomistic quantum transport simulations show that ballistic $I_{\rm{ON}}=284$A/m is obtained at 15nm channel length, $I_{\rm{OFF}}=1\times10^{-3}$A/m, and $V_{\rm{DD}}=0.3$V. While with uniform body thickness, the largest achievable $I_{\rm{ON}}$ is only 25A/m. Simulations also indicate that this design is scalable to sub-10nm channel length., Comment: 4 pages, 8 figures

III-V tunnel field-effect transistors (TFETs) offer great potentials in future low-power electronics application due to their steep subthreshold slope and large “on” current. Their 3D quantum transport study using non-equilibrium Green’s function method is computationally very intensive, in particular when combined with multiband approaches such as the eight-band \( \varvec{k} \cdot \varvec{p} \) method. To reduce the numerical cost, an efficient reduced-order method is developed in this chapter and applied to study homojunction InAs and heterojunction GaSb–InAs nanowire TFETs. Device performances are obtained for various channel widths, channel lengths, crystal orientations, doping densities, source–pocket lengths, and strain conditions.

Thickness engineered tunneling field-effect transistors (TE-TFET) as a high performance ultra-scaled steep transistor is proposed. This device exploits a specific property of 2D materials: layer thickness dependent energy bandgap (Eg). Unlike the conventional hetero-junction TFETs, TE-TFET uses spatially varying layer thickness to form a hetero-junction. This offers advantages by avoiding the interface states and lattice mismatch problems. Furthermore, it boosts the ON-current to 1280$\mu A/\mu m$ for 15nm channel length. TE-TFET shows a channel length scalability down to 9nm with constant field scaling $E = V_{DD}/L_{ch}= 30V/nm$. Providing a higher ON current, phosphorene TE-TFET outperforms the homojunction phosphorene TFET and the TMD TFET in terms of extrinsic energy-delay product. In this work, the operation principles of TE-TFET and its performance sensitivity to the design parameters are investigated by the means of full-band atomistic quantum transport simulation., Comment: 6 figures

Tunneling field-effect transistors (TFETs) based on 2D materials are promising steep sub-threshold swing (SS) devices due to their tight gate control. There are two major methods to create the tunnel junction in these 2D TFETs: electrical and chemical doping. In this work, design guidelines for both electrically and chemically doped 2D TFETs are provided using full band atomistic quantum transport simulations in conjunction with analytic modeling. Moreover, several 2D TFETs' performance boosters such as strain, source doping, and equivalent oxide thickness (EOT) are studied. Later on, these performance boosters are analyzed within a novel figure-of-merit plot (i.e. constant ON-current plot)., Comment: 5 pages, 8 figures

When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field effect transistors (FETs) and tunnel field effect transistors (TFETs). Therefore, a survey of materials in a nanowire (NW) geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge and carbon nanotubes (CNTs). The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence band and, therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semi- analytic approach to calculating tunnel current is demonstrated which requires considerably less computation than a full-band numerical calculation.

The phonon spectra in zinc blende InAs, GaAs and their ternary alloy nanowires (NWs) are computed using an enhanced valence force field (EVFF) model. The physical and thermal properties of these nanowires such as sound velocity, elastic constants, specific heat (C v ), phonon density of states, phonon modes, and the ballistic thermal conductance are explored. The calculated transverse and longitudinal sound velocities in these NWs are ~25% and 20% smaller compared to the bulk velocities, respectively. The C v for NWs are about twice as large as the bulk values due to higher surface to volume ratio (SVR) and strong phonon confinement in the nanostructures. The temperature dependent C v for InAs and GaAs nanowires show a cross-over at 180°K due to higher phonon density in InAs nanowires at lower temperatures. With the phonon spectra and Landauer's model the ballistic thermal conductance is reported for these III---V NWs. The results in this work demonstrate the potential to engineer the thermal behavior of III---V NWs.

The correct estimation of the thermal properties of ultra-scaled CMOS and thermoelectric semiconductor devices demands for accurate phonon modeling in such structures. This work provides a detailed description of the modified valence force field (MVFF) method to obtain the phonon dispersion in zinc-blende semiconductors. The model is extended from bulk to nanowires after incorporating proper boundary conditions. The computational demands by the phonon calculation increase rapidly as the wire cross-section size increases. It is shown that nanowire phonon spectra differ considerably from the bulk dispersions. This manifests itself in the form of different physical and thermal properties in these wires. We believe that this model and approach will prove beneficial in the understanding of the lattice dynamics in the next generation ultra-scaled semiconductor devices.

Tunnel Field Effect Transistors (FETs) have the potential to achieve steep Subthreshold Swing (S.S.) below 60 mV/dec, but their S.S. could be limited by trap-assisted tunneling (TAT) due to interface traps. In this paper, the effect of trap energy and location on OFF-current (IOFF) of tunnel FETs is evaluated systematically using an atomistic trap level representation in a full quantum transport simulation. Trap energy levels close to band edges cause the highest leakage. Wave function penetration into the surrounding oxide increases the TAT current. To estimate the effects of multiple traps, we assume that the traps themselves do not interact with each other and as a whole do not modify the electrostatic potential dramatically. Within that model limitation, this numerical metrology study points to the critical importance of TAT in the IOFF in tunnel FETs. The model shows that for Dit higher than 1012/(cm2 eV) IOFF is critically increased with a degraded ION/IOFF ratio of the tunnel FET. In order to have ...

We present an atomistic tight-binding approach to calculating the electronic structure of semiconductor nanostructures. We start by deriving the strain distribution in the structure using the valence force field model. The strain field is incorporated into the tight-binding electronic structure calculation carried out in the frame of the effective bond orbital model and the fully atomistic Sp(3)d(5)s* approach. We apply the method to a vertically coupled self-assembled double-dot molecule. Using the effective mass approach, we establish the existence of electronic bonding and antibonding molecular orbitals for electrons and holes, whose probability density is shared equally between the dots. In the atomistic calculation we recover the molecular character of electron orbitals, but find that structural and atomistic details of the sample modify the hole orbitals, leading to a strongly asymmetric distribution of the probability density between the dots.

Atomistic disorder such as alloy disorder, surface roughness and inhomogeneous strain are known to influence electronic structure and charge transport. Scaling of device dimensions to the nanometer regime enhances the effects of disorder on device characteristics and the need for atomistic modeling arises. In this work SiGe alloy nanowires are studied from two different points of view: (1) Electronic structure where the bandstructure of a nanowire is obtained by projecting out small cell bands from a supercell eigenspectrum and (2) Transport where the transmission coefficient through the nanowire is computed using an atomistic wave function approach. The nearest neighbor sp3d5s* semi-empirical tight-binding model is employed for both electronic structure and transport. The connection between dispersions and transmission coefficients of SiGe random alloy nanowires of different sizes is highlighted. Localization is observed in thin disordered wires and a transition to bulk-like behavior is observed with increasing wire diameter.

The electronic behavior of metallic carbon nanotubes under the influence of externally applied electric fields is investigated using the Non-Equilibrium Green’s function method self consistently coupled with three-dimensional (3D) electrostatics. A nearest neighbor tight binding model based on a single pz orbital for constructing the device Hamiltonian is used. The 3D Poisson equation is solved using the Finite Element Method. Carbon nanotubes exhibit a very weak metallic behavior, and external electric fields can alter the electrostatic potential of the tubes significantly. A single vacancy defect in the channel of a metallic carbon nanotube can decrease its conductance by a factor of two. More than one vacancy can further decrease the conductance.

A bilayer graphene based electrostatically doped tunnel field-effect transistor (BED-TFET) is proposed in this work. Unlike graphene nanoribbon TFETs in which the edge states deteriorate the OFF-state performance, BED-TFETs operate based on different bandgaps induced by vertical electric fields in the source, channel, and drain regions without any chemical doping. The performance of the transistor is evaluated by self-consistent quantum transport simulations. This device has several advantages: 1) ultra-low power (VDD=0.1V), 2) high performance (ION/IOFF>104), 3) steep subthreshold swing (SS, 4 pages, 6 figures in 2016 Journal of the Electron Device Society

In addition to its high mobility, the possibility of opening sizable bandgaps has made bilayer graphene (BLG) a promising candidate for many electronic and optoelectronic applications. Yet, the achievable bandgap (300 meV) is not sufficient to make BLG a candidate for high performance transistors. Vertical strain in conjunction with the vertical field can help to achieve a larger band gap in BLG. In this paper, p z nearest-neighbor atomistic tight-binding model and Non-equilibrium Green's Function (NEGF) method are used to study the transport behavior of strained BLG transistors under electric field. A field tunable dynamic band gap (DBG) of up to 300 meV is found to exist in BLG with no strain in agreement with previous reports. By applying strain, one can increase the band gap of BLG beyond 300 meV. Finally, the DBG effect and vertical strain are shown to be able to enhance the ON/OFF ratio of a BLG field effect transistor (FET) to 1000.

Gate controlled tunnel junctions wherein the PN-junction like potential profile is made by two gates with opposite polarities are currently dominant in the fabrication of 2D material devices. Electrical doping methods are also preferred in tunnel field-effect transistors (TFETs) as chemical doping introduces states within the bandgap of the semiconductor and therefore degrades the OFF-state performance of TFETs. Moreover, low band gap 2D materials are preferable for high performance TFETs. Consequently, bilayer graphene (BLG) TFET is studied in this work. The critical design parameters in the performance of low bandgap electrically doped 2D transistors are investigated here. Through atomistic simulations, it is shown that the key element in the performance of electrically gated junctions is the thickness of the oxide even when the top and bottom gates have different biases. But still the equivalent oxide thickness (EOT) cannot be disregarded completely since it determines the value of the electric field dependent band gap in BLG.

In this work, the performance of an electrically doped monolayer WTe 2 tunnel field-effect (TFET) transistor is investigated by means of full band quantum transport simulations. The atomistic simulations predict an ON-current above 100 uA/um and a SS below 10 mV/dec for a channel length of 13nm and V DD of 0.5V. The impact of the design parameters such as oxide thickness and dielectric constant is discussed in detail.