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Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on recently manufactured commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) from three vendors. Abrupt changes of the electric field acceleration parameters ( $\gamma $ ) are observed at oxide electric fields ( $E_{ox}$ ) around 8.5 MV/cm to 9 MV/cm for all commercial MOSFETs. Gate leakage currents and threshold voltage shifts are also monitored under different oxide fields ( $E_{ox}= {\mathrm {8 MV/cm}}$ and 10 MV/cm). The results suggest the failure mode under high oxide electric field is modified by impact ionization or Anode Hole Injection (AHI) induced hole trapping. This observation agrees with previously published oxide reliability studies on SiC MOSFETs and suggests that constant-voltage TDDB measurements need to be carefully performed under low oxide fields to avoid lifetime overestimation caused by hole trapping. The extrapolated $t_{63\%}$ lifetimes (times to 63% failures) from TDDB measurements performed at $E_{ox} < {\mathrm {8.5 MV/cm}}$ are longer than 108 hours at 150°C for all vendors. The predicted lifetimes at $E_{ox}= {\mathrm {4 MV/cm}}$ demonstrate more than 105 times increases than the oxide lifetimes reported a decade ago, showing promising progress in SiC technology.

The commercialization of silicon carbide (SiC) power metal-oxide-semiconductor field-effect-transistors (MOSFETs) has expanded during the last decade. The gate oxide reliability is the primary issue for SiC power MOSFETs since it determines the device's operational lifetime. In this work, we investigate the gate leakage currents under different gate voltages on commercial 1.2 kV SiC power MOSFETs. The impact ionization and/or anode hole injection (AHI) triggered by high oxide electric fields results in hole trapping that enhances the gate leakage current and reduces device's threshold voltage. The electron injection and trapping due to Fowler-Nordheim (F - N) tunneling tend to reduce the gate leakage current and increases threshold voltage. Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are also conducted on the commercial MOSFETs. The results on gate leakage current suggest that the change of the field acceleration factor is due to enhanced gate current/hole trapping under high gate oxide fields. Therefore, it is suggested that TDDB measurements should be conducted under low gate voltages to avoid overestimation of lifetime under normal operating gate voltage.

We report a 900V 4H-SiC depletion mode (DM) VJFET with a specific on-resistance (RDSON,SP) of 1.46mOhm-cm2 at VGS=2.5V, IDS=10A. The RDSON,SP of the DM VJFET, designed for 600V-800V applications, is one of the lowest reported for a VJFET and is an order of magnitude lower compared to best Si Super Junction (SJ) MOSFETs reported in the literature. The turn-on (EON), turn-off (EOFF) and total (ETOTAL) switching energies of the DM-VJFET at VDD=400V, IDS=32.5A are 146uJ, 168uJ and 314uJ respectively. The switching figure of merit RDSON×QG is 3.8Ohm-nC; this is comparable to or better than the reported SJ-MOSFETs.

An all SiC 600V / 6 m hermetic half-bridge power module has been developed to operate at ambient temperatures of 200oC and with junction temperatures near 250oC. The modules use SiC trench JFET technology and can output over 100A at Tj=250oC. Double pulsed switching was performed up to temperatures of 150oC with a measured total switching energy of 0.73mJ

This is the first high-temperature static and dynamic characterization of a half-bridge power module using 1200 V, 45 mΩ depletion-mode vertical JFETs. With only 36 mm2 of JFET area, the peak pulsed current is measured to be nearly 500 A at room temperature (transistors not saturated), decreasing to 230 A at 250 °C (transistors saturated). Total switching losses are less than 3.2 mJ from 25 °C to 250 °C and show negligible dependence on junction temperature. The achievement of this level of performance with such a small SiC transistor area is important, since die area directly impacts achievable module footprint (system-level power density and cost), device capacitance (switching losses), and semiconductor cost.

Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.

This work presents the progress in developing an all SiC based power module for use in high frequency and high efficiency applications. Using parallel combinations of 1200V enhancement mode SiC VJFETs (36mm2) and Schottky diodes (23mm2), a total on-resistance of only 10mOhm (2.7m-cm2) was achieved at ID=100A in a commercially available standard module configured as a half-bridge circuit. Careful attention to module layout, gate driver design, and the addition of optimized snubbers resulted in excellent switching waveforms with low total switching losses of 1.25mJ when switching 100A at 150oC.

The high-temperature static and dynamic characteristics of the new 1200 V, 45 mΩ, 9 mm2 depletion-mode SiC vertical trench junction field-effect transistor (vtJFET) are compared with those of a 1200 V, 50 mΩ, 9 mm2 enhancement-mode SiC vtJFET. It is shown that both devices are fully capable of high-temperature operation and that each type has its own unique advantages. For applications operating in extreme high-temperature environments, the larger saturation current (~2.5x) and lower on-state resistance (~150 mΩ at 250 °C) of the depletion-mode SiC vtJFET provide very attractive performance at temperatures beyond silicon's fundamental limitations. In addition, operating the normally-on vtJFET at VGS less than 2 V reduces the gate drive's current requirements to a negligible level, which is an important design factor for high-temperature power modules that use multiple die in parallel.

Recently 63 m, 100 m, and 125 m 1200 V normally-off SiC VJFETs have become commercially available and 99% efficiency has been demonstrated in a single-phase solar inverter using these components [1]. They exhibit low specific on-resistance (3 m∙cm2), high saturation current density (1000 A∙cm-2), and low switching losses. For some applications, including 30 to 100 kW inverter modules and those requiring high surge current capability, larger die size is required. This paper reports the static and dynamic performance of 15 mm2 1200 V normally-off VJFETs with 25 m on-resistance and 120 A saturation current at 25 °C.

Normally-off Silicon Carbide (SiC) power Junction Field Effect Transistors (JFETs) were compared with competing power transistor technology at temperatures from 25 °C to 150 °C as limited by the packaging. Switching energies were measured from 1200 V, 125 mΩ and 50 mΩ (room temperature) rated SiC power JFETs and compared with 900 V silicon (Si) super-junction Metal Oxide Semiconductors (MOSFETs) and 1200 V Si Insulated Gate Bipolar Transistors (IGBTs). For both comparisons, measured performance for the SiC power JFET was advantageous at all temperatures when switching at 50 kHz, including a total switching energy (ESW) of 97 μJ for the SiC JFET, compared with 158 μJ for the Si super-junction MOSFET, and 550 μJ for the Si IGBT at 25 °C. At 150°C, the ESW was 138 μJ for the SiC power JFET, 413 μJ for the Si super-junction MOSFET, and 1020 μJ for the Si IGBT. Increasing the die size of the 1200 V, normally-off SiC JFET by 2.25 resulted in an measured increase in switching energy of 2.7 and 2.37 at 25 °C and 150 °C, respectively, a quasi-linear relationship. Higher power preview products of the SiC normally-off JFET technology were also examined including a 1200 V, 25 mΩ (room-temperature rating) power JFET characterized up to 250 °C, and a module capable of 1200 V, 120 A DC performance at 25 °C.

In this work, we report the most recent reliability results of the 1200-V SiC vertical-channel JFETs (VJFETs) under reverse and forward bias of the gate-source diode at temperatures up to 200 °C. The preliminary results indicate that continuous forward bias stress of the gate-source diode at 200 °C for 112 hours produced no observable change in the forward conduction or transient or reverse blocking characteristics of the vertical-channel JFET. This preliminary result suggests that devices based on this structure, such as the enhancement-mode (normally off) SiC VJFET, may not be effected by the recombination enhanced defect creation process and the associated increase in on-resistance, related to body-diode conduction in the SiC DMOSFET and the SiC lateral-channel depletion-mode JFET. Since the vertical-channel JFET has no body diode, no degradation is possible from the reverse conduction mode of operation.

Prototype 800 V, 47 A enhancement-mode SiC VJFETs have been developed for high temperature operation (250 °C). With an active area of 23 mm2 and target threshold voltage of +1.25 V, these devices exhibited a 28 m room temperature on-resistance and excellent blocking characteristics at elevated temperature. With improved device packaging, on-resistance and saturation current values of 15 m and 100 A, respectively, are achievable.

The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal parameters are reported, (3) gain performance and small signal parameters of the basic analog circuit block, Common Source (CS) amplifier, based on the variation of the load transistors threshold voltage (Vth) are studied and analyzed, and (4) frequency and transient response of the cascoded CS amplifier (CS-Cas) are reported.

In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time. The off-state characteristics were evaluated by high temperature reverse bias (HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours. A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for 1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for all tested devices.

SiC Lateral Trench JFET (LTJFET) technology is demonstrated as a promising candidate for use in high-temperature wireless telemetry systems. 4H-SiC LTJFETs were designed, fabricated and characterized for DC, and small-signal AC and RF performance at different case temperatures. Four-fold drain current reduction was observed at 460°C as compared to RT measurements. The measured threshold voltage shift was less than 2.3 mV/°C from 21°C to 460°C. A simple common source amplifier built using a fabricated device demonstrated stable small-signal AC performance after 100 hrs of operation at 450°C. Small-signal RF measurements were carried out on the packaged devices at different temperatures. GMax above 8 dB was measured over the L-band frequency range at RT. The average degradation of small-signal power gain measured at f=250 MHz did not exceed 0.0125 dB/ °C over the temperature ranging from 21°C to 365°C.

Epitaxial growth of 3-in, 4° off-axis 4H SiC with addition of HCl has been presented. Good surface morphology with a low defect density has been obtained, even for epi thickness of 38 µm. Comprehensive characterization techniques conducted on the epi material obtained in this process have independently confirmed the high purity and low density of crystalline imperfections. Low temperature PL displays clear free exciton I77 recombination while no L1 line is discernable. DLTS measurements have confirmed a low concentration of Z1/2 and EH6/7 below or in the range of 1011 cm-3. Time resolved PL at room temperature performed on a 38 µm thick epi wafer gives long carrier lifetime in the range of 1.5 to above 5 µsec. PiN diodes with diode area up to 25 mm2 have demonstrated blocking voltages above 900V, with a max electric field of above 2.5 MV/cm.

An integrated p-i-n diode for use in SiGe BiCMOS technology applications has been developed. The device may be used into the MMW frequency range

We present the advances in Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT) and BiCMOS technology capabilities to address the emerging millimetre-wave (mmWave) applications. SiGe HBTs with fMAX performance reaching 350 GHz that are integrated with advanced CMOS and high-frequency passives is envisioned to allow better integration capability for mmWave applications. This capability of SiGe HBT BiCMOS technology is discussed relative to an InP HBT technology. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Proton irradiation is used to probe the physics of 4H-silicon carbide (SiC) Schottky barrier diodes (SBDs) and negative channel metal oxide semiconductor (nMOS) capacitors for the first time. Both 4H-SiC SBD diodes and SiC MOS structures show excellent radiation tolerance under high-energy, high-dose proton exposure. Unlike for SiC JBS diodes, which show a strong increase in series resistance after proton irradiation, these SiC SBDs show very little forward bias I--V degradation after exposure to 63.3 MeV protons up to a fluence of 5/spl times/10/sup 13/ p/cm/sup 2/. An improvement in reverse leakage current after irradiation is also observed, which could be due to a proton annealing effect. The small but observable increase in blocking voltage for these SiC SBDs is attributed to a negative surface charge increase, consistent with earlier gamma results. The resultant Q/sub eff/ change of 4H-SiC nMOS capacitors under proton irradiation was used to quantify the radiation induced changes to the blocking voltage in the SBD diodes in MEDICI simulations, and showed a good agreement with the experimental data. Characterization of these capacitors also suggests that 4H-SiC MOS structures are radiation hard.

The effects of proton irradiation on the static ( dc) and dynamic (switching) performance of high-voltage 4H-SiC Junction Barrier Schottky (JBS) diodes are investigated for the first time. In contrast to that observed on a high-voltage Si p - i - n diode control device, these SiC JBS devices show an increase (degradation) in series resistance (R/sub S/), a decrease (improvement) of reverse leakage current, and increase (improvement) in blocking voltage after high-fluence proton exposure. Measured breakdown voltages of post-irradiated SiC diodes increase on average by about 200 V after irradiation. Dynamic reverse recovery transient measurements show good agreement between the various dc observations regarding differences between high-power SiC and Si diodes, and show that SiC JBS diodes are very effective in minimizing switching losses for high-power applications, even under high levels of radiation exposure.

The short-circuit reliability of power switches plays very important part in many applications, where a 10μs short-circuit duration at 400V is usually required for 650V switches. Although emerging high voltage AlGaN/GaN HEMT technologies have shown switching advantages, the short-circuit performance has not been thoroughly investigated. In this work, we present an experimental study and numerical simulation analysis of 650V AlGaN/GaN HEMTs short-circuit safe-operating-area (SCSOA), and provide a theory for the reduction in ruggedness at high voltage short circuit conditions.

The effects of radiation on high-voltage 4H-SiC Schottky diodes for use in extreme environment power supplies are investigated for the first time. Diodes were fabricated with a wide range of barrier heights (1.06-1.60 eV) and were evaluated after being exposed to a /sup 60/Co gamma radiation source. DC current-voltage characteristics were measured after several radiation doses, with no observable degradation in the diode forward or reverse characteristics up to a total dose of 4 Mrad(Si). Measured breakdown voltages of post-irradiated diodes increase approximately 200 V compared to the virgin devices and are attributed to increased negative interface charge, as determined by MOS capacitor measurements and correlated with numerical breakdown simulations.

The design of SiC planar and non-planar junction termination extension (JTE) structures are investigated through calibrated quasi-3D numerical simulation. JTE techniques are optimized with respect to breakdown voltage, area consumption, surface fields, and interface charge. Simulated JTE charge profiles predict near-ideal breakdown values with surface fields less than 60% of their bulk values, and show that the critical implant activation percentage can vary as much as 40% with only 10% reduction in breakdown voltage for lightly doped blocking layers. These results are extended to unique multiple-zone JTE and mesa-JTE structures applicable to a wide range of planar and non-planar SiC power devices.

An optimized multiple floating guard ring structure is investigated for the first time as an edge termination method for high voltage 4H-SiC planar devices. Simulations were performed to investigate SiC guard ring termination, and determine the optimum guard ring spacing for planar diodes with up to four floating rings. Simulated optimized designs predicted breakdown values from 40% of the ideal breakdown with a single ring, to 84% of the ideal value for diodes with four rings. Implanted 4H-SiC pn diodes with optimized guard ring designs were fabricated and results correlated to simulation. Experimental breakdown values of 1.2–1.3 kV for guard ring structure with four rings were in good agreement with simulated results.

Silicon carbide (SiC) is an emerging semiconductor material which has been widely predicted to be superior to both Si and GaAs in the area of power electronic switching devices. This paper presents an overview of SiC power devices and concludes that the MOS turn-off thyristor (MTO™), comprising of a hybrid connection of SiC gate turn-off thyristor (GTO) and MOSFET, is one of the most promising near term SiC switching device given its high power potential, ease of turn-off, 500°C operation and resulting reduction in cooling requirements. The use of a SiC and an anti-parallel diode are primary active components which can then be used to construct an inverter module for high-temperature, high-power direct current (d.c.) motor control.

1200V SiC vertical trench JFETs have been evaluated for their reverse conduction properties. Absent of a traditional body diode, the SiC trench JFET is shown to be able to operate effectively in reverse mode when used with or without an antiparallel diode in applications requiring reverse commutation. Device characteristics and experimental results are given for both traditional half-bridge and cascode topologies.

The unique wide bandgap properties of SiC allow the creation of high performance normally-off vertical JFET power device. Due to the vertical nature of the device, it can easily be designed with blocking capability exceeding 2kV with R DS(ON), sp > 3mΩ-cm2, resulting in the lowest specific on-resistance for enhancement mode SiC devices with V BR DS(ON), sp yields a small die size that translates into switching losses that are 5–10X smaller than similarly rated Si IGBTs. When used as an IGBT replacement, a significant reduction in losses can be achieved, greatly increasing the overall system efficiency of solar inverters and other renewable power systems.

A novel SiC junction field effect transistor (JFET) model is proposed that uses a unified description of linear and saturated conduction modes. Advantages of the proposed model are improved robustness and convergence, inclusion of fielddependent mobility effects, and more physical description of the current saturation phenomenon. The model is validated against a normally-off JFET sample over a wide temperature range. Finite element simulation are used to demonstrate the physicsbased nature of the proposed model.

A practical parameter extraction procedure for power junction field effect transistor (JFET) is presented. The carrier mobility and carrier concentrations are very important parameters, strongly affecting the current capability and dynamic characteristics of the device for a given design. When modeling JFETs, values of these parameters usually are based on assumptions and given by a vendor in a range. As a result, model accuracy is compromised. In this paper, a step-by-step parameter extraction procedure is described that includes extraction of the mobility and the carrier concentration in the channel and drift regions based on knowledge of the device geometrical parameters. For the first time, carrier mobility in channel and drift regions of power JFET are extracted individually. It is found that channel and drift region mobilities can be very different for a given device, since they are strongly fabrication-process dependent. The developed procedure includes extraction of parameters for proposed empirical temperature dependencies of mobilities in the channel and drift regions. A simple static I-V characterization and C-V measurements are the only measurements required for the parameter extraction.

Twenty amp normally-off enhancement mode 4H-SiC VJFETs are demonstrated with 1.9kV avalanche breakdown voltage and a specific on-resistance of 2.8mΩ-cm2. The VJFETs shown near ideal subthreshold characteristics and maintain enhancement mode functionality to temperatures exceeding 175°C due to the optimized channel design with low DIBL characteristics. The low specific on-resistance enables the VJFET to have low intrinsic capacitances that result in low total switching times of less than 150ns at 15A at a Tj=175°C, and low total switching energies of 97µJ when switching 12A at Tj=25°C. Short circuit performance was also investigated with the VJFET exhibiting a rugged short circuit withstand capability in excess of 700µs at a V DS =600V.

In this work a physical model for a SiC Junction Field Effect Transistor (JFET) is presented. The novel feature of the model is that the mobility dependence on both temperature and electric field is taken into account. This is particularly important for high-current power devices, where the maximum conduction current is limited by drift velocity saturation in the channel. The model equations are described in detail, emphasizing the differences introduced by the field-dependent mobility model. The model is then implemented in Pspice. Both static and dynamic simulation results are given. The results are validated with experimental results under static conditions and under resistive switching conditions.

The conventional wisdom that the SiC JFET is a normally on device has recently been superseded by the first practical normally off SiC JFET. The new true enhancement mode, three-terminal, pure-SiC design provides designers with a normally off solution that retains all the benefits of the normally on SiC JFET. With a simple change in the series gate impedance, the EM SiC JFET can be used with common IC drivers and is a drop-in replacement for current power devices in most applications. Device characteristics are superior to MOSFETs and IGBTs and offer the possibility of efficiency improvements from reduced conduction and switching losses. The work presented in this paper demonstrates the drop-in replacement of an IGBT with a normally off SiC JFET in a PFC demo circuit. System efficiency using each device was observed and compared. An improvement was noted with the JFET as expected.

This paper reports on the development of a normally- off 4H-SiC VJFET power switch technology suitable for drop in replacement in switching-mode power supplies (SMPS). The fabricated devices exhibited a low specific on-resistance (Ron-sp) measured at VDS=1 V and VGs=2-5 V. The transistors designed for 800 V applications had RON-SP < 2.9 mOmegaldrcm2 and RON-SP < 6.6 mOmegaldrcm2 at 25degC and 200degC, respectively. The devices designed for 1200 V application had RON-SP < 4.3 mOmegaldrcm2 at 25degC and RON-SP < 12.8 mOmegaldrcm2 at 200degC. The total delay time of 73 ns was measured on a 1200 V device when switching from 600 V to 4.9 A with the gate bias ranging from 0 V to 2.75 V. The highest measured off-state drain voltage blocked by a 1200 V device at VGS=0 V exceeded 1800 V with the total drain leakage of 1 mA.

This paper presents experimental characterization and modeling of intermodulation linearity in a 200 GHz SiGe HBT technology. The impact of biasing current, voltage, and breakdown voltage is examined. IP3 is simulated using the VBIC, HICUM and Mextram model to evaluate the linearity capability of these models. The impact of avalanche and self-heating on IIP3 are examined. A weak avalanche is shown to have significant impact on IIP3.

The input non-quasi-static (NQS) effects in SiGe HBTs are analyzed using Taylor series expansions of intrinsic Y-parameter expressions. The input NQS effect is shown to strongly affect extraction of the intrinsic base resistance and hence NF/sub min/ modeling.

This work presents experimental characterization of intermodulation linearity of CMOS transistors from a 0.13 /spl mu/m process. The IIP3 in the saturation region is shown to increase with V/sub ds/, even though g/sub m/ saturates. The IIP3 in strong inversion is found to be higher than the IIP3 at the well known linearity sweet spot near the threshold voltage. Longer channel transistors and thick oxide transistors are found to have linearity advantages. The results provide useful guidelines for optimal biasing and device selection in RFIC design.

This paper investigates the methodologies for generating and integrating scalable bipolar models in the modern design environment. Additionally, fundamental bipolar parameter scaling is reviewed and demonstrated with a scalable SiGe HBT model valid for models such as VBIC, MEXTRAM, and HiCUM.

A new direct extraction method, using a set of Z-parameter based ratios, is developed for SiGe HBTs. The input non-quasi-static effect is included to enable more accurate noise modeling. Excellent fitting with experimental data is obtained up to 60 GHz over a wide range of biasing currents.

This work presents experimental extraction of intrinsic base and collector current noise of SiGe HBTs as well as their correlation. Using the extraction results, several widely used noise models are evaluated, including the conventional SPICE model, the Van Vliet model, and the transport noise model. Connections and differences between various models are discussed.

The behavior of 4H-SiC power diodes under radiation exposure and related issues are investigated and reviewed in this chapter. The fundamentals of power diodes and radiation are introduced. The DC performance of unterminated SiC junction barrier Schottky (JBS) diodes and Schottky barrier diodes (SBDs) under gamma radiation shows the significant tolerance of SiC diodes to gamma radiation exposure. The breakdown voltage increase after gamma radiation is ascribed to changes in the SiC/SiO2 interface. Investigation of SiC MOS capacitors confirmed this effect. NO passivation is shown to effectively improve the SiC/SiO2 interface and the interface charge density even after gamma irradiation. Both the DC and the AC performance of SiC JBS/SBDs under high-dose proton irradiation were also investigated. SiC JBS devices show a degradation of series resistance (R S) and improvements of reverse leakage current and blocking voltage after high-fluence proton exposure. The AC performance after proton irradiation shows that SiC JBS diodes are very effective in minimizing switching losses for high-power applications, even under high levels of radiation exposure, indicating superior radiation hardness for SiC switching diodes. We conclude that SiC power devices hold much promise for power-switching systems operating in a radiation environment.

Electrostatic discharge robustness of an epitaxial-base pseudomorphic Silicon Germanium Heterojunction Bipolar Transistor (HBT) device with Carbon incorporation is shown for the first time. Experimental results show that incorporation of Carbon in the base of a SiGe HBT device improves power-to-failure variation by improved control of the base width and base width distribution.

High frequency performance at low current density and low wafer cost is essential for low power wireless BiCMOS technologies. We have developed a low-complexity, ASIC-compatible, 0.18 /spl mu/m SiGe BiCMOS technology for wireless applications that offers 3 different breakdown voltage NPNs; with the high performance device achieving F/sub t//F/sub max/ of 60/85 GHz with a 3.0 V BV/sub CEO/. In addition, a full suite of high performance passive devices complement the state-of-the-art SiGe wireless HBTs.