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In this letter, we report the realization of sub-10-nm diameter vertical nanowire (VNW) p-type tunnel FETs (TFETs). Using a broken-band GaSb/InAsSb heterostructure design and a top-down fabrication approach, we demonstrate a 9-nm diameter VNW TFET with excellent on-state characteristics featuring a peak transconductance of 90 $\mu \text{S}/\mu \text{m}$ at $V_{{\text {ds}}} = -0.3$ V. The same device exhibits a minimum linear subthreshold swing of 225 mV/dec at $V_{\text {ds}} = -0.05$ V. Our p-type GaSb/InAsSb TFETs exhibit clear negative differential resistance at room temperature, with a peak-to-valley current ratio over 3. The excellent device performance of these devices bodes well for the viability of GaSb-based complementary TFETs in future ultra-scaled logic technologies. [ABSTRACT FROM AUTHOR]

In the presence of prominent gate oxide trapping, the conventional technique for channel mobility extraction in MOSFETs based on I – V/C – V measurements becomes inadequate. This is the consequence of two different effects associated with oxide traps: gate voltage stretch-out and electron trapping and detrapping in the oxide at the megahertz (MHz)-range frequencies that are commonly utilized. In thin-channel planar InGaAs MOSFETs, both effects are observed and found to result in a severe overestimation of mobile charge and subsequently an underestimation of mobility using I – V/C – V. To address this issue, we demonstrate a new mobility extraction technique (RF- ID) based on concurrent I – V and S-parameter measurement in the gigahertz (GHz) regime that is largely immune to oxide trapping. Excellent agreement with Hall measurements as well as with theoretical predictions from Poisson–Schrodinger simulations gives confidence to the new technique. Importantly, the new technique is not limited to InGaAs planar MOSFETs, but applies to any device geometry and any material system. Promising mobility ~1100 cm2/V⋅s is found in quantum-well planar InGaAs MOSFETs with a 4-nm-thick channel. [ABSTRACT FROM AUTHOR]

GaN electronics constitutes a revolutionary technology with power handling capabilities that amply exceed those of Si and other semiconductors in many applications. RF, microwave, and millimeter-wave GaN-based power amplifiers are now deployed in commercial communications, radar, and sensing systems. GaN power transistors for electrical power management are also starting to reach the marketplace. From the dawn of this technology, inadequate transistor stability and reliability have represented stumbling blocks preventing widespread commercial use of GaN electronics. Intense research has been devoted to addressing these issues, and great progress has taken place recently. This article reviews some of the most interesting and significant stability and reliability issues that have plagued GaN power field-effect transistors for RF and power management applications. [ABSTRACT FROM AUTHOR]

InGaAs FinFETs are challenged by relatively high leakage current in the OFF state. This originates from band-to-band tunneling (BTBT) at the drain end of the channel that is amplified by a parasitic bipolar effect (PBE) as a result of its floating body. In this paper, we present a simple model of the PBE in InGaAs FinFETs, which captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain on the parasitic bipolar junction transistor (BJT). The model enables the extraction of the carrier diffusion length which exhibits the predicted fin width dependence. For short gate length transistors, source recombination is shown to dominate and the parasitic bipolar gain scales with the inverse of the gate length. [ABSTRACT FROM AUTHOR]

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain. [ABSTRACT FROM AUTHOR]

A p-type Diamond:H/WO3 metal–oxide–semiconductor field-effect transistor (MOSFET) based on surface transfer doping is demonstrated. Using a low-temperature ALD-grown HfO2 as gate insulator, the Diamond:H/WO3 MOSFETs show excellent output characteristics, gate-controllable 2-D hole gas, and low gate leakage current. Long-channel FETs exhibit improved subthreshold behavior but reduced transconductance with respect to short-channel devices. An observed WO3-thickness-dependent threshold voltage is consistent with enhanced surface transfer doping as the WO3 layer is thinned down. Low-temperature measurements suggest a significantly lower mobility than expected in this material system. This illustrates the challenge of maintaining high TMO quality during device fabrication. [ABSTRACT FROM AUTHOR]

We present a detailed study of the off-state leakage current in scaled self-aligned InGaAs FinFETs. In long-channel devices, band-to-band tunneling at the drain-end of the channel is shown to be the root cause of excessive off-state current. This conclusion emerges from its characteristic electric field and temperature behavior and the absence of gate length and fin width dependencies. In short-channel devices, off-state current is significantly larger and it increases as the gate length shortens or the fin widens. We attribute this behavior to current multiplication through the gain of a floating-base parasitic bipolar transistor that is present inside the MOSFET. We extract the bipolar current gain which in short-channel devices is found to increase as the gate length shortens and decrease as the fin width narrows. In long channel devices, the current gain drops exponentially due to base recombination. This has allowed us to extract the diffusion length of electrons in the body of the transistor. [ABSTRACT FROM AUTHOR]

The single-event-transient response of InGaAs FinFETs with different fin widths is examined using pulsed-laser and heavy-ion irradiation. Devices with wider fins collect more charge in both environments. Quantum-well structures confine charge collection in the channel, and determine the sensitive volume. Simulations show that the charge density produced by irradiation is similar for devices with different fin widths, but more charge is collected by wider fin devices due to the larger channel volume. Charge accumulated in the buffer and substrate layers modulates the body potential, altering the degree of back-gate control, leading to additional effects associated with charge accumulation in wider fin devices. Optical simulations for a model system suggest that optical phenomena in the fins should be considered for laser testing. These include optical interference, plasmonic enhancement at the metal–dielectric interfaces, and enhanced electron–hole pair recombination due to multiple reflections in multigate devices with nanoscale dimensions. [ABSTRACT FROM PUBLISHER]

The electrical degradation of InAlN/GaN high-electron-mobility transistors for millimeter-wave applications has been examined under simultaneous high VDS,stress and high IDstress electrical stress. Besides a drain current decrease and a positive threshold voltage shift, the creation of an anomalous source-side gate leakage path has been identified. We attribute this to high electric-field induced trap generation in the AlN layer directly under the gate edge on the source side. The resulting increase in gate leakage further exacerbates the degradation of the gate diode. In addition, we postulate that high-power stress leads to significant device self-heating that causes gate sinking and leads to a permanent positive threshold voltage shift and drain current degradation. [ABSTRACT FROM AUTHOR]

We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of time-to-first breakdown, hard breakdown, and the gate current evolution during PBD all share similar, shallow activation energies that suggest a common underlying mechanism. However, the gate current noise during PBD seems to be independent of temperature and is likely due to a tunneling process. Understanding of temperature-dependent breakdown is essential to developing accurate device lifetime estimates. [ABSTRACT FROM PUBLISHER]

Physics-based transistor models are important for technology projections and circuit simulations. To date, there has been little discussion on the incorporation of ballistic effects in transistor models. Recent experimental studies have revealed the significance of ballistic transport in the electrical characteristics of nanometer-scale InGaAs MOSFETs with ultra-low external resistance. Without proper accounting for the ballistic resistance and its gate voltage dependence, the access resistance to the intrinsic device cannot be accurately determined, and any physics-based transistor modeling is bound to fail. In this letter, we show that the MIT Virtual Source model, which natively captures ballistic transport physics, correctly incorporates the impact of ballistic resistance. As a result, it accurately models the electrical characteristics of self-aligned nanoscale InGaAs MOSFETs, an excellent model system for near-ballistic transistors, over a broad operational range. We also show that the success of the model development effort crucially relies on the correct extraction of the external source and drain resistance, R{\text {sd}} , from experimental measurements. [ABSTRACT FROM AUTHOR]

We present a comprehensive study of bias temperature instability (BTI) in GaN MOSFETs under moderate positive and negative gate bias stress. We investigate the evolution of threshold voltage ( V_T) , maximum transconductance ( gm,max) , and subthreshold swing (S). Our results show a universal continuous, symmetrical, and reversible V_T shift and gm, max change as gate stress voltage ( \text V{{\text {GS,\text {stress}}}}) increases from −5 to 5V at room temperature. The time evolution of V_T is well described by a power law model. The voltage dependence, time dependence, and temperature dependence of our results suggest that for moderate gate bias stress, positive BTI and negative BTI are due to a single reversible mechanism. This is electron trapping/detrapping in preexisting oxide traps that form a defect band very close to the GaN/oxide interface and extend in energy beyond the conduction band edge of GaN and below the Fermi level at the channel surface at 0 V. [ABSTRACT FROM PUBLISHER]

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work. [ABSTRACT FROM PUBLISHER]

This letter introduces a novel alcohol-based digital etch technique for III–V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at V \mathrm { {DS}}= 50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides. [ABSTRACT FROM AUTHOR]

The effects of total-ionizing-dose irradiation are investigated in HfO2/InGaAs quantum-well MOSFETs. Radiation-induced hole trapping is higher for irradiation under positive gate bias than under negative gate bias. Electrical stress-induced electron trapping compensates radiation-induced hole trapping during positive gate-bias irradiation. Stress-induced hole trapping adds to the effects of radiation-induced hole trapping under negative gate bias. Radiation-induced charge trapping increases with the channel length. [ABSTRACT FROM PUBLISHER]

The degradation of InAlN/GaN high-electron-mobility transistors (HEMTs) for millimeter-wave applications has been examined under on conditions. Two dominant permanent degradation mechanisms have been identified as well as two trapping mechanisms which affect the device characteristics in different ways. Under high-voltage, low-current stress conditions, we have observed permanent enhancement in the maximum drain current ID\mathrm {{max}} that arises from a negative shift in threshold voltage VT . We attribute this mechanism to depassivation of hydrogenated defects. Under the same stress conditions, there is prominent and reversible hot-electron trapping on the drain side of the device that brings ID\mathrm {{max}} down and increases the drain resistance. Under low-voltage high-current stress conditions, there is a visible permanent reduction in ID\mathrm {{max}} and a positive shift in VT . This is also the signature of-high temperature stress under unbiased conditions and is attributed to gate sinking. [ABSTRACT FROM AUTHOR]

We study the scaling properties of self-aligned InGaAs FinFETs with sub-10-nm fin widths fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5, and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices feature self-aligned metal contacts that are 20–30 nm away from the edge of the gate. FinFETs with Lg=30 nm, Wf=7 nm, and channel height of 40 nm exhibit a transconductance of 900~\mu \textS/\mu \textm at V\mathrm { {DS}}=0.5 V. When normalized to Wf , this is a record value among all III–V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls. [ABSTRACT FROM PUBLISHER]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

Recent advances in the fabrication technology have yielded nanometer-scale InGaAs quantum-well (QW) MOSFETs with extremely low and reproducible external contact and access region resistances. This allows, for the first time, a detailed analysis of the role of ballistic transport in the operation of these devices. This paper presents a systematic analysis of external resistance, ballistic resistance, and channel mobility in InGaAs QW-MOSFETs under near-equilibrium conditions, i.e., under very low drain-source bias. This is an important regime for device characterization. Devices with a wide range of channel lengths, from 70 to 650 nm, are investigated. Our analysis includes the consideration of the impact of carrier degeneracy in the QW channel. We show that unless the ballistic behavior in the intrinsic channel is accounted for, the standard extraction technique for external resistance grossly exaggerates its value as it incorporates the so-called ballistic resistance. By separating out the ballistic resistance, the external resistance in our devices is shown to be extremely low, $74~\Omega $ - \mu \text{m} , including both source and drain sides. This is thanks to our contact-first self-aligned Mo-contact technology. Furthermore, taking the advantage of the wide range of ballisticity of the devices studied in this paper, we demonstrate a methodology to self-consistently extract scattering-dependent effective mobility, mean-free-path length, and ballistic mobility. [ABSTRACT FROM AUTHOR]

This letter presents a self-aligned InGaAs quantum-well MOSFET with a transconductance, gm,\max , of 3.45 mS/ \mu \textm at V\mathrm {ds}= 0.5 V. This is a record value among III-V FETs of any kind, including MOSFETs and HEMTs, and represents an improvement of over 10% with respect to the previous record on planar devices. This result was achieved by redesigning the access regions that link the intrinsic device to the source and drain contacts so as to increase their electron concentration. This mitigates the nonlinear increase of the access resistance at high current. This is often referred to as source starvation and leads to the loss of transconductance under strong on conditions. [ABSTRACT FROM PUBLISHER]

Using a novel gate-last process scheme that affords precise channel thickness control, we have fabricated self-aligned InGaAs quantum-well (QW) MOSFETs. Devices with a channel thickness between 3 and 12 nm, and a gate length between 40 nm and 5 \mu \textm are fabricated on a heterostructure that includes a composite InGaAs/InAs QW and an InP barrier. It is observed that channel thickness has a strong impact on the device characteristics. In general, a thick channel is beneficial to ON-state figures of merit, including transconductance and effective carrier mobility. However, a thin channel is beneficial to OFF-state metrics, such as subthreshold swing and drain-induced barrier lowering (DIBL). The InAs composition and effective mass that electrons experience in the channel emerges as a factor that significantly affects channel mobility and presumably the transport characteristics of these devices. The subthreshold swing and DIBL are found to follow a classic scaling behavior. This suggests that the InGaAs QW MOSFETs are at the limit of scaling around Lg=50 nm. [ABSTRACT FROM AUTHOR]

A number of recent reports have noted excess OFF-state leakage current ( I\mathrm{{\scriptscriptstyle OFF}}) in scaled InGaAs quantum-well nMOSFETs. There is growing evidence that a combination of band-to-band tunneling (BTBT) and a floating-body bipolar gain effect is responsible for this. Unless this issue is effectively addressed, the scaling potential of this transistor structure will be compromised. This paper presents a detailed study of the physics of I\mathrm{{\scriptscriptstyle OFF}} and explores I\mathrm{{\scriptscriptstyle OFF}} reduction strategies through 2-D device simulations that have been calibrated with experiments. In essence, under OFF conditions at even moderate values of V\textrm {ds} , a BTBT process at the drain-end generates holes in the channel and thereby reduces the source–channel potential barrier. This results in injection of electrons into the channel that contribute to enhanced I\mathrm{{\scriptscriptstyle OFF}} while the holes are injected into the source where they recombine. In a nanoscale device, the bipolar effect that is at play here can have a very large current gain and amplify many fold even a small BTBT current. A study of approaches to mitigating this effect is analyzed here. It is concluded that the most effective strategy is to minimize the bipolar current gain rather than BTBT in scaled transistors. [ABSTRACT FROM AUTHOR]

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms. [ABSTRACT FROM PUBLISHER]

The origin of structural and electrical degradation in AlGaN/GaN high-electron mobility transistors (HEMTs) under OFF-state stress was systematically studied. Hydroxyl groups (OH^-) from the environment and/or adsorbed water on the III-N surface, were found to play an important role in the formation of surface pits during OFF-state electrical stress. The mechanism of this water-related structural degradation is explained by an electrochemical cell formed at the gate edge where gate metal, the III-N surface, and the passivation layer meet. The relationship between structural and electrical degradation in AlGaN/GaN HEMTs under OFF-state stress is discussed. Specifically, the permanent decrease in the drain current is directly linked with the formation of the surface pits, while the permanent increase in the gate current is found to be uncorrelated with the structural degradation. [ABSTRACT FROM PUBLISHER]

A p-type MOSFET based on a heterointerface of hydrogenated-diamond transfer doped with MoO3 (Diamond:H/MoO3) is demonstrated for the first time. This is an important new heterostructure system due to its potentially improved temperature stability as compared with the better established Diamond:H/H2O system. MOSFETs using HfO2 as gate insulator show excellent output characteristics and gate control over the 2-D hole gas at the Diamond:H/MoO3 interface. In 3.5- $\mu $ m gate length devices, we obtain a maximum drain-current ON-OFF ratio of three orders of magnitude and a maximum transconductance of 2.5 $\mu $ S/ $\mu $ m. [ABSTRACT FROM AUTHOR]

This letter introduces a novel inductively coupled plasma-reactive ion etching (ICP-RIE) technique based on a BCl3/SiCl4/Ar chemistry for fabricating sub-20 nm diameter InGaAs nanowires with smooth, vertical sidewall and high aspect ratio (>10) . To mitigate dry-etch damage, RIE is followed by a digital etch method comprised of multiple cycles of self-limiting low power O2 plasma oxidation and diluted H2SO4 rinse. Using these technologies, we demonstrate vertical InGaAs gate-all-around nanowire MOSFETs with 30 nm diameter. Digital etch improves both the subthreshold swing and peak transconductance, indicating enhanced sidewall interfacial quality. The combination of RIE and digital etch techniques proposed here is promising for future 3-D III-V MOSFETs. [ABSTRACT FROM AUTHOR]

We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of low-power O2 plasma oxidation, followed by diluted H2SO4 rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is \sim0.9~nm/cycle. We illustrate the new process by fabricating Lg=60\-nm self-aligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO2 for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/\mum(Vds=0.5~\rm V), subthreshold swing of 89 mV/decade, and 102 mV/decade at Vds=0.05 and 0.5 V, respectively, and on current of 326 \muA/\mum at IOFF=100~nA/\mum and Vdd=0.5~\rm V. [ABSTRACT FROM AUTHOR]

We demonstrate Lg = \100\ \nm high-speed enhancement-mode (E-mode) InAs quantum-well MOSFETs with outstanding high-frequency and logic performance. These devices feature a 3-nm \Al2\O3 layer grown by atomic layer deposition. The MOSFETs with Lg = \100\ \nm exhibit VT = \0.2\ \V (E-mode), RON = \370\ \Omega\cdot\mu\m, S = \105\ \mV/dec, DIBL = \100\ \mV/V, and g{m\_\max} = \1720\ \mu\S/\mu\m at VDS = \0.5 \ \V. They also have an excellent high-frequency response of fT = \248\ \GHz and f\max = \302\ \GHz at VDS = \0.5\ \V , the highest fT and f \max in III–V MOSFETs ever reported. [ABSTRACT FROM AUTHOR]