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Condition monitoring of insulated gate bipolar transistor (IGBT) modules is an effective way to improve the transient performance and reliability of modular multilevel converters (MMC). This article proposes a novel bond wire failure monitoring method for the multichip IGBT modules in the MMC half-bridge submodule (SM) structure. The collector voltage undershoot VCA(np) of the complementary IGBT switch is measured during the turn-off switching transition of the controlled IGBT switch. VCA(np) is sensitive to the induced voltage over the stray inductance of the IGBT bond wires and provides high sensitivity as a health indicator. The non-intrusive measurement technique is demonstrated using a half-bridge circuit during the turn-off transition of the controlled IGBT, while its complementary switch (i.e., the device under test) is in the off state. Theoretical analysis and experimental results show that the parametric drift due to wire bonding failures can be effectively monitored with high specific relative sensitivity and granularity. To ensure its effectiveness in practical applications, the influence of load current, SM capacitor voltage, and junction temperature is discussed. In addition, a readout circuit is designed featuring the integrated desaturation detection and voltage peak detection, which offers both the short-term overcurrent fault protection and long-term bond wire aging monitoring functions. [ABSTRACT FROM AUTHOR]

The multiplier is an electronic circuit used in digital electronics, to multiply two binary numbers. The advantages of the multiplier are low power consumption, regularity of layout, less chip area, high speed etc. Multiplier plays an important role in today's digital processing and various applications. Multipliers are the key components in some high-speed systems such as FIR filters, microprocessors, ALU and other commercial applications like computers, mobiles, high speed calculators and some general-purpose processors require binary multipliers. Since last few years, the tiny size of MOSFET, that is less than tens of nanometres, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub threshold conduction and reduced output resistance. To overcome the above problems, FinFET has the advantages of an increase in the operating speed, reduced power consumption, reduced static leakage current is used to realize most of the applications by replacing MOSFET. By considering the attractive features of the FinFET, a multiplier is designed as an application. Sequential circuits are extensively used in the design of memory elements such as flip flops and register. Registers are used as data storage devices in low power VLSI designs. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the important performance metrics such as delay, power and power delay product (PDP), energy delay product (EDP) metrics into consideration. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

An integrated bootstrap diode emulator is experimentally investigated, including a high voltage (HV) junction field effect transistor (JFET) with adjustable pinch-off voltage ($\text{V}_{{\mathrm {P}}}$) and a medium voltage (MV) diode. It features substrate leakage current suppression, and it can be integrated to 600 V N-type epitaxial (N-epi) Bipolar-CMOS-DMOS (BCD) technology. The HV JFET is formed in a part of the high voltage isolation region and the MV diode is formed outside of the high voltage isolation region. In HV JFET, the extending P-type buried layer (PBL) is introduced as the back gate to adjust $\text{V}_{{\mathrm {P}}}$ of JFET. Since JFET is easy to pinch-off, and $\text{V}_{{\mathrm {P}}}$ of JFET is much lower than breakdown voltage (BV) of MV diode, the bootstrap diode emulator can obtain a high BV of 970 V at block mode. Moreover, BV of MV diode depends on the thickness and doping concentration of N-epi rather than the doping concentration of N-type buried layer (NBL). Thus, the highly doped NBL layer can be introduced in the junction of N-epi/P-sub to further suppress the substrate leakage current at conduction mode. Besides, due to the fact that HV JFET is a majority carrier device, the equivalent reverse recovery characteristic of the bootstrap diode emulator is also competitively, and the equivalent reverse recovery process is also qualitatively analyzed. [ABSTRACT FROM AUTHOR]

This article presents a fully integrated RF energy harvester (EH) with 30% end-to-end power harvesting efficiency (PHE) and supports high-output voltage operation, up to 9.3 V, with a 1.07-GHz input and under the electrode model for neural applications. The EH is composed of a novel ten-stage self-biased gate (SBG) rectifier with an on-chip matching network (MN). The SBG topology elevates the gate-bias of transistors in a nonlinear manner to enable higher conductivity. The design also achieves $>$ 20% PHE range of 12 dB. The design was fabricated in 65-nm CMOS technology and occupies an area of 0.0732 mm2 with on-chip MN. In addition to standalone EH characterization measurement results, animal tissue stimulation test was performed to evaluate its performance in a realistic neural implant application. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) inference and training produce a large amount of intermediate data. To achieve high energy efficiency, sufficient on-chip buffer is preferred to reduce the energy and time consuming off-chip DRAM access. However, SRAM buffer suffers from large area cost and high standby power due to its large cell size and high leakage current. Although embedded DRAM (eDRAM) offers higher memory density, its energy consumption is high due to frequent refresh operation, which is induced by the short refresh interval (40∼100μs). In this paper, a dual-mode buffer memory based on the CMOS compatible HfZrO2 ferroelectric material is proposed for DNN accelerators. It can operate in both volatile eDRAM mode and non-volatile ferroelectric RAM (FeRAM) mode. The functionality of the proposed dual-mode memory bit-cell design is verified using SPICE simulation with the multi-domain Preisach physical model. A data-lifetime-aware memory mode configuration protocol is proposed to optimize the buffer access energy for both DNN inference and training. Detailed circuitry and architectural support for the dual-mode memory are presented. For DNN training with ferroelectric-field-effect-transistor (FeFET) and SRAM-based compute-in-memory (CIM) accelerator, the proposed dual-mode buffer design improves the overall energy efficiency by 92.2%∼98.7%, 44.1%∼47.6%, 12.6%∼13.0% compared to baseline designs using SRAM buffer with the same buffer area, eDRAM and FeRAM with the same buffer capacity, respectively. For DNN inference with tensor-processing-unit (TPU)-like systolic array, the energy efficiency during computing is improved by 40.7%∼45.6%, 18.4%∼29.6% compared to the designs with eDRAM and FeRAM buffer, respectively. By storing the persistent data using the non-volatile mode, the energy efficiency of systolic array is improved by 2.3×∼5.5× over SRAM-based design when standby is frequent. The chip area overhead of the dual-mode buffer design is 5.2%, 4.1% and 7.2% for FeFET-based-CIM, SRAM-based-CIM and systolic-array-based accelerators using eDRAM buffer, respectively. [ABSTRACT FROM AUTHOR]

Converter topologies such as current-source rectifiers and inverters require switching devices with bipolar voltage blocking and unidirectional current conduction capability. Recently available dual-gate GaN monolithic bidirectional switches (MBDSs) can mimic such self-reverse-blocking (SRB) behavior if the MBDS’ two gates are controlled accordingly, but thus need twice the number of gate signals and gate drive circuits. Therefore, we propose cascode-diode control (i.e., without additional sensing or gate drive circuitry) of one MBDS gate using a cascode configuration with a low-voltage silicon Schottky diode. The resulting SRB-MBDS features quasi-ohmic conduction characteristic and single-gate control. We provide static and dynamic measurements of a discrete proof-of-concept realization (600-V, 190-m $\mathrm{\Omega }$ GaN MBDS; 40-V, 10-A silicon Schottky diode) that demonstrate the proposed SRB-MBDS’ feasibility. [ABSTRACT FROM AUTHOR]

Using the framework developed in the first part of this work, we demonstrate the capabilities of the extended two-state nonradiative multi-phonon (NMP) model by reproducing leakage current characteristics of two selected technologies. First, we identify the temperature-activated leakage mechanism in SiC / SiO2 stacks using a tens of nanometer thick thermally grown oxide as trap-assisted tunneling (TAT) through defects. Interestingly, this effect can be reproduced with the same parameters in a SiC / SiO2 stack with deposited oxide. Our simulations demonstrate that these charge transition centers are distributed within only a few nanometers from the SiC / SiO2 interface. The low thermal activation of the leakage current is linked to the low relaxation energies of the involved traps compared with those typically involved in bias temperature instability (BTI) and Random Telegraph Noise (RTN). Second, a similar mechanism can explain TAT characteristics and transient charge trapping currents in Metal–Insulator–Metal (MIM) capacitors with a ZrO2 insulating layer. By comparison of our model parameters to theoretical density functional theory (DFT) calculations, we identify self-trapped electrons (polarons) as a likely cause for these effects, as they have the required low relaxation energies. [ABSTRACT FROM AUTHOR]

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (${V}_{\text {side}}$). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage (${V}_{t}$) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm $\times $ 78 nm (width $\times $ length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and ${V}_{t}$ increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. ${V}_{t}$ can be adjusted from ~0.3 to ~1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using ${V}_{\text {side}}$. This high level of tunability allows electronic control of ${V}_{t}$ and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (<10−13 A). [ABSTRACT FROM AUTHOR]

A small subthreshold swing (SS) hydrogen-terminated diamond field-effect transistor is realized by using a wide bandgap material (SnO2). Results showed an SS of 106.4 mV/dec, which should be ascribed to the low interface state density (1.05 $\times10$ 12 cm $^{-2}\cdot $ eV−1) between SnO2 and diamond. The fixed charge density and trapped charge density are $1.1\times10$ 12 cm−2 and $8.6\times10$ 11 cm−2, respectively. Leakage current between source and gate is less than $2.1\times10$ −8 A at gate voltages from −5.0 to 1.0 V and the breakdown voltage is measured to be −180 V. In addition, the devices exhibit normally- OFF characteristics, whose threshold voltage and maximum drain current density are −0.12 V and −21.6 mA/mm with 4- $\mu \text{m}$ gate at ${V}_{GS} = -3$ V. The ON/OFF ratio is around 107 and the maximum effective mobility is extracted to be 165 cm2/(Vs). This work indicates that SnO2 dielectric could form low interface state density with hydrogen-terminated diamond surface and it also provides a simple method to realize normally- OFF devices. [ABSTRACT FROM AUTHOR]

This work presents a comparative study of the subthreshold swing (SS) in InAlN/GaN-based high electron mobility transistor (HEMT), with and without carbon doping in the buffer layer. It is observed that devices with carbon-doped (C-doped) buffer exhibit near-ideal SS of close to 60-mV/decade over a wide range of drain voltage for both up and downsweep. The C-doped buffer layer reduces the OFF-state drain leakage current and increases the drain current ON/OFF ratio. TCAD simulation of the vertical electric field under the gate shows that the sample with a C-doped buffer layer has a much lower value of the peak electric field at the drain side edge of the gate, resulting in lower reverse-biased gate leakage current and smaller SS compared to that of the undoped buffer. Moreover, the junction capacitance at the interface of the unintentionally doped GaN (UID:GAN) and the C-doped buffer layer, in series with the depletion capacitance, reduces the overall capacitance, which further improves the SS in the C-doped wafer. [ABSTRACT FROM AUTHOR]

The Smart Discrete concept which monolithically integrates a vertical high-voltage power device with low-voltage smart circuits has been widely adopted in silicon world for many years and may bring similar benefits to SiC world. For example, it is highly desirable to integrate a gate driver circuit onto a high-voltage SiC thyristor for ultra-fast turn-on. However, the electrical isolation between the vertical high-voltage power device and the low-voltage circuit elements remains a major technical challenge for silicon, and even more so for SiC due to the very limited processing options. In this article, we propose a combination of shallow junction isolation (JI) and partial dielectric isolation (DI) for high-voltage 4H-SiC smart thyristor, which is monolithically integrated with low-voltage nMESFET circuits. The characterization of fabricated devices and analysis of leakage currents across the isolation structure have been done to experimentally verify the feasibility of the isolation method. 8 V parasitic lateral NPNP thyristor between a 6.3 kV 4H-SiC thyristor and isolation moats, 175 V lateral PNP transistor between the passive resistor and isolation moats, and 10 V lateral reverse-biased p-n diode between nMESFET and isolation moats are experimentally demonstrated. [ABSTRACT FROM AUTHOR]

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between contact metal and CNT impacts both contact resistance and leakage current. The physical mechanisms underlying the effects are analyzed. A model with calibrated metal coupling strength from experimental data projects ION-IOFF design space to understand the trade-off between shrinking contact and extension lengths. For CNT with diameter of 1 nm, both contact and extension lengths greater than 8 nm are a good compromise between ION and IOFF for digital logic in advanced technology nodes. [ABSTRACT FROM AUTHOR]

In this work, we comprehensively studied the correlation between the electrical characteristics and the gate width (${W}_{G}$) of GaN-based HEMTs. On the one hand, as ${W}_{G}$ is scaled down from 100 $\mu \text{m}$ down to $3~\mu \text{m}$ , the devices exhibit five-times-enhanced on-state drain current density and largely reduced on-resistance, thanks to the increased electron mobility and mitigated self-heating effects in the narrow- ${W}_{G}$ channels. On the other hand, the devices with a wider ${W}_{G}$ exhibit reduced off-state leakage current and enhanced breakdown voltage, thanks to a decreased electric field and increased Schottky barrier height. Further temperature-dependent characterization reveals that the ${W}_{G}$ -modulation behavior on both on- and off-state device properties is still effective at a high temperature of 150°C. These experimental results can provide a straightforward approach for effective channel modulation and device optimization of GaN-based power devices of the future. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

This article studies the apparition and the fast annealing of a leakage current in p- and n-MOS transistors and structures. This leakage current is observed for total ionizing doses (TIDs) of 50 Mrad(SiO2) and above and anneals rapidly within the hours following the end of irradiation. An extensive set of specially designed and dedicated structures are used to study this phenomenon. In particular, the article presents the effects of the dose rate, the transistor type (n or p), the drain–source voltage, or the bias during annealing. Results show that the observed transient leakage current is an intensification followed by fast annealing of the generation current inside the drain and source depletion regions. It appears that this generation leakage current most likely originates from the creation of positive charges in the thick oxides of the devices, that is, the shallow trench isolation (STI) and the pre-metal dielectric (PMD), and it generally anneals at ambient temperature in less than 12 h after irradiation. [ABSTRACT FROM AUTHOR]

A CMOS ternary logic is demonstrated using a biristor threshold switch (BTS). A biristor, which can operate as a threshold switch, encloses a two-terminal n-p-n structure with a floating p-base region akin to a base-open BJT. The switching mechanism is a single-transistor latch (STL). When a BTS and a MOSFET are serially connected, three stable states are sustained for a ternary logic system. Compared to other ternary devices, static power can be greatly reduced due to low leakage current of the BTS. In addition, the BTS and the MOSFET were co-integrated due to their homeomorphy for fabrication simplicity, i.e., because the BTS has a structure identical to that of a MOSFET, unlike other threshold switches. [ABSTRACT FROM AUTHOR]

Direct bidirectional current discharge paths between input/output (I/O) and ground (GND) are imperative to achieve robust charged device model (CDM) protection for very stringent design window in advanced low-voltage (LV) processes. In this brief, a compact and fast response dual-directional silicon-controlled rectifier (CFR-DDSCR) has been proposed. Using P-electrostatic discharge (ESD) implantation layer to implement each diode-triggered silicon-controlled rectifier (SCR) within only one n-well, the inherent defect of the prior art (i.e., the cumbersome p-well/n-well triggering diode) is eliminated, ensuring the low resistance of auxiliary triggering path and the compactness of silicon footprint. Moreover, by shielding all internal shallow trench isolation (STIs) with floating high- ${k}$ metal gates (HKMGs), an all-gate-bounded SCR structure is realized, and all triggering diodes evolve into gated diodes with compact current paths, thus improving the CDM protection capability greatly. Experimental results indicate that the CFR-DDSCR, with a design window suitable for 1.2 V-CMOS technologies, acquires a higher effective CDM robustness (73% improved), a faster turn-on speed (64% improved), and a more compact layout (31% shrunk) compared with its conventional counterpart, which is promising for the advanced LV CDM protection. [ABSTRACT FROM AUTHOR]

The leakage current degradation, single-event burnout (SEB), and single-event gate rupture (SEGR) behaviors induced by the heavy-ion irradiation in p-Channel and n-Channel power U-shaped metal–oxide–semiconductor field-effect transistors (UMOSFETs) are comparatively investigated in this article via experiments and simulations. The SEB and SEGR performances of a commercially available −100-V-rated p-Channel UMOSFET are tested under heavy-ion irradiation. The experimental results show that the sample devices can be prevented from the drain leakage current or gate leakage current degradation under the bias conditions of $V_{\mathrm {GS}} = -100$ V and $V_{\mathrm {GS}} = 0$. However, a severe gate leakage current degradation can occur at $V_{\mathrm {DS}} = -100$ V when $V_{\mathrm {GS}} \ge 5$ V. In addition, the SEB and SEGR characteristics of a 100-V-rated n-Channel UMOSFET are obtained by simulations. The simulation results indicate that a p-Channel UMOSFET can achieve much better robustness against heavy ions compared with an n-Channel UMOSFET. Further, the leakage current degradation and failure mechanisms induced by heavy-ion irradiation are investigated via simulations. Finally, an effective method, which enlarges the width and depth of the source contact trench, is introduced to enhance the SEB tolerance of an n-Channel UMOSFET. The simulation result shows that the SEB threshold voltage can represent an increase of 23.1% with the hardening method. [ABSTRACT FROM AUTHOR]

In this article, a novel voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge (ESD) protection applications has been proposed and verified in a 65-nm epitaxial CMOS process. The trigger structure formed by a voltage divider and an nMOS is introduced to the proposed structure. The voltage divider composed of two series capacitors can control the turn-on of the nMOS, and the nMOS current can trigger the silicon-controlled rectifier (SCR) device to reduce the trigger voltage of the proposed device. Such triggering structure is fully embedded in the proposed device for saving area. The measurement results show that the proposed device can achieve a low trigger voltage of 2.88 V, a low leakage current of 120 pA, and the second breakdown current of 4.35 A for a 1.2-V application. Furthermore, the VDTSCR device can be immune from the risk of latch-up and false triggering. Due to the low trigger voltage and low leakage current of the proposed device, it is suitable for low-voltage and low-power applications. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of $1.8 \mu \text{m}$ and active area of 0.104 mm2 achieves a breakdown voltage of 1086 V and a specific ON-resistance of 0.98 $\text{m}\Omega \,\cdot $ cm2. The first-quadrant output and transfer characteristics are presented, from which the ON-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the ${x}$ -direction and trapezoidal mesas in the ${y}$ -direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop ($\vert {V}_{\text{on}}\vert $) and the maximum current before gate junction turn-on (${J}_{\text{umax}}$). The third-quadrant performance can be improved by using forward-on gate voltage, a $\vert {V}_{\text{on}}\vert $ lower than 0.2 V (at 100 A/cm2) and a ${J}_{\text{umax}}$ larger than 500 A/cm2 are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications. [ABSTRACT FROM AUTHOR]

We present a novel p-gallium nitride (GaN) gate HEMT structure with reduced hole concentration near the Schottky interface by doping engineering in metal-organic chemical vapor deposition (MOCVD), which aims at lowering the electric field across the gate. By employing the additional unintentionally doped GaN (u-GaN) layer, the gate leakage current is suppressed and the gate breakdown voltage is boosted from 10.6 to 14.6 V with negligible influence on the threshold voltage and ON-resistance. A reduced Mg concentration in the u-GaN layer was confirmed by secondary-ion mass spectrometry. Time-dependent gate breakdown measurements reveal that the maximum gate drive voltage increases from 6.2 to 10.6 V for a ten-year lifetime with a 1% gate failure rate, which effectively expands the operating voltage margin of the p-GaN gate HEMTs without any other additional process step. [ABSTRACT FROM AUTHOR]

Radiation-induced leakage current degradations for SiC power MOSFETs are investigated by 181Ta ion irradiation. An ion flux-related leakage degradation is reported for the first time. It is manifested as a more significant leakage current under higher flux irradiation than that under low flux irradiation, even though the total fluence is the same. Emission microscope (EMMI) results show that more leakage paths are formed for high flux irradiation. The drain bias during irradiation is another key fact to affect the radiation-induced leakage degradation. The leakage only occurs when the drain bias is larger than 300 V for flux = 1000/cm $^{2}\cdot \text{s}$ irradiation. An interesting phenomenon is that although radiation-induced leakage is not observed at 200 V with ion flux of 1000/cm $^{2}\cdot \text{s}$ , leakage appears when the ion flux increases to 6000/cm $^{2}\cdot \text{s}$. A multi-ion interaction theory is proposed to explain the above phenomenon. The mechanisms of these phenomena are also proved by TCAD simulations. [ABSTRACT FROM AUTHOR]

Composed of computation units each containing a parallel, dual-gate (DG) thin-film transistor (TFT) and a memory capacitor addressed by an access TFT, a neuromorphic circuit implementing fundamental AND and OR logic functions is realized and characterized. The exceptionally low leakage current of a TFT built on indium-gallium-zinc oxide (IGZO) allows the capacitor to be used as a quasi-static memory element. Appropriate weight signals for the realization of the two logic functions are obtained using a gradient-descent training algorithm. The circuit can be configured to execute one of the two functions by the setting of the weight signals. [ABSTRACT FROM AUTHOR]

The performance of a novel ‘buffer-free’ AlGaN/GaN-on-SiC MISHEMTs for power switching applications is demonstrated in this letter. High voltage operation with exceptionally low gate and drain leakage currents is shown. A specific on-resistance of 3.61 m $\boldsymbol {\Omega } \cdot $ cm2 and an abrupt breakdown voltage of 1622 V at a drain current of 22 nA/mm is achieved. Using two-terminal breakdown measurements, nitrogen-implanted GaN display breakdown fields of 0.96 MV/cm. The semi-insulating SiC substrate is capable of suppressing vertical leakage currents, ensuring that off-state operation is limited by lateral breakdown. The impact of electron trapping effects on dynamic on-resistance is small up to a drain quiescent voltage of at least 240 V. Drain current transient characteristics display a 14% increase in dynamic on-resistance with respect to quiescent drain bias, and a negligible change in resistance up to 100 ms. These types of ‘buffer-free’ heterostructures are of interest for power electronic applications above 1000 V and with potential for co-integration of power and RF-electronics. [ABSTRACT FROM AUTHOR]

Diverse areas such as the Internet of Things (IoT), aerospace and industrial electronics increasingly require non-volatile memory to work under high-temperature, radiation-hard conditions, with zero standby power. Nanoelectromechanical (NEM) relays uniquely have the potential to work at 300 °C and absorb high levels of radiation, with zero leakage current across the entire operational range. While NEM relays that utilise stiction for non-volatile operation have been demonstrated, it is not clear how to design a relay to reliably achieve given programming and reprogramming voltages, an essential requirement in producing a memory. Here, we develop an analytical, first-principle physics-based model of rotational NEM relays to provide detailed understanding of how the programming and reprogramming voltages vary based on the device dimensions and surface adhesion force. We then carry out an experimental parametric study of relays with a critical dimension of $\approx ~\mathrm {80~~\, \text {n} \text {m} }$ to characterise the surface adhesion force, and derive guidelines for how a NEM relay should be dimensioned for a given contact surface force, feature size constraints and operating requirements. We carry out a scaling study to show that voltages of $\approx ~\mathrm {1~~\, \text {V}}$ and a footprint under $\approx ~\mathrm {2~~\, \mu \text {m} ^{2}}$ can be achieved with a critical dimension of $\approx ~\mathrm {10~~\, \text {n} \text {m} }$ , with this device architecture. [2021-0138] [ABSTRACT FROM AUTHOR]

In this study, a circuit- and device-level design was developed to improve the radiation tolerance of an analog switch integrated circuit (IC), which was fabricated using a commercial 0.35- $\mu \text{m}$ bipolar–CMOS–DMOS (BCD) process. Both circuit- and layout-level approaches were used to improve the total ionizing dose (TID) tolerance of the IC. In the circuit-level approach, a level shift unit was used to reduce the amount of oxide traps. Under the layout-level approach, a ring gate and a doping ring were added to reduce the leakage current. Moreover, the optimum doping concentration of $P_{\mathrm {WELL}}$ and length of the $N_{+}$ drift zone were calculated for the n-MOSFET based on simulations to obtain the best device structure and improve the single-event burnout (SEB) tolerance. The radiation tolerance was tested experimentally. The results indicated that the newly designed 30-V high-voltage low-power analog switch chip had a TID tolerance >300 krad(Si) and a SEB tolerance >75 MeV cm2/mg, which are useful to improve the radiation-tolerant capability of high-voltage analog switches. [ABSTRACT FROM AUTHOR]

The electrical characteristics of 2.3-kV 4H-SiC power Junction Barrier Schottky Field-Effect Transistors (JBSFETs) fabricated with 55-nm gate oxide thickness are reported as a function of temperature for the first time. The behavior of three cell topologies (linear, hexagonal, and octagonal) is compared. Excellent JBSFET characteristics are demonstrated up to 150 °C. The ON-resistance was found to increase by 45% from 25 °C to 150 °C for the linear and hexagonal cell layouts, which is much less than the 100% increase previously reported for silicon carbide (SiC) power MOSFETs. The threshold voltage decreases with temperature but remains above 1.2 V even at 150 °C for all cases. The third-quadrant current flow via the integrated JBS diode is confirmed to suppress body diode conduction at all temperatures. The leakage current remains below $1~\mu \text{A}$ even at 150 °C despite the presence of the Schottky contact in the JBSFET structure due to optimum JBS diode design. The octagonal cell topology is shown to exhibit the best figures of merit (FOMs) FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{C}_{ \mathrm{\scriptscriptstyle GD}}$ ] and FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{ Q}_{ \mathrm{\scriptscriptstyle GD}}$ ] even at elevated temperatures. The observed device behavior is explained using device analytical modeling. The analytical modeling reveals that the reduced rate of increase in ON-resistance with temperature for the 2.3-kV SiC JBSFETs is due to the relatively large source contact resistance produced by the lower (900 °C) contact anneal temperature. The lower anneal temperature is required to simultaneously make the Schottky contact for the JBS diode. [ABSTRACT FROM AUTHOR]

In this study, we demonstrate a novel recessed channel ferroelectric field-effect transistor (FeFET) with gate metal/ferroelectric (FE) layer/inter-metal (IM)/interlayer (IL)/Si stacks, which can be called as dual metal gates recessed channel FeFET (DM-RFeFET), for nonvolatile memory applications with high performance and robust reliability. Through technology computer-aided design (TCAD) simulations with calibrated FE and device model parameters, it is revealed that the DM-RFeFET can have the wide memory window (MW) and the possibility of endurance improvement by maximizing the area ratio of FE and IL without sacrificing the footprint. Furthermore, the guidelines for the DM-RFeFET design are provided in terms of recess depth and additional high- ${k}$ blocking layer between IM and IL to maximize the MW and to minimize IM charging by the gate leakage current. [ABSTRACT FROM AUTHOR]

In this article, an ultrahigh voltage silicon carbide (SiC) gate turn off (GTO) Thyristor with a novel trench-modulated two-zone junction termination extension (TM-TZ-JTE) is investigated through TCAD simulations and experimental fabrications. Bevel trench rings are included in each JTE to achieve a smooth decrease of the effective JTE dose from the inner side to outer side of the termination, which significantly increases the tolerance window to the both vertical and horizontal etching process variations without increasing the total number of lithography masks. TCAD simulations indicate that the tolerance window of TM-TZ-JTE to the interface charges is over two times larger than that of the conventional TZ-JTE. Experimental measurements demonstrate that the device could achieve a breakdown voltage (BV) of 12.5 kV at a leakage current of $1 \mu \text{A}$. The voltage drop on unit termination length is the highest among the reported terminations for SiC GTOs, which is preferred for improving the power density. The differential ON-resistance at a current density of 100 A/cm2 is 7.91 $\text{m}\Omega \cdot $ cm2. The current rising and falling time under inductive switching test are 1.5 and $2.3 \mu \text{s}$ , respectively. Finally, the bipolar degradation due to the N+ implantation is evaluated. After 10-h accelerating test, only slight degradation of forward voltage drop is observed. [ABSTRACT FROM AUTHOR]

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at ${V}_{\text {DD}} = {0.6}$ V and ${T} = {80}\,\,^{\circ }\text{C}$. The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology. [ABSTRACT FROM AUTHOR]

In this article, a novel S-gate-assisted silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistor (SGA SOI n-MOSFET) structure is proposed in order to suppress the total ionizing dose (TID) effect. The new structure settles the radiation-induced leakage current by isolating both the source and drain from the shallow trench isolation (STI) oxides and introducing two auxiliary gates. This work simulates the TID irradiation of three SOI n-MOSFET devices by Sentaurus TCAD and verifies the anti-TID irradiation characteristics of the proposed SGA SOI n-MOSFET. After the novel SGA SOI n-MOSFET was irradiated with 500 krad(Si), the OFF-state leakage current is only marginally increased, the ON-state leakage current is almost unchanged, the threshold voltage drift is 9.423%, and the transconductance degradation is only 7.453%. The simulation results demonstrated the proposed SGA SOI n-MOSFET resisted TID radiation doses up to 500 krad(Si). Meanwhile, the SGA SOI n-MOSFET is much more compact and saves tremendous cost compared with the H-gate-assisted (HGA) SOI n-MOSFET during very large scale integration (VLSI) fabrication and mass production. Moreover, the SGA SOI n-MOSFET solves the disadvantages of the ring-gate-assisted (RGA) SOI n-MOSFET complex aspect ratio ${W}/{L}$ design. The SGA SOI n-MOSFET offers a better alternative for nonultrahigh radiation dose environments. [ABSTRACT FROM AUTHOR]

The collector engineered bidirectional insulated gate bipolar transistor (CEB-IGBT) with p-buffer and semi-superjunction (Semi-SJ) is proposed. The structural modification at collector side provides support to reverse breakdown voltage ($\text {BV}_{R}$) in two ways. First, the p-buffer layer allows the device to deplete completely and eliminates premature breakdown effects. Second, the Semi-SJ region introduces an electric field component in the ${x}$ -direction (${E}_{X}$) in order to further improve the $\text {BV}_{R}$. The overall increased electric field, which is a resultant of ${E}_{X}$ and ${E}_{Y}$ , improves $\text {BV}_{R}$ by 53.83% compared to nonpunchthrough IGBT (NPT-IGBT). The efficient potential distribution in the drift region provides support to forward breakdown ($\text {BV}_{F}$) as well. The n-layer below p-body acts as a field stop (FS) layer, which reduces the leakage current during the OFF-state condition. The p-buffer, which injects higher minority charges along the drift side and n-layer with charge storage effect collectively, provides conductivity modulation in the epitaxial region in order to increase current handling capability. This high collector current density leads to reduce ${V}_{ \mathrm{\scriptscriptstyle ON}}$ by 14.5% compared to NPT-IGBT. Furthermore, the charge coupling effect of Semi-SJ region enables the proposed device to turn-off quickly with higher pillar doping and reduces turn-off loss (${E}_{ \mathrm{\scriptscriptstyle OFF}}$) in comparison with NPT-IGBT. [ABSTRACT FROM AUTHOR]

The ohmic contact resistance (${R}_{C}$), surface resistance (${R}_{S}$), and channel resistance (${R}_{\text {CH}}$) of hydrogen-terminated diamond (H-diamond) MOSFETs were investigated in this study. Planar-type and T-type H-diamond MOSFETs were employed to analyze them. Because no interspaces exist between the source–drain and gate electrodes for the T-type H-diamond MOSFETs, then ${R}_{S}$ is zero. Both planar-type and T-type MOSFETs show low leakage current densities and good operations. By considering the relationships between the total resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and 1/ $\vert $ gate voltage-threshold voltage $\vert $ , ${R}_{C}$ and ${R}_{\text {CH}}$ for the T-type H-diamond MOSFET at a gate voltage of −10.0 V are determined to be 13.8 and 21.8 $\Omega \cdot $ mm, respectively. As ${R}_{C}$ for both MOSFETs is the same, ${R}_{S}$ and ${R}_{\text {CH}}$ for the planar-type H-diamond MOSFET are deduced to be 90.0 and 15.8 $\Omega \cdot $ mm, respectively. ${R}_{S}$ accounts for 75.3% of ${R}_{ \mathrm{\scriptscriptstyle ON}}$ for the planar-type H-diamond MOSFET, which is the main reason for its lower drain current and extrinsic transconductance than those of the T-type MOSFET. Although ${R}_{S}$ is suppressed for the T-type H-diamond MOSFET, ${R}_{C}$ occupies 38.8% of ${R}_{ \mathrm{\scriptscriptstyle ON}}$. To further improve the performance of the H-diamond MOSFETs, it is important to eliminate ${R}_{S}$ and decrease ${R}_{C}$ to further improve the electrical properties of the H-diamond MOSFETs. [ABSTRACT FROM AUTHOR]

In this article, solution-derived amorphous cerium oxide (CeO2) with smooth surface as gate dielectric has been investigated. Electrical analysis has indicated that ALD-derived 3 nm Al2O3 passivation layer on CeO2 surface is benefit to reduce leakage current of CeO2 MOS capacitors. Meanwhile, solution-processed In2O3 thin-film transistors (TFTs) based on optimized Al2O3/CeO2 bilayer dielectric are integrated for the first time. Results indicate that 300 °C annealed In2O3/Al2O3/CeO2 TFT presents high performances with saturation mobility of 18.25 ± 0.92 cm2/ $\text{V}\cdot \text{s}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of (1.81 ± 0.30) $\times \,\,10^{{7}}$ , subthreshold swing of 0.071 ± 0.002 V/decade, interfacial trap states (${D}_{\,\text {it}}$) of (6.00 ± 0.48) $\times \,\,10^{{11}}$ cm $^{-{2}}$ , and remarkable positive bias stress (PBS) stability, respectively. Furthermore, a resistor-loaded inverter is fabricated with voltage gain of 12.81 at 5 V and good voltage-transfer characteristics (VTCs), demonstrating the potential application of Al2O3/CeO2 as high- ${k}$ gate stacks for future TFTs. [ABSTRACT FROM AUTHOR]

The anode-short metal–oxide–silicon (MOS)-controlled thyristor (AS-MCT) is the latest generation of MCT. Due to its MOS gating, high-current-rise rate, normally-OFF, and high blocking capabilities, the AS-MCT is an ideal switch for pulse discharge application. Previously, we show that the static behaviors of AS-MCT are susceptible to displacement damage (DD) as it contains bipolar structures. As a continuation of our previous work, this article reports the experimental results for the degradation of pulse discharge circuit (PDC) characteristics induced by the DD of its XND1 AS-MCT switch following fast neutron exposure up to $7.8\times {10}^{13}\,\,{\text {cm}}^{-2}$. Both the charging time and the peak surge current of the PDC decrease significantly once the neutron flux surpasses a critical value, $\sim {10}^{12}\,\,{\text {cm}}^{-2}$. From device and circuit physics perspectives, an analytical model based on equivalent leakage current resistance is proposed to describe the degradation of the two parameters, and then, this article suggests the mechanisms behind such degradations from the neutron exposure of AS-MCT switch. [ABSTRACT FROM AUTHOR]

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized under dynamic and static test conditions through changes in ring oscillator (RO) frequencies, leakage currents, and inverter delays. Results from total-dose exposures using the ARACOR X-ray machine showed that static conditions represented the worst case conditions. Higher operating frequencies resulted in increased leakage currents and inverter delays after irradiation. The rate of change for leakage current was inversely proportional to frequency during exposure. The rate of change for inverter delay was directly related to frequency during TID exposure. Overall, degradations in circuit-level parameters (logic gate delays and operating current) were less than 1% for TID exposures of 435 krad(SiO2). [ABSTRACT FROM AUTHOR]

Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-around (GAA) nanowire (NW) devices are characterized for different biasing conditions. Negative-bias-stress-induced degradation in Ge GAA device originates primarily from the interface- and border-trap generation. Devices stressed at high gate voltage show rapid initial degradation and quick saturation dominated by interface-trap generation. Radiation-induced OFF-state leakage current in Ge GAA NWs increases with dose due to enhanced band-to-band tunneling (BTBT) caused by charge trapping in the shallow trench isolation (STI). [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) transistors exemplify the fundamental tradeoff between desirable high mobility and undesirable leakage current due to the small effective mass and bandgap. To understand leakage current limits in high-speed CNT transistors, electrical bandgaps are extracted on 12 single-CNT top-gate MOSFETs from the energy gap between thermionic emission and band-to-band tunneling (BTBT) at 10 K. At 300 K the minimum IOFF at 0.5 V VDS is analyzed as a function of bandgap between 0.96 eV and 0.43 eV with IOFF-MINfrom 0.2 pA/CNT to 15 nA/CNT. NEGF simulation validates the bandgap extraction methodology and reproduces the experimental MOSFET IOFF-MIN data. A TCAD model calibrated to this work’s leakage data projects the accessible ION-IOFF design space bounded by CNT bandgap, indicating EG > 0.65 eV (dCNT < 1.3 nm) is needed to achieve 100 nA/ $\mu \text{m}$ at 0.5 V VDD and 250 CNT/ $\mu \text{m}$ for channel length above 20 nm. An EG of 1.06 eV (dCNT = 0.8 nm) can deliver $2750\times $ tunable range of IOFF by adjusting VT, which exceeds the $400\times $ tunable range of IOFF used in Si CMOS platform technologies. [ABSTRACT FROM AUTHOR]

Breakdown mechanism in 0.25- ${\mu } \text{m}$ gate length AlGaN/GaN-on-SiC iron doped high electron mobility transistors (HEMTs) with background carbon is investigated through the drain current injection technique. The measurement results reveal that it can be divided into two distinct stages according to the gate voltage levels. The first stage of the measured drain injected breakdown is mainly due to the initiation of the punchthrough process under the gate, and the second stage of breakdown is associated with the potential barrier between the unintentionally doped (UID) GaN and the Fe doped p-type GaN buffer layer which also has a higher carbon density. The electroluminescence (EL) results suggest that the first stage shows uniform punchthrough current flow, but localized leakage current flow associated with a snapback breakdown mechanism replaces the uniform punchthrough current flow and dominates the second stage. A 2D-TCAD simulation has been implemented and shows the current paths under uniform flow conditions. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Si-rich SiN/Si3N4 bilayer passivation were studied in this article. The use of a Si-rich SiN interlayer leads to improved channel transport property, current collapse, power performance, and temperature-dependent stability. Devices without Si-rich SiN interlayer passivation exhibit an increase in the gate leakage current by over three orders of magnitudes with temperature increasing from 300 to 420 K, leading to an increase in a current collapse from 9.7% to 24.7%, while the devices with Si-rich SiN passivation exhibit a weak temperature dependence of leakage current and a constant current collapse about 5%. Small signal characterization shows that Si-rich SiN passivation results in a remarkable decrease in the effective gate length by ~15% with temperature up to 420 K. At 17 GHz, devices with Si-rich SiN interlayer passivation exhibit an output power density of 7 W/mm and a peak power-added efficiency (PAE) of 56%. The improved power performance of devices using Si-rich SiN interlayer passivation is attributed to the suppressed current collapse and superior device stability under high channel temperature. [ABSTRACT FROM AUTHOR]

In this article, InGaAs FinFETs using (010) orientation channel and nitrogen post remote plasma (RP) treatment have been fabricated. This device exhibits a peak transconductance, ${g}_{m}$ , of 2727 $\mu \text{S}/\mu \text{m}$ which is among the highest values reported for In0.53Ga0.47As FinFETs. In addition, subthreshold performances are improved with leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) of $1.13\times 10^{-{4}}~\mu \text{A}/\mu \text{m}$ , subthreshold swing (SS) of 78 mV/dec, drain-induced barrier lowering (DIBL) of 55 mV/V, and equivalent oxide thickness (EOT) ~0.8 nm. These excellent results are attributed to the strong electrostatic control and the superior high- $\kappa $ /InGaAs interface quality achieved by scaled fin width and RP passivation. [ABSTRACT FROM AUTHOR]

This work reports recent progress in the sub-6 GHz power performance of GaN-based HEMTs grown on high resistivity silicon substrates with passivation implanted termination (PIT) process. Thanks to the mitigated electric field crowding at the gate edge and the suppressed negative fixed charge-induced carrier depletion, the fabricated HEMTs demonstrate a low leakage current, a high ON/OFF current ratio of 108, and improved breakdown voltage associated with a current collapse at 40 V drain quiescent condition of as low as 5.6%. S-band continuous-wave large signal measurements yield a high power-added efficiency (PAE) of 69%, a drain efficiency (DE) of 72%, and an output power density (${P}_{\text{out}}$) of 7.2 W/mm at ${V}_{\text{DS}}=30$ V. Moreover, the transistor delivers a maximum ${P}_{\text{out}}$ up to 10.2 W/mm with a peak PAE of 63.8% at ${V}_{\text{DS}}=40$ V. The PAE and ${P}_{\text{out}}$ as a function of drain bias indicate that the transistors remain constant high PAE and linearly increased ${P}_{\text{out}}$ over a wide range of drain voltage variation. These excellent results have demonstrated the PIT process could be an attractive technique to facilitate the application of high-performance and cost-competitive GaN-on-Si HEMTs for 5G wireless base stations. [ABSTRACT FROM AUTHOR]

Endurance to cyclic program/erase (P/E) in a gate-all-around (GAA)-based SONOS flash memory device is improved by Joule heat, which was driven by gate-induced drain leakage (GIDL) current (${I}_{\text {GIDL}}$) with a current level of microamperes. By use of COMSOL simulation, induced temperature (${T}$) by the ${I}_{\text {GIDL}}$ is higher at the GAA with the ONO gate dielectrics than at a GAA with a thermal gate oxide due to the confined heat inside a silicon nanowire channel wrapped by a relatively thick ONO. Furthermore, ${T}$ is high enough to cure the damage from the iterative P/E operations. For a quantitative evaluation of the damage level before and after cyclic P/E, border trap density (${N}_{\text {bt}}$) in a tunneling oxide was analyzed with the aid of low-frequency noise (LFN) measurements. The damage was almost fully cured by ${I}_{\text {GIDL}}$ without an external Joule heater or structural modifications because it is always around a MOSFET. [ABSTRACT FROM AUTHOR]

In this work, the effects of Rare-Earth (RE) doping (Y, Gd, Dy, Yb) in HfO2 on the interface chemistry and leakage current conduction mechanism of Ge-MOS devices have been explored. The electrical experimental results have indicated that ${\text{HfREO}}_{\!{x}}$ (RE = Gd and Dy) show excellent performance, including the reduced flat-band voltage, almost disappeared hysteresis, and the decreased leakage current, which can be attributed to the tradeoff of performance between lanthanide-based oxides and HfO2. X-ray photoelectron spectroscopy (XPS) measurements also display that ${\text{HfGdO}}_{\!{x}}$ and ${\text{HfDyO}}_{\!{x}}$ gate dielectrics can effectively inhibit the formation of unstable Ge suboxides and low- ${k}$ germanate interface layer, leading to the reduced defect state at/near the interface and the improved electrical performance. In addition, the doping element-dependent leakage current conduction mechanism of Ge-based MOS devices under low temperature has been investigated systematically. As a result, it can be inferred that RE doping has a significant impact on Hf-based MOS capacitors, and Hf-based gate dielectrics doped with heavy RE elements show excellent application prospects in future microelectronic devices. [ABSTRACT FROM AUTHOR]

To control the parasitic conduction between devices, photolithography and dry etching of organic thin-film transistors (OTFTs), which utilize the gate metal as a hard-mask for organic semiconductor (OSC) patterning, are used. This study shows that the hard-mask patterning process results in a gate leakage current, which is attributed to the sidewall defects. The characteristic mechanisms of different leakage currents were studied to understand this behavior, including negative-bias temperature stress (NBTS) testing and measurements of devices with structural asymmetry. Additionally, an optimized structure design is proposed to suppress the leakage and increase the reliability of OTFTs. Such improvements are necessary for practical applications of OTFTs requiring small channel widths, such as displays and logic circuitry. [ABSTRACT FROM AUTHOR]

In this work, the steady-state and transient behavior of the metal–insulator–semiconductor tunnel diodes with designed high-low (H/L) oxide layers were studied, by performing experiments and TCAD simulations. The H/L oxide layers were formed by thickening the oxide around the gate edge while still in a tunneling-transparent thickness. This could reduce the leakage or tunneling current at reverse bias by decreasing the minority carrier density near the gate edge via the induced lateral electric field caused by H/L oxides. The characteristics of devices with various designed parameters were under investigation to discover the necessary conditions for the tunneling current reduction. Due to the leakage current reduction, the enhancement of transient current was found out, accompanied with enlarged transient capacitance change. Steady-state and transient simulation could help to confirm the observed phenomenon and also illustrated the existence of lateral electron current flow that reduced the minority carrier density near the gate edge at reverse bias. A memory operation using the H/L device was demonstrated. The read current at 120 ms improved more than an order of magnitude in current window with respect to planar. The stable performance under endurance testing made the H/L device a possible future volatile memory application. [ABSTRACT FROM AUTHOR]

Schottky contacts have been used to fabricate normally- OFF lateral reverse-blocking MESFETs on p-type (boron-doped) O-terminated monocrystalline diamond. The devices utilized an ohmic source contact but both gate and drain contacts were Schottky in nature. Boron-doped p-channel diamond MESFETs reported to date display the less attractive normally- ON characteristics. Here, the normally- OFF transistor delivered a current level of ~1.5 $\mu $ Amm−1 at a negative ${V}_{\text {GS}}$ of 0.8 V and a transconductance (${g}_{m}$) of $16~\mu $ Smm−1, measured at room temperature (RT); at a temperature of 425 K, these values rose to $\sim 70~\mu $ Amm−1 for ${I}_{\text {DS}}$ and a ${g}_{m}$ value of $260~\mu $ Smm−1. In both cases, a negligible gate leakage current was measured with no breakdown apparent at the maximum field investigated here ($3.7\times 10^{{5}}$ V/m−1). The Schottky gate demonstrates a well-behaved control of the channel even at higher temperatures. The high-temperature operation, normally- OFF behavior, and diamond’s inherent radiation hardness make this transistor promising for harsh environment applications. [ABSTRACT FROM AUTHOR]

In this study, dual-gate thin-film transistors with low-temperature polysilicon as the active channel layer are thoroughly investigated. Under a large current operation where a high voltage is applied, impact ionization occurs near the drain, generating a large number of electron-hole pairs. Owing to the positive bias applied to the gate and drain, holes accumulate on the backside of the channel, which causes an earlier turn-on in the sub-channel, as is observed in the I-V characteristics of the saturation region. By enlarging the highly doped region between the double gates in the channel, the threshold voltage shift can be completely suppressed, and the leakage current rise can be reduced. The electric field simulation using Silvaco TCAD was consistent with the experimental results. Finally, a series transistor structure is used to measure the impact after the operation condition and further verify the physical model. [ABSTRACT FROM AUTHOR]