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This paper proposes a digital logic circuit in the source driver for OLEDoS micro display which uses a novel data signal tree structure with clock gating logic to reduce power consumption. The proposed structure for 4096×4096 (4K) 144 Hz micro displays was verified using a CMOS 110 nm process. The power consumption was reduced by 69.6 % compared to the conventional data signal tree structure, enabling a low‐power design. [ABSTRACT FROM AUTHOR]

Due to its powerful brain‐like parallel computing and efficient data processing capabilities, memristors are considered to be the core components for building the next generation of artificial intelligence systems. In this study, the CeOx/WOy heterojunction is employed as the functional layer, and various metal materials are utilized as the top electrode to fabricate the memristor. The results indicate that the memristive performance of the Ag/CeOx/WOy/ITO device can be improved by using Ag as the top electrode. By studying the conductivity mechanism of the device, a conductivity model is established that regulates oxygen vacancies and Ag conductive filaments. Furthermore, using the as‐prepared memristor, it is constructed four basic digital logic circuits: OR, AND, XOR, and XNOR, as well as a half adder and a full adder that can be used for digital arithmetic operations. Specifically, an odd/even checker is developed based on XOR and XNOR logic circuits to verify the correctness of data transmission. Finally, it is also designed and implemented a cryptographic array based on a memristor, which can be applied to encrypt and decrypt a series of numbers and images. Therefore, this work extends the application of memristor toward digital circuits, information transmission, data processing and image security encryption. [ABSTRACT FROM AUTHOR]

The object of this study is models of low-power digital logic circuits. The problem being solved is the effectiveness of the technique for simplifying Boolean functions to obtain optimal structures of logic circuits. A new theorem of a non-standard system of simplification of Boolean functions has been formulated, according to which in order to obtain a minimal function it will suffice to perform all non-redundant operations of simple and/or super-gluing of variables, which ultimately provides a minimal function in the main basis without using an implicant table. Thus, the problem of simplifying Boolean functions to the simplest normal equivalent is solved in one step. The interpretation of the result is that the properties of 2-(n, b)-design combinatorial systems make it possible to reproduce the definition of logical operations of super-gluing variables, to represent logical operations in a different way, and vice versa. This, in turn, ensures the establishment of the locations of equivalent transformations on the binary structure of the truth table and the implication of a systematic procedure for simplifying Boolean functions by an analytical method. Special feature of the results is that unambiguous identification of the locations of equivalent transformations is possible even when different intervals of the Boolean space containing the 2-(n, b)-design systems have common modules. It has been experimentally confirmed that the non-standard system improves the efficiency of simplifying Boolean functions, including partially defined ones, by 200–300 % compared to analogs. In terms of application, a non-standard system for simplifying Boolean functions will ensure the transfer of innovations to material production: from conducting fundamental research, expanding the capabilities of digital component design technology to organizing serial or mass production of novelties. [ABSTRACT FROM AUTHOR]

As an emerging nanodevice, Quantum-dot cellular automata (QCA) is a hopeful candidate for conventional complementary metal oxide semiconductor devices. XOR, one of the most vital gates, occupies a significant positon in digital logic circuits. In order to improve the property performance of XOR, a novel five-input majority gate is put forward first. Then, an efficient XOR employing a NAND-NOR-Inverter (NNI) and the proposed five-input majority voter is realized in the paper. Compared with previous counterparts based on gates, the proposed design requires fewer cells, occupies less area, and consumes less average energy consumption. Specifically, it improves by 11.11% in cell count, 2.11% in area, and 9.51% (1.5Ek) in energy consumption when compared to the state-of-the-art design. The clock delay of the XOR in the article keeps the same with the minimum of them. Additionally, the proposed design has the lowest QCA cost, including area-delay cost, QCA-specific cost, and energy-delay cost. Moreover, the design is coplanar, without any crossing types. All these make it an outstanding design. To demonstrate its practicality, n-bit parity generators using the proposed XOR are implemented. The novel 4-bit parity generator excels in cell count, area, and average energy dissipation, achieving optimization of up to 10.6%, 6.0%, and 38.6% (0.5Ek), respectively, compared to previous optimum values. The significance of these optimization results becomes more pronounced as the bit of parity generators increases, indicating a promising future for constructing complex circuits. [ABSTRACT FROM AUTHOR]

A set of laboratory exercises are presented, which use the video game Minecraft as the environment for teaching combinational digital logic in an introductory electronics lab. Several advantages are noted when students use the virtual Minecraft environment prior to building any real digital circuits. Editor's Note: Looking for new ways to connect with your students or to get your students to connect with each other? If so, Minecraft may be for you! In this paper you'll learn how to use the best-selling video game in history to develop digital electronics activities that teach concepts as simple as basic logic gates or as complicated as the emulation of a whole working computer. [ABSTRACT FROM AUTHOR]

This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme. [ABSTRACT FROM AUTHOR]

[Display omitted] There is an unceasing quest to create novel forms of intelligent active matter that exhibits sensing, energy harvesting, actuating, computing, and communication functionalities. Realizing such capabilities can provide new road maps to autonomous and electronic materials with numerous applications in robotics, human–machine interfacing, micro/nano-electromechanical systems, and flexible electronics. Here, we introduce "mechanical metamaterial electronics (meta-mechanotronics)" as a platform for designing intelligent matter that can sense external stimuli, self-power and process the information to create an integrated closed-loop control system. We achieve these advanced functionalities by fusing mechanical metamaterials, digital electronics and triboelectric nano energy harvesting technologies. Meta-mechanotronic systems use only their constituent components and integrated nanogenerator mechanisms to perform self-powered mechanical–electrical-logic and information storage operations. Thus, they establish a direct interaction mechanism between the external environment and electronics, which is a radically different approach from conventional electrically-controlled units. We demonstrate digital unit cells as building blocks for meta-mechanotronics to perform various self-powered computation functionalities. Analytical models, numerical simulations and experimental studies are performed to design a suite of electronic mechanical metamaterials capable of synthesizing discrete mechanical configurations, performing binary/ternary computations, and realizing digital logic gates, i.e., AND, OR, XOR, NAND, NOR, and XNOR. We demonstrate the capability of the framework by creating self-powered mechanically-responsive data storage devices that can store various ASCII codes. Further discussion is provided on how meta-mechanotronics and the associated circuitry can lead to developing future mechanical metamaterial computers, complementing traditional electronics with electronics made of mechanical metamaterials. [ABSTRACT FROM AUTHOR]

DNA as an informational polymer has, for the past 30 years, progressively become an essential molecule to rationally build chemical reaction networks endowed with powerful signal‐processing capabilities. Whether influenced by the silicon world or inspired by natural computation, molecular programming has gained attention for diagnosis applications. Of particular interest for this review, molecular classifiers have shown promising results for disease pattern recognition and sample classification. Because both input integration and computation are performed in a single tube, at the molecular level, this low‐cost approach may come as a complementary tool to molecular profiling strategies, where all biomarkers are quantified independently using high‐tech instrumentation. After introducing the elementary components of molecular classifiers, some of their experimental implementations are discussed either using digital Boolean logic or analog neural network architectures. [ABSTRACT FROM AUTHOR]

The development of nanoscale technologies has come from the downsizing of electronic equipment and the inadequacy of CMOS innovation resulting from hybrid circuit establishment and its failure to respond to nanoscale. Quantum-based technologies, like quantum-dot cellular automata (QCA), are likely to succeed the present technologies due to their incredible benefits, like faster processing, smaller footprints and ultra-low energy usage. In arithmetic and comparison circuits, the fundamental gate is frequently used. Arithmetic logic circuits centered on OR, AND and NOT logic gates have a low design complexity. To obtain complicated logic gates, several architectures have been proposed in the QCA. This work offers a QCA composite gate that achieves all critical digital logic gates, including Inverter, OR, AND, NAND, NOR and exclusive gates like XOR and XNOR. All basic logic is generated in a single unit with this architecture. Only 0.09 μ m2 of area, three three-input majority gates, one XOR, three Inverters, and 0.5 clock zones were required for the suggested circuit. As a result, a decrease of 33% in cell count is achieved compared to the previous systems. The design is evaluated and the dissipated energy is analyzed. For the research on power dissipation, the QCADesigner-E simulator is used to verify the final result. The simulation outcomes show that the suggested layout is advantageous over earlier constructions regarding the area, number of cells, clock phases and cost. The design complexity of arithmetic logic circuits based on OR, AND, and NOT logic gates is low. Inverter, OR, AND, NAND, NOR, and exclusive gates like XOR and XNOR are all achieved via the QCA composite gate provided in this work. Three three-input majority gates, one XOR, and three inverters produce all the fundamental logic. [ABSTRACT FROM AUTHOR]

Graphene-based vertical Schottky-barrier transistors (SBTs), renowned as graphene barristors, have emerged as a feasible candidate to fundamentally expand the horizon of conventional transistor technology. The remote tunability of graphene's electronic properties could endorse multi-stimuli responsive functionalities for a broad range of electronic and optoelectronic applications of transistors, with the capability of incorporating nanochannel architecture with dramatically reduced footprints from the vertical integrations. In this Feature Article, we provide a comprehensive overview of the progress made in the field of SBTs over the last 10 years, starting from the operating principles, materials evolution, and processing developments. Depending on the types of stimuli such as electrical, optical, and mechanical stresses, various fields of applications from conventional digital logic circuits to sensory technologies are highlighted. Finally, more advanced applications toward beyond-Moore electronics are discussed, featuring recent advancements in neuromorphic devices based on SBTs. [ABSTRACT FROM AUTHOR]

In this article, MEMS-based logic gates such as OR, AND, NOT, NOR, and NAND gates with functionalities similar to the electronic digital devices are designed and simulated. The key feature of these logic devices is that the mechanical cantilever structure of the basic piezo-actuator is adapted to operate like a particular digital logic gate based on the digital inputs. Complete analytical modelling for a single piezo-actuator with a correlation between its out-of-plane tip deflection with applied voltage is obtained. The proposed digital logic devices are further validated through simulation using the MEMS CAD tool CoventorWare. [ABSTRACT FROM AUTHOR]

Standard electronic computing based on nanoelectronics and logic gates has upended our lives in a profound way. However, suffering from, both, Moore's law and Joule's law, further development of logic devices based solely on electricity has gradually stuck in the mire. All‐optical logic devices are believed to be a potential solution for such a problem. This work proposes an all‐optical digital logical system (AODLS) based on unidirectional (one‐way propagation) modes in the microwave regime. In a Y‐shaped module of the AODLS, the basic seven logic gates, including OR, AND, NOT, NOR, NAND, XOR, and XNOR gates, are achieved for continuous broadband operation relying on the existence of unidirectional electromagnetic signals. Extremely large extinction and contrast ratios are found in these logic gates. The idea of "negative logic" is used in designing the AODLS. Moreover, the authors further demonstrate that the AODLS can be assembled to multi‐input and/or multi‐output logical functionalities, which is promising for parallel computation. Besides, numerical simulations perfectly fit with and corroborate the theoretical analyses presented here. The low‐loss, broadband, and robust characteristics of this system are outlined and studied in some detail. The AODLS consisting of unidirectional structures may open a new route for all‐optical calculation and integrated optical circuits. [ABSTRACT FROM AUTHOR]

Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has been known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology has been recognized as a suitable replacement for CMOS technology due to its excellent potential in developing designs with low-power consumption, high speed, and high density. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. As the main unit in logic circuits and digital arithmetic, adders play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and, due to its remarkable features, can be useful to reach circuits with the minimum required area and power consumption. Therefore, this study recommends a new design for RCA in QCA technology to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner-E version 2.0.3 as a well-known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count compared to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan. [ABSTRACT FROM AUTHOR]

Nano and microelectromechanical relays can be used in lieu of transistors to build digital integrated circuits that can operate with zero leakage current at high operating temperatures and radiation levels. Four‐terminal (4‐T) relays facilitate efficient logic circuits with greatly reduced device counts compared to three‐terminal (3‐T) relay implementations. Existing 4‐T relays, however, require two moving contacts to simultaneously land on two stationary electrodes, which can adversely impact reliability, or have complex out‐of‐plane fabrication methods that can reduce yield and increase cost while having poor scalability. In this work an in‐plane four‐terminal relay with a single moving contact is demonstrated for the first time, through successful fabrication and characterization of prototypes with a critical dimension of 1.5 µm. Body biasing is shown to reduce the pull‐in voltage of this 4‐T relay compared to a 3‐T relay with the same architecture and footprint. The potential of the 4‐T relay to build efficient logic circuits is demonstrated by fabricating and characterizing a 1‐to‐2 demultiplexer (DEMUX) circuit using only two devices, a saving of eight devices over a 3‐T relay implementation. [ABSTRACT FROM AUTHOR]

A number of arithmetic operations and applications use digital logic circuits as their primary building blocks, to operate with high reliability and precision. The multiplier is the core part of most arithmetic designs. The trend of imprecise multiplier has gained visibility in recent years, especially for image processing applications. Most of the multiplier designs use a compressor in the dot product reduction. In recent years, researchers have focused on designing imprecise, or approximate compressor to reduce design complexity while maintaining a low error rate. For higher bit multiplication, the design of a higher-order compressor is required. Using Karnaugh map (K-map) and truth table for approximation is a challenging task for the higher-order compressor. To address this issue, a scalable compressor with reasonable approximation using counter-based comparison methods is designed in this paper. The simulation results used with scalable compressors are compared with the existing 8 × 8 and 16 × 16 multipliers. These approximate circuits show significant improvement in the efficiency of multimedia signal processing, leading to better efficiency in terms of 30% area, 25% power, 20% delay, mean error distance (MED), error distance (ED), and normalized error distance (NED). The proposed method is applied in image multiplications for image contrast enhancement application. The peak signal-to-noise ratio (PSNR) is then determined and compared to other existing work. [ABSTRACT FROM AUTHOR]

With the advent of big data, multi‐valued logic computing becomes an indispensable technology in the field of new micro‐electronic devices. As a new concept attracting more attention in recent years, anti‐ambipolar behavior shows its application potential in digital electronic and logic circuits. Here, the anti‐ambipolar transistors (AATs) based on metal–WSe2–metal configuration with dual contact barriers is fabricated. Under light illumination, the photocurrent as function of gate voltage exhibits anti‐ambipolar behavior with a distinct peak which can be varied with incident light power. The appearance of anti‐ambipolar transport is attributed to both contact barrier and photo‐excited carriers. The variation of the Fermi level in WSe2 regulated by gate voltage plays a key role in altering the dominant transport mechanism of the carrier type. This work proposes a new device concept that the photocarrier and barrier can induce an anti‐ambipolar characteristic, guiding the new direction for the multi‐valued logic/digital electronic applications. [ABSTRACT FROM AUTHOR]

Graphene is considered a promising material because of the novel functionalities associated with its outstanding charge transport properties. However, because graphene has no bandgap, its electrical conductivity cannot be controlled as in semiconductors, at present. Although many attempts have been made to achieve a bandgap opening in graphene, a meaningful bandgap opening for p -type field-effect-transistors (FETs) still remains a challenge. In this study, boron-doping in transfer-free monolayer graphene was successfully demonstrated for digital logic devices. Our approach is highly versatile, as it allows the fabrication of p -type single-crystal graphene FETs having a mobility of ∼290 cm2V−1s−1, an on/off ratio of 1.9 × 105, and a subthreshold swing of 70 mVdec−1. The scalability and versatility of this transfer-free approach for the fabrication of p -type graphene FETs pave the way for high-performance p -type graphene-based digital logic circuits. A scalable direct-growth approach to the fabrication of p- type graphene FETs, which manifest cutting-edge performance is demonstrated for the large-scale complementary integration of p -type graphene-based circuit for digital logic device applications. [Display omitted] [ABSTRACT FROM AUTHOR]

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows $>5\times $ reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself. [ABSTRACT FROM AUTHOR]

This article presents the first keyword spotting (KWS) IC that uses a ring-oscillator-based time-domain processing technique for its analog feature extractor (FEx). Its extensive usage of time-encoding schemes allows the analog audio signal to be processed in a fully time-domain manner except for the voltage-to-time conversion stage of the analog front end. Benefiting from fundamental building blocks based on digital logic gates, it offers better technology scalability compared to conventional voltage-domain designs. Fabricated in a 65-nm CMOS process, the prototyped KWS IC occupies 2.03 mm 2 and dissipates 23- $\mu \text{W}$ power consumption, including analog FEx and digital neural network classifier. The 16-channel time-domain FEx achieves a 54.89-dB dynamic range for 16-ms frame shift size while consuming 9.3 $\mu \text{W}$. The measurement result verifies that the proposed IC performs a 12-class KWS task on the Google Speech Command dataset (GSCD) with >86% accuracy and 12.4-ms latency. [ABSTRACT FROM AUTHOR]

This paper proposes a C/X/Ku/K band 6-bit digital step attenuator (DSA) which employs a variety of improved attenuation cells to achieve a wide bandwidth, stable amplitude variation, stable phase variation, and small area. In this paper, the improved T-type, π-type, and switched-path type topologies are analyzed theoretically and applied to different attenuation values to achieve the optimal attenuator performance. In addition, in order to reduce the complexity and to improve the stability of the overall radar system, the logic control circuit is integrated in the DSA chip in this paper. Finally, the proposed attenuator is implemented in 0.15μm GaAs technology, which has a maximum attenuation range of 31.5 dB with 0.5 dB steps. The proposed DSA exhibits a root-mean-square (RMS) attenuation error of less than 0.15 dB and an RMS phase error of less than 3°, at 4–24 GHz. The insertion loss (IL) and the area of the DSA are 4.3–4.5 dB and 1.5 mm × 0.4 mm, respectively. Benefiting from the improvements of the attenuation cells and the characteristic of GaAs technology with strong resistance to radiation and power processing capability, the proposed DSA is suitable for spaceborne radar systems. [ABSTRACT FROM AUTHOR]

Organic electronic circuits based on organic electrochemical transistors (OECTs) are attracting great attention due to their printability, flexibility, and low voltage operation. Inverters are the building blocks of digital logic circuits (e.g., NAND gates) and analog circuits (e.g., amplifiers). However, utilizing OECTs in electronic logic circuits is challenging due to the resulting low voltage gain and low output voltage levels. Hence, inverters capable of operating at relatively low supply voltages, yet offering high voltage gain and larger output voltage windows than the respective input voltage window are desired. Herein, inverters realized from poly(3,4‐ethylenedioxythiophene):polystyrene sulfonate‐based OECTs are designed and explored, resulting in logic inverters exhibiting high voltage gains, enlarged output voltage windows, and tunable switching points. The inverter designs are based on multiple screen‐printed OECTs and a resistor ladder, where one OECT is the driving transistor while one or two additional OECTs are used as variable resistors in the resistor ladder. The inverters' performances are investigated in terms of voltage gain, output voltage levels, and switching point. Inverters, operating at +/−2.5 V supply voltage and an input voltage window of 1 V, that can achieve an output voltage window with ∼110% increment and a voltage gain up to 42 are demonstrated. [ABSTRACT FROM AUTHOR]

Compared with the two-valued memristor, the three-valued memristor has higher data density, richer dynamic characteristics, and more potential in digital logic and chaotic circuit. The present model of the three-valued memristor has several limitations. It doesn't perform well enough in three-valued applications since its hysteresis loops are linear and asymmetric. The mathematical model of the three-valued memristor with nonlinear and symmetric hysteresis loops is proposed in this research. To further investigate the electrical characteristics of the three-valued memristor, a circuit emulator of the memristor has been constructed with fundamental components. Multisim simulations and hardware experiments demonstrate the emulator's effectiveness. The three-valued memristor application in chaotic circuits shows fascinating dynamic characteristics and lays the foundation for future research. • The mathematical model of the three-valued memristor with nonlinear and symmetric hysteresis loops is proposed in this paper. • A circuit emulator of the three-valued memristor is proposed and verified using hardware and software. • The three-valued memristor application in chaotic circuits shows fascinating dynamic characteristics. [ABSTRACT FROM AUTHOR]

Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and higher device density. One of the most important and widely used circuits in digital logic calculations is the full adder (FA) circuit, which actually creates the problem of finding its optimal design and increasing performance. In this paper, we designed and implemented two new FA circuits in QCA technology and then implemented ripple carry adder (RCA) circuits. The proposed FAs and RCAs showed excellent performance in terms of QCA evaluation parameters, especially in cost and cost function, compared to the other reported designs. The proposed adders' approach was 46.43% more efficient than the best-known design, and the reason for this superiority was due to the coplanar form, without crossovers and inverter gates in the designs. [ABSTRACT FROM AUTHOR]

In very large-scale integration (VLSI) circuits, a partial of energy lost leads to information loss in irreversible computing because, in conventional combinatorial circuits, each bit of information generates heat and power consumption, thus resulting in energy dissipation. When information is lost in conventional circuits, it will not be recoverable, as a result, the circuits are provided based on the reversible logic and according to reversible gates for data retrieval. Since comparators are one of the basic building blocks in digital logic design, in which they compare two numbers, the aim of this research is to design a 1-bit comparator building block based on reversible logic and implement it in the QCA with the minimum cell consumption, less occupied area, and lower latency, as well as to design it in a single layer. The proposed 1-bit reversible comparator is denser, cost-effective, and more efficient in quantum cost, power dissipation, and the main QCA parameters than that of previous works. [ABSTRACT FROM AUTHOR]

As the semiconductor industry strives for downsizing and high speed, it is confronted with increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and low-power consumption. We introduced an optimal design of content addressable memory (CAM) memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the first time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts. [ABSTRACT FROM AUTHOR]

The Si-CMOS based technology has been dominating the digital design for more than 40 years. However. nuinerous device non-idealities that cause critical reliability issues in Si-CMOS designs are introduced at 32nm technology nodes and beyond. Continued scaling gives rise to short channel effects that diminish the controllability of the gate. Other factors like significantly increased leakage power dissipation, larger process variation and other technological and economical challenges arise with continued Si-CMOS scaling. Therefore, traditional Si-CMOS technology has reached a point where further advancement in terms of speed and size is becoming extremely challenging as devices scale down into the deep submicron region. Graphene Nano Ribbon Field Effect Transistor (GNRFET) is an einerging technology that has received a lot of attention in recent years due to its high carrier mobility for ballistic transpoit, compatibility with high k dielectrics, high carrier velocity to have abrupt switching, and good thermal conductivity. In this work, various GNRFET-based conventional two-input digital logic gates are implemented. The different gate designs are analyzed in terms of speed of operation, leakage power dissipation. and energy consumption using HSPICE. The results are then compared to the Si-CMOS implementations of these gates at the saine future size and nominal voltage. Simulation results demonstrate that GNRFET could be potential emerging energy efficient electronic device at semiconductor industry for future digital systems design. [ABSTRACT FROM AUTHOR]

The conventional CMOS scaling trend faces device scaling limitations, interconnect bottleneck, and signal integrity issues due to crosstalk, which is the unwanted interference of signals between neighboring metal lines. Traditional computing circuits always try to reduce the crosstalk noise by applying various circuit and layout techniques. In contrast, Crosstalk computing is a new computing framework that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. In this paper, we present a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model for large-scale design. It also performs a comparison study between Crosstalk circuits and existing CMOS-based approaches. The ability to design a wide range of logic circuits (basic and complex logics) and programmable gates compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation results designed at 7 nm show 3.4x improvement density, 62% reduction in Energy-Delay-Product (EDP), and 34.5% improvement in performance compared to counterpart implementation in CMOS circuit style. • Interference based radically new concept to compute logic for digital Integrated Circuits. • Fabricated a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65 nm technology. • A detailed methodology for large scale circuit implementation and discussed signal integrity aspects of Crosstalk Computing. • Presented a host of circuit styles for quick adaptation of Crosstalk Computing. • A unique hardware-level programmability feature allowing run-time reconfiguration and enabling security, and fault resilience. [ABSTRACT FROM AUTHOR]

This paper describes the fabrication of digital logic circuits comprising resistors and diodes made from protein complexes and wired together using printed liquid metal electrodes. These resistors and diodes exhibit temperature-independent charge-transport over a distance of approximately 10 nm and require no encapsulation or special handling. The function of the protein complexes is determined entirely by self-assembly. When induced to self-assembly into anisotropic monolayers, the collective action of the aligned dipole moments increases the electrical conductivity of the ensemble in one direction and decreases it in the other. When induced to self-assemble into isotropic monolayers, the dipole moments are randomized and the electrical conductivity is approximately equal in both directions. We demonstrate the robustness and utility of these all-protein logic circuits by constructing pulse modulators based on AND and OR logic gates that function nearly identically to simulated circuits. These results show that digital circuits with useful functionality can be derived from readily obtainable biomolecules using simple, straightforward fabrication techniques that exploit molecular self-assembly, realizing one of the primary goals of molecular electronics. Proteins are promising molecular materials for next-generation electronic devices. Here, the authors fabricated printable digital logic circuits comprising resistors and diodes from self-assembled photosystem I complexes that enable pulse modulation. [ABSTRACT FROM AUTHOR]

Memristor has been widely explored in digital logic circuits where most of the works are focused on basic gate circuits, such as OR and AND logic gates or full adders while few involve flip‐flops. In fact, flip‐flops are also basic logic units with memory function for various digital systems. In this paper, we present circuit designs for Delay (D) and Jump‐Key (JK) flip‐flops based on memristor ratioed logic (MRL). The proposed circuit for D flip‐flop only needs five memristors and one NMOS transistor, and circuit for JK flip‐flop needs seven memristors and two NMOS transistors. Furthermore, the proposed circuits have been mapped into a hybrid memristor‐CMOS crossbar array. Compared with previous approaches, the quantity of MOSFET for each proposed circuit has been greatly reduced. Thus, the proposed designs have achieved simpler structure, smaller area, and lower power consumption benefiting from the memristor's nanoscale size and low power consumption. The circuit verification based on PSpice simulation is also provided. [ABSTRACT FROM AUTHOR]

We investigate the circuit performance of the junctionless nanowire transistor. We have demonstrated pass transistor-based logic gates using the junctionless transistor. Pass transistor-based basic logic gates: AND, OR, XOR are designed using only the n-type junctionless nanowire transistor with HfO2 gate dielectric. Simulations of these circuits have been studied and analyzed under a mixed-mode environment. Outcomes of the analysis show that 3D dual gate junctionless nanowire transistor with 20 nm gate length well performed for pass transistor logic. In addition, a junctionless nanowire transistor-made multiplexer has also been studied and found to perform well. A high-k gate dielectric was used for all junctionless transistors as the higher k value improves the device characteristics and circuit performances. Our study also shows that the junctionless nanowire transistor-based pass transistor logics for digital circuit perform well. [ABSTRACT FROM AUTHOR]

Quantum dot-cellular automata (QCA) technology has recently emerged as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents and implements two 1-bit QCA-based comparator designs. The proposed QCA implementations are compact, require only a single layer and are less complex compared to recently reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvements compared to their existing counterparts in terms of the number of QCA cells and occupational area requirements in addition to cost and efficient complexity values. Furthermore, all of the proposed structures are dissipating extremely low energy values. Thus, the proposed QCA-based comparators can be viewed as viable options for low power digital applications. [ABSTRACT FROM AUTHOR]

This paper presents a general modeling method for threshold-type multivalued memristors. Through this memristor modeling method, it is very simple to establish threshold-type memristor behavior models with different numbers of memristance elements, and these models are verified by numerical MATLAB simulations. A corresponding circuit-level SPICE model of the ternary memristor behavior model is developed and simulated in LTspice, shown to be consistent with the MATLAB results. Finally, the SPICE model is used to design the AND gate, OR gate, and three NOT gates of ternary state-based logic, and the effectiveness of the circuit is proved by LTSpice simulation. [ABSTRACT FROM AUTHOR]

This paper proposes three modified memristor ratioed logic (MRL) gates: NOT, NOR and A AND (NOR B) (i.e., A · B ¯ ), each of which only needs 1 memristor and 1 NMOS. Based on the modified MRL gates, we design some combinational logic circuits, including 1-bit comparator, 3-bit binary encoder, 3-bit binary decoder and 4:1 multiplexer. Furthermore, an improved multifunctional logic module is proposed, which contains one NMOS transistor and five memristors, and can implement AND, OR and XOR logic operations. Using this multifunctional logic module, a 4-bit comparator and a 1-bit full adder are designed. Finally, the proposed combinational logic circuits are verified by LTSPICE simulations. Compared with other memristor-based logic circuits and the traditional CMOS technology, the proposed logic circuits have made great progress in reducing delay, power consumption and the number of transistors. [ABSTRACT FROM AUTHOR]

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Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a new low-voltage low-power circuit is introduced for implementing CMOS-based basic logic functions using the analog current-mode techniques. The logic functions have been realized by using their expansion in Power Series representation, a Squaring circuit and a Geometric Mean circuit. To illustrate the proposed method, simultaneous realization of the basic logic functions NOT, OR, AND, XOR, NOR, NAND and XNOR in a single circuit is considered. Furthermore, these functions have been used to realize various combinational circuits including full-adder, full-subtractor, etc. SPICE simulation results, obtained with 1.5-V supply, are included. [ABSTRACT FROM AUTHOR]

Here we report a type of dynamic effect that is at the core of the so called "counterfactual computation" and especially "counterfactual communication" quantum effects that have generated a lot of interest recently. The basic feature of these counterfactual setups is the fact that particles seem to be affected by actions that take place in locations where they never (more precisely, only with infinitesimally small probability) enter. Specifically, the communication/computation takes place without the quantum particles that are supposed to be the information carriers travelling through the communication channel or entering the logic gates of the computer. Here we show that something far more subtle is taking place: It is not necessary for the particle to enter the region where the controlling action takes place; it is enough for the controlled property of the particle, (i.e., the property that is being controlled by actions in the control region), to enter that region. The presence of the controlled property, without the particle itself, is possible via a quantum Cheshire Cat type effect in which a property can be disembodied from the particle that possesses it. At the same time, we generalize the quantum Cheshire Cat effect to dynamical settings, in which the property that is "disembodied" from the particle possessing it propagates in space, and leads to a flux of "disembodied" conserved quantities. In quantum mechanics, counterfactual behaviours are generally associated with particles being affected by events taking place where they can't be found. Here, the authors consider extended quantum Cheshire cat scenarios where a particle can be influenced in regions where only its disembodied property has entered. [ABSTRACT FROM AUTHOR]

Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications. [ABSTRACT FROM AUTHOR]

In this paper, a behavioral SPICE memristor model for digital logic implementation is presented and demonstrated in LTSpice. We show binarized state switching and voltage thresholding in the model, which are both important features in practical digital systems. The use of this SPICE model is straightforward and intuitive because almost all parameters in the model can be changed according to the application, including the threshold voltage and the memristance. The LTSpice circuit simulation shows the same characteristics as the original MATLAB numerical implementation, which means that the circuit-level SPICE model can be integrated with other designs. Three types of memristor digital logic circuits are simulated with the LTSpice model with positive results, which proves that the behavioral memristor model has potential application in digital system design. [ABSTRACT FROM AUTHOR]

The proposal of compute-in-memory (CIM) is a breakthrough for the traditional von Neumann architecture to achieve efficient computing research. This architecture has unique advantages in the computing field thanks to supporting multi-line computing and without data transmission between processor and memory. In this paper, an in-memory computing structure based on 9T SRAM unit is proposed, which can both operate on memory and computing mode. Compared with the previous works, thanks to the redundant units, the computational structure can directly complete XNOR operations and storage of the whole SRAM array in only one cycle, without the need of extra digital logic circuits (such as AND, OR circuits), which can significantly improve the parallelism of the computation. Meanwhile, the architecture can map the XNOR logical operation into the binary multiplication, and then add up the one-bit multiplication results through the addition tree, thus realizing the binary convolution calculation. A 64-bit × 64-bit (4 Kb) SRAM array with the proposed scheme is designed and simulated in 55 nm CMOS technology. Simulation results show excellent stability and write yields in SRAM memory mode at an operating frequency of 200 MHz. In computing mode, the SRAM array power consumption for logical operation is 52.68 fJ/bit at 1.2 V supply voltage. At a minimum supply voltage of 0.8 V, the power consumption is only 5.58 fJ/bit, with an energy efficiency 179.21 TOPS/W. [ABSTRACT FROM AUTHOR]

Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of two circuits; however, this requires human effort and expertise to write multiple output functions and carry out interactive proof of their equivalence. In this paper, we (1) define two simple, one formal and the other informal, gate-level hardware description languages, (2) design and develop a formal automatic combinational circuit equivalence checker (CoCEC) tool, and (3) test and evaluate our tool. The tool CoCEC is based on human-assisted theorem prover Coq, yet it checks the equivalence of circuit descriptions purely automatically through a human-friendly user interface. It either returns a machine-readable proof (term) of circuits' equivalence or a counterexample of their inequality. The interface enables users to enter or load two circuit descriptions written in an easy and natural style. It automatically proves, in few seconds, the equivalence of circuits with as many as 45 variables (3.5 × 10 13 states). CoCEC has a mathematical foundation, and it is reliable, quick, and easy to use. The tool is intended to be used by digital logic circuit designers, logicians, students, and faculty during the digital logic design course. [ABSTRACT FROM AUTHOR]

Integrated circuits utilize networked logic gates to compute Boolean logic operations that are the foundation of modern computation and electronics. With the emergence of flexible electronic materials and devices, an opportunity exists to formulate digital logic from compliant, conductive materials. Here, we introduce a general method of leveraging cellular, mechanical metamaterials composed of conductive polymers to realize all digital logic gates and gate assemblies. We establish a method for applying conductive polymer networks to metamaterial constituents and correlate mechanical buckling modes with network connectivity. With this foundation, each of the conventional logic gates is realized in an equivalent mechanical metamaterial, leading to soft, conductive matter that thinks about applied mechanical stress. These findings may advance the growing fields of soft robotics and smart mechanical matter, and may be leveraged across length scales and physics. A method to cultivate decision-making in soft materials would provide a key step to autonomous engineered matter. Here, the authors report a class of conductive polymer-based mechanical metamaterials that process information by digital logic and permit logic gate assembly. [ABSTRACT FROM AUTHOR]

Micro-electro-mechanical relays with multiple gate electrodes (i.e., multiple input voltage signals), operated with a tunable body bias voltage, are investigated for more compact and energy-efficient implementation of digital logic circuits. Specifically, a relay design with three gate electrodes of equal area is demonstrated to be capable of performing different digital logic functions for the same input operating voltage (${V} _{\textbf {DD}}$), by adjusting the body bias voltage. Since the lower limit for ${V} _{\textbf {DD}}$ is equal to the switching hysteresis voltage (${V} _{\textbf {H}}$), the magnitude of ${V} _{\textbf {H}}$ is investigated for different combinations of transitioning input voltage signals. It is found that ${V} _{\textbf {H}}$ is larger for fewer transitioning input voltage signals, i.e., reduced effective actuation area of the switching input voltage signal. This can set a practical upper limit for the number of independent gates in a single relay. [ABSTRACT FROM AUTHOR]

The explosive demands of storage capacity and the von Neumann bottleneck of modern computer architectures trigger many innovations in information technology. Amongst them, nonvolatile spintronics attract considerable attentions for which can embed the computation capability into memory, enable neuromorphic, and probabilistic computing. These exciting progresses typically rely on the manipulation of the relative magnetization orientations of two magnetic layers. By extending to 3D spintronic architectures made of multiple magnetic layers (n), the exponentially increased 2n magnetic states can provide ample opportunities for implementing novel spintronic functionalities. Here, through building perpendicularly magnetized 3D spin‐orbitronic architectures – [Pt/Fe1−xTbx/Si3N4]n multilayers, it is demonstrated the electrical programing of 2n memory states via current‐induced spin–orbit torques (SOTs), and the accompanied reconfigurable multifunction in‐memory logic features in a single four‐terminal Hall device. Further, an electrical readout of these 2n states, together with the implementation of Boolean logic gates and digital circuitry such as 2–4 and 3–8 decoders, are successfully conducted. More complex logic circuits are also envisioned. The experiments thus substantiate 3D spin‐orbitronic structures as a promising platform for exponentially boosting the storage capacity and accommodating in‐memory computing that can be important for promoting the emerging 3D nanospintronics. [ABSTRACT FROM AUTHOR]

The complementary metal oxide semiconductor technology, CMOS, is reaching its physical limitations, as the transistors' feature size decreases. A promising alternative is the nanomagnetic logic technology (NML), a paradigm of field-coupled nanocomputing. This technology applies single domain nanomagnets to implement digital logic with switching energies that are orders of magnitude lower than a CMOS transistor due to the complete absence of static energy dissipation. When designing nanomagnetic circuitry, several challenges arise, such as the design of a clocking system able to avoid signal disruption due to the thermal noise effect. In this paper, we compare four NML clocking schemes: BANCS, USE, RES, and 2DDWave by analyzing scalability and area overhead of combinational and sequential circuits. [ABSTRACT FROM AUTHOR]

Body-biased micro-electro-mechanical (MEM) relays previously have been demonstrated to be a promising alternative to transistors for ultra-low voltage digital logic applications. A basic requirement for reliable relay-based circuit operation is suitably low and stable relay ON-state resistance ($R_{\mathbf {ON}}$). In this work, the effect of body biasing on $\text{R}_{\mathbf {ON}}$ is investigated for relays of different contact designs. It is found that a single direct contact design not only provides for the smallest hysteresis voltage but also the smallest $R_{\mathbf {ON}}$ , making it the most suitable for low voltage applications. Body-biased operation is found to degrade $R_{\mathbf {ON}}$ stability over many ON/OFF switching cycles, however, due to a reduction in contact velocity. [2020-0297] [ABSTRACT FROM AUTHOR]

Spin-devices are switched by flipping spins without moving charge in space and this can lead to ultra-low-energy switching replacing traditional transistors in beyond Moore's law era. In particular, the electric field-induced magnetization switching has emerged to be an energy-efficient paradigm. Here, we review the recent developments on ultra-low-energy, area-efficient, and fast spin-devices using multiferroic magnetoelectric composites. It is shown that both digital logic gates and analog computing with transistor-like high-gain region in the input-output characteristics of multiferroic composites are feasible. We also review the equivalent spin-circuit representation of spin-devices by considering spin potential and spin current similar to the charge-based counterparts using Kirchhoff's voltage/current laws, which is necessary for the development of large-scale circuits. We review the spin-circuit representation of spin pumping, which happens anyway when there is a material adjacent to a rotating magnetization and therefore it is particularly necessary to be incorporated in device modeling. Such representation is also useful for understanding and proposing experiments. In spin-circuit representation, spin diffusion length is an important parameter and it is shown that a thickness-dependent spin diffusion length reflecting Elliott–Yafet spin relaxation mechanism in platinum is necessary to match the experimental results. [ABSTRACT FROM AUTHOR]