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Metalenses, planar lenses realized by placing subwavelength nanostructures that locally impart lenslike phase shifts to the incident light, are promising as a replacement for refractive optics for their ultrathin, lightweight, and tailorable characteristics, especially for applications where payload is of significant importance. However, the requirement of fabricating up to billions of subwavelength structures for centimeter-scale metalenses can constrain size-scalability and mass-production for large lenses. In this Letter, we demonstrate a centimeter-scale, all-glass metalens capable of focusing and imaging at visible wavelength, using deep-ultraviolet (DUV) projection stepper lithography. Here, we show size-scalability and potential for mass-production by fabricating 45 metalenses of 1 cm diameter on a 4 in. fused-silica wafer. The lenses show diffraction-limited focusing behavior for any homogeneously polarized incidence at visible wavelengths. The metalens' performance is quantified by the Strehl ratio and the modulation transfer function (MTF), which are then compared with commercial refractive spherical and aspherical singlet lenses of similar size and focal length. We further explore the imaging capabilities of our metalens using a color-pixel sCMOS camera and scanning-imaging techniques, demonstrating potential applications for virtual reality (VR) devices or biological imaging techniques.

This presentation discusses a collaborative effort of two Fraunhofer institutes to develop a lithography model that simulates the fabrication of blazed gratings using grayscale lithography. The model is calibrated with experimental data of blazed grating profiles. The complete process of modelling and calibration has been performed using the Research and Development lithography simulator Dr.LiTHO. To emulate the grayscale exposure of blazed gratings in a LED-based micro-image stepper with Dr.LiTHO a thin mask with a linear variation of the mask transmission and corresponding distribution of exposure dose was used. The resulting photoresist profiles are obtained with a standard model for Diazonaphthoquinone (DNQ) photoresistas. The calibration of simulated and experimental profile data of blazed gratings is performed using Dr.LiTHO’s inbuilt optimizer - Pythmea. The difference between experimental and simulated profile shapes is expressed by an areaFit. Minimization of this areaFit versus photoresist parameters and correlation analysis help to identify the most appropriate model parameters. The extendibility of the model to larger ranges of blazed grating pitches and grayscale exposures of other microstructures such as arrays of microlenses is discussed. Selected examples demonstrate the application of the model for the optimization of dose distributions for grayscale exposures to improve obtained profile shapes.

The fan-out packaging (FOP) catches the general interest of microelectronics packaging, which has several advantages such as smaller formfactor, more efficient heat dissipation, better signal integrity, and higher reliability, matching with the requirements of advanced consumer electronics. It is, however, the reconstituted die shift and the carrier warpage have yet to overcome. These critical issues tighten the lithography overlay tolerance. Warpage issue can be controlled by suitable carrier selection. On the other hand, die shift can be well managed when following factors are taken into account: (1) carrier coefficient of thermal expansion (CTE) and thickness; (2) die/mold thickness and fan-out ratio; (3) shrinkage/expansion of involved materials. Fan-out panel level packaging (FOPLP) is considered a cost-effective solution owing to higher carrier usage ratio. However, the aforementioned challenges are aggravated by the fact that the panel is not centrosymmetric and has larger die placement area with respect to the traditional wafer form carrier. Mask-less laser direct imaging (LDI) lithography technology has been adopted as a potential solution to overcome large die shift by relaxing lithography overlay constraint. But the low throughput of LDI undermines the cost benefit of PLP. In this paper, we implement an off-line mapping system to collect and analyze the die shifts on a panel with size of 510mm ×515mm. The mapping data are subsequently introduced into a stepper to guide the PLP exposure process and achieve more than double the throughput. With proper die shift compensation, on top of the integrated mapping/exposure system, the throughput by using the full reticle exposure can be further enhanced to 20 times than that of die-by-die exposure. The integrated system can be utilized to predict lithography yield under the combination of different exposure field size and different overlay spec. By using the same system, we achieve a lithography yield of 99.9% within ±12um lithography overlay spec at the maximum field size.

Growth in the usage of heterogenous integration and chiplets-based designs in modern advanced packages for leading applications like AI and HPC is driving the need for very large chip sizes that exceed the dimensions of a single back-end stepper exposure field. Simultaneously, these advanced designs are requiring 1.0 micrometer or smaller linewidth connections in their redistribution layers to meet their package I/O density and bandwidth performance requirements. In this paper, we demonstrate a process for 1.0 and 0.8 micrometer Cu lines across a two-field stitch boundary, and tests indicate negligible impact of the stitch on electrical resistance or leakage current. We show that this process is viable to support fine resolution features for large area packages.

We have developed a cross-line process to fabricate sub-micron Josephson tunnel junctions using i-line stepper lithography and RIE etching. In the process, step sidewall was introduced to achieve the passivation of the junction utilizing the Al-AlOx layer in situ and a self-aligned insulating layer. The effect of junction area shrinkage in the process enables one to form smaller junction with dimension even at or below lithography limitation. Josephson junction with minimum area of 0.7 × 0.35 μm2 was obtained. The junction with gap current density of 1 kA/cm2 demonstrated high junction quality with a gap voltage of 2.8 mV and small sub-gap leakage current. The cross-line process for sub-micron junctions could be used in SQUID or other superconducting circuits where a low capacitance is desired. To verify the process, a SQUID magnetometer was also presented.

This paper presents the latest advances in photolithography technologies to enable scaling of package redistribution layer (RDL) toward critical dimensions (CD) of $1 ~\mu \text{m}$ and below. High-bandwidth memory channels require not only fine pitch but also low-trace-delay RDL. High-aspect-ratio (AR) traces enable lower delays, and the photolithographic advances to achieve such traces are demonstrated on panel-based glass substrates for packages with low cost, high input/output (I/O) density, high bandwidth, and large body size. CD of 0.9- $\mu \text{m}$ line and space with an AR of 5.5 was successfully demonstrated using a low-numerical aperture (NA = 0.16) $1 \times$ i-line projection stepper tool with a novel chemically amplified plating photoresist. The 1- $\mu \text{m}$ lithography technology is a must for high-density RDL to enable 2.5-D interposer and embedded fan-out package substrates. These architectures can achieve I/O densities of 500 IOs/mm/layer. The resistance of the trace with an AR of 5 is five times lower than a trace with an AR of 1. This technological advance will greatly reduce the signal propagation loss and increase the data rate of the RDL traces. The combination of high density and high data rate will greatly increase the system interconnect bandwidth. Furthermore, low-NA stepper with a large exposure area will enable the fabrication of large-body-size interposers at low cost. This paper analyzes the relationship between trace width resolution ( $w$ ), depth of focus, and materials to conclude that it is feasible to fill the gap between semiconductor back-end-of-line and package substrate RDL technologies. The final section discusses the issues in process development of lithography for multilayer fine-line RDLs.

Single nanowires (NWs) have a broad range of applications in nanoelectronics, nanomechanics, and nanophotonics, but, to date, no technique can produce single sub-20 nm wide NWs with electrical connections in a scalable fashion. In this work, we combine conventional optical and crack lithographies to generate single NW devices with controllable and predictable dimensions and placement and with individual electrical contacts to the NWs. We demonstrate NWs made of gold, platinum, palladium, tungsten, tin, and metal oxides. We have used conventional i-line stepper lithography with a nominal resolution of 365 nm to define crack lithography structures in a shadow mask for large-scale manufacturing of sub-20 nm wide NWs, which is a 20-fold improvement over the resolution that is possible with the utilized stepper lithography. Overall, the proposed method represents an effective approach to generate single NW devices with useful applications in electrochemistry, photonics, and gas- and biosensing.

Intracellular delivery with a nanoneedle is a versatile method of injecting various types of materials into a single cell. A single hollow needle limits the throughput of cellular delivery. This study aims to develop an array of hollow nanoneedles suitable for massively parallel delivery and mass production. The fabrication of hollow nanoneedle structures by stepper lithography looks promising, but a method for the fabrication has remained unclear. We patterned the tips of nanoneedles by i-line stepper lithography and fabricated a hollow nanoneedle array. We used silicon and silicon-on-insulator wafers and established a process for controlling needle diameter, height, and pitch. Needle tips were produced on the front side and introduction channels were formed on the backside. A fluorescent DNA solution was transported by electrokinetic ejection through a fabricated nanoneedle array.

In making sensors require multiple processing by using different masks to accomplish, it needs reload and multiple aligning for a wafer in order to make a functional wafer, thus, the consuming for making mask are wasted, and used lamps toxic. In the study, a ULVLED stepper with Programmable LCoS or DLP as mask for multiple process wafer is proposed. By a programmable ultraviolet light-emitting diode (UVLED) array with a collimated lens as a transfer lens forms uniform source, to expose programmable LCoS or DLP as mask by using a 1 to 1 lithographic lens. Sensors and optical binary lens are easily made.

3D pixel sensors aimed at the upgrades of the ATLAS and CMS experiments at the High Luminosity LHC have small pixel size and pretty dense layouts. In addition, modified 3D designs with small pixel size and trenched electrodes in place of columnar electrodes are being developed to optimize the pixel timing performance in view of the LHCb upgrade. The fabrication of these advanced 3D pixels is challenging from the lithographical point of view. This motivated the use of stepper lithography at Fondazione Bruno Kessler in place of a standard mask aligner. The small minimum feature size and high alignment accuracy of stepper allow a good definition of the sensor geometries also in the most critical layouts, so that a higher fabrication yield can be obtained. In this paper, we will present the main design and technological issues and discuss their impact on the electrical characteristics of 3D pixel sensors of different geometries.

The resolution enhancement lithography assisted by chemical shrink (RELACS) is presented to increase the resolution of the i-line lithography. We have succeeded in developing an advanced i-line lithography process based on i-line stepper lithography and second-RELACS process. Moreover, the limit resolution of i-line lithography can be increased from 0.35 μm to 0.1 μm at the first time, and the wafer yield of GaN high electron mobility transistor (HEMT) with 3.1 mm gate width which has an Lg = 0.147 μm is 87.4 %. Besides, the second-RELACS process is applied to X-band GaN monolithic microwave integrated circuit power amplifier (MMIC PA), the resist width and gate length are about 0.15 μm and 0.2 μm. It is confirmed that the wafer yield of T gate with 6.8 mm gate width can be as high as 70.2 %. Comparing with the results of deep ultra-violet (DUV) lithography, the electrical and radio frequency (RF) characteristics of the GaN HEMTs fabricated with the second-RELACS process are stable.

In the next few years, advanced process technologies in advanced packaging fabs will migrate rapidly to reduction lithography to achieve 2/2 RDL and beyond. Reticle enhancement techniques, such as Optical Proximity Correction (OPC) may be required in multiple reticle layers to provide sufficient process latitude for high volume manufacturing. However, a challenge in the manufacturing of OPC reticles is the lack of a precise specifications for defect inspection with respect to the printability on wafers [1]. In this paper, the printability of reticle defects for 2/2 micrometers Redistribution Layer (RDL) design rule are studied via i-line resist process. The reticle defect printability is determined by considering the wafer process critical dimension (CD) variability. In the experiment, an i-line 2x reduction stepper with 0.1 NA imaging lens was used to expose the programmed defect reticle. The resist CD response to the reticle defect area is measured under a variety of process conditions, i.e., different exposure dose or focusThe programmed defect reticles consisted of both Clear and Dark Field polarities comprising of 2/2 design rules will be used for the printability study. Defects such as intrusions and protrusions at various sizes on RDL patterns, have been characterized. Defect disposition comparing reticle to designed programmed defects to those without will be shown as well as the impact of the defect on patterning performance. Finally, the allowable reticle defect requirement is assessed where the printable reticle defect size is tied to the wafer process specifications and the actual wafer process CD controllability. The influence of the reticle manufacturing processes on wafer patterning performance is examined. Through this comparison, insights into target specifications (MTT, CDU, defects) for advanced RDL reticles can be derived while balancing cost tradeoffs.

More-than-Moore approaches to improving system performance have been a hot topic for a decade, starting with 3D-integration using Through-Silicon Vias (TSV) and silicon interposers. Today, Heterogeneous Integration (HI) technologies including Fan-Out Wafer-Level Packaging (FOWLP) with fine Redistribution Layers (RDL) are promising technologies that can deliver benefits not possible with More-Moore scaling alone.Fan-Out devices are required to meet the demands of advanced Graphics Processing Unit (GPU) and Field-Programmable Gate Arrays (FPGA) that require wideband interconnection with memory for Artificial Intelligence (AI) and autonomous driving. Next-generation devices require submicron RDL and large die sizes to enable high-performance computing using GPU and FPGA designs.For large die-size devices, Fan-out Panel Level Packaging (FOPLP) can offer efficiency and cost advantages compared to FOWLP, however FOPLP poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first 500 mm panel size patterning exposure tool capable of submicron resolution.The new panel exposure tool is equipped with a wide-field projection optics that offer a wide image field (52 mm x 68 mm) and optimum 0.24 NA for sub-micron resolution and a newly developed panel handling system that handles up to 515 mm x 515 mm panels.Die-by-die focus and tilt compensation are necessary to realize submicron patterning and Canon’s panel exposure tools adopt a front-end i-line stepper, on-axis optical focus, tilt system for die-by-die focus and tilt measurement. Canon also developed a new panel stage that executes die-by-die focus and tilt compensation.Canon manufactured a debug tool and confirmed the new panel exposure tool advantages for submicron FOPLP high volume manufacturing and in this paper, we will report on the performance of the new submicron patterning panel exposure tool and will introduce technology innovations supporting advanced heterogeneous integration technologies. We will also discuss current and future FOPLP advantages and challenges and will report on FOPLP resolution performance related to slit coater performance, photoresist materials and the flatness of panel substrates.

Fifth Generation (5G) network and high speed/high frequency (HS/HF) technology is the key to setting higher transmission rates and improved connectivity but will require significant innovation from materials to enable the manufacturing and performance of future networks. Photoimageable Dielectrics (PID) are set to play a large role in the manufacturing of panel and wafer level packaging of 5G circuits, but PID materials and imaging mechanisms currently rely on chemistry with high dipole moments and heteroatoms which possess dielectric losses (Df) too high for 5G devices at desirable form factors. A newly developed polymer platform has been identified as a potential useful material for 5G PID, the new material possessing a low Df (0.004 at 30GHz) at a low curing temperature (under 200°C for one hour), self-priming adhesion to relevant substrates (silicon, copper, silicon nitride, polyimide), low moisture absorption, as well as a desirable solvent based developer: propylene glycol monomethyl ether acetate (PGMEA). Herein, targeting a 15 μm final film thickness, the effect of processing conditions on resolution, via shape and process window are described on a high numerical aperture (NA = 0.48) stepper, a low NA (0.1) stepper, and a Mask Aligner through different soft and post exposure bake conditions. High resolution (6 μm via) and high aspect ratio (2.5:1) can be achieved. Elements critical to the lithographic process including Bossung curves, bake conditions and tradeoffs in resolution versus desirable side-wall angle over different tools demonstrate processing surfaces towards the successful implementation of photodielectrics for 5G applications with stringent lithographic requirements.

Herman van Heek and Gijs Bouwhuis create the world’s first wafer stepper. Van Heek is the system architect; Bouwhuis develops the brilliant aligning principle that puts Dutch lithography on the global map in the decades that follow.

Accurate alignment between the cavities in cavity-SOI (c-SOI) wafers and lithography on the wafer surface is essential to advanced MEMS production. Existing alignment methods are well defined, but often require specialized equipment or costly software packages available only in professional manufacturing environments. It would be beneficial for the microfabrication world to be able to utilize standard alignment techniques and tools that are easily available also in smaller MEMS fabrication units and especially the majority of research facilities. Therefore, we demonstrate a feasible method for c-SOI wafer alignment using an ASML PAS5500/100 wafer stepper with standard software configuration by relocating ASML alignment markers towards wafer's edges and utilizing a terracing process to reveal them for alignment. Moreover, we characterize the magnitude and behavior of image offset errors that are introduced using this method. The offset error is found to be inversely proportional to the value of the coordinate in each axis, resulting in images being shifted towards the center of the wafer. The measured offset errors are

The Internet of Things (IOT), mobile devices, memory and automotive applications are major market drivers. These drivers require high performance, low cost, increased functionality and reliability (especially for automotive), 2.5D and 3D packaging solutions. Fan out panel level packaging (FOPLP) is one of the technologies that has the potential to meet these packaging requirements. FOPLP processes require the reconstitution of dies on a substrate, which are displaced from their nominal grid location during the epoxy molding compound process. This fan out technology delivers more space for redistributed I/O connections, providing increased flexibility for homogeneous and heterogeneous integration. Moreover, the final package size can be increased since the panel format supports more packages per substrate than 300mm wafers. Although FOPLP processing has many advantages, it also faces significant challenges. One critical challenge is the reconstituted die placement error, which occurs during the reconstitution and molding process. These placement errors are amplified with the larger panel format when compared to reconstituted wafers, and errors of $50\mu\mathrm{m}$ or more are not unusual. In order to guarantee acceptable yield, these errors must be corrected during the lithography process using site by site corrections. Conducting metrology and site by site exposures on the lithography system is very time consuming. Substrate alignment and error correction are traditionally calculated using global alignment, but this correction does not accommodate the non-linear die placement errors. It has become clear that only site corrections can deliver the overlay required to maintain good yield. Typically, this approach has a huge impact on throughput and would increase the cost of FOPLP process making it impractical. In this paper we demonstrate a revolutionary FOPLP lithography solution for the die placement error challenge. We describe the use of an external metrology tool to capture die placement error data from a panel, and a “feed forward” solution to optimize stepper, site by site, X, Y and rotation offsets, during exposure. We also show how visualization of the metrology data provides the user with the ability to characterize upstream and downstream processes together with a unique yield predication capability. This solution significantly increases stepper throughput, reducing cost and increasing productivity whilst ensuring high yield.

High-Performance Computing systems can employ leading-edge Heterogeneous Integration (HI) technology including Fan-Out Wafer Level Packaging (FOWLP) and high-density Redistribution Layers (RDL) to maximize system bandwidth and performance. These More-than-Moore strategies are growing in importance and present unique challenges that must be overcome to enable mainstream adoption. FOWLP roadmaps for interconnections between SoC (System on Chip) and DRAM (Dynamic Random Access Memory), split-die FPGA (Field-Programmable Gate Array) and image sensors and SoC are driving RDL scaling and aggressive FOWLP processes are targeting $0.8\ \mu \mathrm{m}$ design rules. High-resolution lithography is required for high-density, fine-RDL applications and the main lithography challenge is to provide a large Depth-of-Focus (DoF) to reliably pattern sub-micron RDL traces across a large exposure field. This paper details an analysis of candidate optical conditions for sub-micron imaging including data demonstrating the DoF performance of an optimized lithography system (stepper). To meet the high-resolution requirements of fine-RDL processes, Canon developed the FPA-5520iV-HR [20iV-HR] i-line stepper that employs a new projection optical system featuring a maximum 0.24 Numerical Aperture (NA) and a 52 x 34 mm field size. We will present data illustrating that 0.24 NA steppers can provide excellent resolution and pattern fidelity throughout each exposure field across the entire wafer. High-density FOWLP wafers can also display extreme die-shift, warpage and topography that must be addressed to enable high-yield and high-productivity processes. Die placement error in FOWLP wafers creates orders of magnitude more alignment error versus traditional silicon wafers and advanced alignment compensation is required to improve overlay matching. Alignment solutions for processing distorted FOWLP wafers include the Grid-PA system that automatically corrects the wafer loading position based on die-grid sampling, and Enhanced Advanced Global Alignment (EAGA) that allows the stepper to measure and compensate for shift, rotation and intra-field magnification errors on a die-by-die basis. FOWLP reconstituted wafers can also experience large warpage that can decrease productivity and DoF and to combat these challenges, our steppers have been designed to handle wafers with over 5 mm of warpage and are also based on a Front-End-Of-the-Line (FEOL) stepper platform that offers die-by-die tilt and focus measurement and compensation to maximize focus accuracy and DoF. This paper provides an analysis of key lithography challenges facing aggressive FOWLP and fine-RDL processes details of stepper technology that helps enable high-density integration in mass-production. We remain committed to enabling innovation through lithography system performance upgrades and development of original options supporting current and future FOWLP and fine-RDL processes.

Single longitudinal mode emission of laterally coupled distributed-feedback (LC-DFB) laser diodes (LDs) based on InGaN/GaN multiquantum-well structures containing 10th-order surface Bragg gratings with V-shaped grooves is demonstrated. The gratings were fabricated alongside a 2-μm-wide contact stripe by i-line stepper lithography and inductively coupled plasma etching. A single peak emission at 404.6 nm with a fullwidth at half-maximum of 0.04 nm was achieved at an output power of about 46 mW under pulsed laser operation. The shift of the lasing wavelength of LC-DFB LDs in the temperature range from 22 °C to 45 °C was around three times smaller than that of comparable ridge waveguide Fabry-Perot LDs.

We demonstrate, for the first time to our knowledge, a fully etched TM grating coupler for low-loss Low-Pressure-Chemical-Vapor-Deposition (LPCVD) based silicon nitride platform with a coupling loss of 6.5 dB at 1541 nm and a 1 dB bandwidth of 55 nm, addressing applications where TM polarization is a pre-requisite. The proposed GC and the 360 nm × 800 nm strip based Si 3 N 4 waveguides have been fabricated by optical projection lithography using an i-line stepper tool enabling low-cost and mass manufacturing of photonic-integrated-circuits.

With demands for shrinking footprints and increasing I/O of electronic components, there is an increasing interest in electrodeposited Cu pillar structures for Package on Package (PoP) interconnects. One example of interest involves a 3D package integration approach with the memory mounted above the processor for mobile applications. This paper will explore the processes required and discuss the challenges for Cu pillar fabrication of PoP interconnects at sub 100um pitches. The test vehicles will include variables such as pillar diameter and pitch for a 200um thick liquid film negative tone plating resist on a 300mm wafer format. The high-density pillar pitch is expected to present challenges to resist material applications, lithography capability, and plating capability. Work for this paper is supported by major material and tool suppliers for resist materials, lithography tools, and plating chemistries & plating tools. JSR Micro, Rudolph Technologies, Atotech

For more than 50 years the semiconductor industry has pursued Moore's law, continuously improving device performance, reducing cost, and scaling transistor geometries down to where advanced CMOS has reached beyond the 10nm technology node. The commensurate increase in I/O count has created many challenges for device packaging which hitherto was considered low cost with simple solutions. It was once thought that old backend foundry lithography steppers could be used to address the new packaging requirements; which was true whilst the substrates remained in the traditional 300mm Silicon format. The recent unprecedented rapid growth in Fan Out Wafer Level Packaging (FOWLP) applications has introduced a more complicated landscape of process challenges, with no restriction on substrate format, where cost is the main driver and high yields are mandatory. This paper discusses the lithography process challenges that have ensued from disruptive FOWLP, and more recently the paradigm shift to Panel fan out Packaging. The work reports on lithography solutions for CD control over topography and high aspect ratio imaging of 2μm line/space RDL. In addition, the introduction of new inspection capabilities for defects and metrology is reported for both wafers and panels. The increase in lithography productivity and cost reduction provided by FOPLP is also discussed with production examples.

In this work we address the capability of an alternative overlay evaluation method for the entire BEOL-Process of IHP’s standard 0.25 and 0.13 μm SiGe:C BiCMOS technology. A dual lithography platform NIKON® NSR 210D/207D scanners and NIKON® NSR SF-150 i-Line stepper layer crossing and wafer bow related overlay issues will be discussed. Stack alignment marks, which serves the exposure alignment and overlay determination were introduced. A mismatch for overlay (x/y) |mean| + 3σ values below 8 nm between the KLA® ARCHER 100 overlay and both lithography tools could be demonstrated.

In stepper lithography, the motion control consists of precision positioning concatenating with output transition of the wafer in a step-by-step rastern pattern. Rapid precision positioning becomes challenging as post-transition vibrations can be induced after each transition, and the precision of the wafer positioning can be adversely affected by the transition-to-positioning switching and the drift of the motor system. The main contribution of this paper is the development of a technique that combines an optimal transition trajectory design with the iterative-learning-based feedforward-feedback control. The optimal transition trajectory design method is utilized to obtain the desired trajectory for rapid stage transition without inducing post-transition vibration of the wafer stage when reaching the exposure position. Then a modeling-free iterative-learning control technique is employed to track the desired transition trajectory accurately, and integrated with feedback control through set-point tuning to remove zero-drift during the positioning. This integrated method is illustrated by implementing it to the motion control in a stepper lithography. The experimental results demonstrate the efficacy of the proposed approach over conventional method in achieving rapid precision positioning for stepper lithography.

We report 100-nm gate AlGaN/GaN high electron mobility transistors (HEMTs) without electron-beam (e-beam) lithography featuring current gain cut-off frequency ( $f_{\mathrm{T}}$ ) and maximum oscillation frequency ( $f_{\max}$ ) of 66 GHz and 206 GHz, respectively. Fabricated in commercial fab, the gate width of ∼80 nm using i-line stepper and sidewall technology on 6-inch wafer indicates the possibility application in rapid mass production compared to slow and expensive e-beam method.

Single nanowires have a broad range of applications in chemical and bio-sensing, photonics, and material science, but realizing individual nanowire devices in a scalable manner remains extremely challenging. This work presents a scalable and flexible method to realize single gold nanowire devices. We use conventional optical stepper lithography to generate notched beam structures, and crack lithography to obtain sub-20-nm-wide nanogaps at the notches, thereby obtaining a suitable shadow mask to define a single nanowire device. Then a gold evaporation step through the shadow mask forms the individual gold nanowires with positional and dimensional accuracy and with electrical contacts to probing pads.

The location-controlled epitaxial growth of vertically aligned Si nanowire (v-SiNW) arrays over large surface area was investigated with Au nanodisks (AuNDs) patterned by KrF stepper lithography. There are two steps for synthesizing v-SiNWs from an AuND pattern: annealing and growth. The annealing process induces the formation of a single Au nanoparticle (AuNP) from an AuND pattern, which consists of several cracked AuNPs. Here, the oxide layer between the AuNDs and Si substrate is necessary for impeding the diffusion of Si atoms into the AuNPs. However, the oxide layer must be removed for properly aligned epitaxial SiNW growth. These SiNW arrays in large area can contribute highly to improve a nanowire-based engineering by controlling the location of SiNWs with consistent pitch.

Mass production of high density interconnects using 3D and 2.5D technologies requires optimal lithography processing with certain optical properties. This paper discusses the modifications and performance changes made to a step-and-repeat camera that have improved the tool utilization. New options are available that enhance the performance and provide the best match to a wide range of resist requirements to attain optimal fidelity and higher throughput. Changes in illumination power, partial coherence and wavelength bandwidth are discussed. Modeling tools are used to predict the improvement and guide the process. Changed optical parameters that impact the image performance are modeled and compared to resist images evaluated. The illumination power increases are used to calculate the impact these changes have on increased throughput. Examples will show modeled and measured improvements achieved.

A slim beam deflector that satisfies both a large steering angle and a large area can be very useful in various applications. However, a smaller electrode pitch for a large steering angle and enlargement of its area are trade-off relations due to the limited number of control channels in an electrically tunable beam deflector system. For a large steering angle in the active area where actual diffraction occurs, an indium tin oxide electrode of 2 µm pitch was implemented through a stepper lithography. The via-hole process was developed to expand the reduced active area due to the small electrode pitch. We developed a beam deflector with 7200 controllable channels in an active area of 14.4 m m × 14.4 m m . The maximum steering angle is 7.643° at a wavelength of 532 nm.

This paper presents the latest lithographic advances to enable scaling of packaging redistribution layer (RDL) feature size towards 1-2 µm line and space on panel-based glass substrates. Critical dimension (CD) of 1 µm line and space with aspect ratio (AR) of 5 was demonstrated in a newly developed chemically amplified plating photoresist by using i-line contact mask aligners and low numerical aperture (NA) 1x projection steppers. The minimum line and space demonstrated was 0.9 µm with AR of 5.5. Such high AR package RDL has much lower trace resistance compared to silicon back-end-of-line (BEOL) RDL, enabling power-efficient higher bandwidth. The relationship between resolution (R) and depth-of-focus (DOF) for low NA projection stepper is discussed. Low cost, low NA, large field steppers are better suited to large panel and large size package fabrication. A cost-effective mechanical fly-cut process was implemented for planarization of the entire wafer or panel with < 1 µm flatness that ensures the success of 1 µm with AR of 5 lithography by using low cost lithographic tools.

As the planarization technology for multilayers develops to advance the miniaturization of the semiconductor devices, the market of chemical mechanical planarization (CMP) equipment/materials continues to expand in pursuit of “More Moore.” In particular, the demand of for CMP technology for the miniaturization has increased owing to the upgrading of lithography technology, and the market has expanded. We consider that CMP market size correlates with developments in lithography. Among lithography generation changes, the advances in miniaturization, multilayer device packaging, and mounting boards are remarkable. In the future, more advanced packaging technology is required for Big Data, the Internet of Things (IoT), 5G communication, artificial intelligence (AI), and autonomous driving. To achieve the miniaturization of packaging technology, the crucial points are as follows: (i) it is necessary to use a stepper for lithography technology, and (ii) the stacking substrate must be accurately connected with a narrow pitch. We investigate the necessity of CMP technology on the basis of trends and future predictions.

Novel wafer stepper by using contact or proximity printing was developed. The ultraviolet region starts right after the violet end of the rainbow. In scientific terms, UV radiation is electromagnetic radiation just like visible light, radar signals and radio broadcast signals. Ultraviolet radiation can be broken down into three bands: UVA, UVB, and UVC. Projection wafer stepper needs use single wavelength as light sources, such as: g-line, i-line, KrF and ArF. The broadband wavelengths of the UVA, UVB and UVC regions: UVA 400 nm - 315 nm, UVB 315 nm - 280 nm, UVC 280 nm - 100 nm can be used for contact or proximity exposure. Wafer stepper without using projection lens, system reliability and manufacturing cost of wafer stepper can be improved by using contact/ proximity method. This novel contact/ proximity wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist.

Single-pixel fiber-coupled superconducting nanowire single-photon detectors (SNSPDs) operating at 1550 nm and utilizing amorphous superconducting tungsten silicide (WSi) films have proven ability to detect photons with: high system-detection efficiency (SDE) of up to 93%, low-jitter on the order of ~150 ps, dark count rates of ~1 kcps, and fast reset times on the order of tens of nanoseconds. Additionally, WSi SNSPD devices with 12-pixels have recently demonstrated downlink data rates of 79 Mbps between a terminal in orbit around the moon and a terminal on earth, as part of the Lunar Laser Communication Demonstration (LLCD) at the Lunar Lasercomm OCTL Terminal (LLOT). To further extend the performance of SNSPD devices for optical and quantum communication for terrestrial and space-based applications, the next generation of devices will need to incorporate hundreds to thousands of SNSPD pixels and to be free-space coupled. The wire widths necessary for optimal performance of WSi (~120-220 nm) devices have to date been achieved using electron-beam lithography (EBL) to pattern photoresists for etch-back fabrication methods. The high cost and time to fabricate kilo-pixel arrays of SNSPDs using EBL will become prohibitive in producing such devices. Here, we report fabrication of a WSi SNSPD test structure with 64 pixels using optical lithography instead of EBL. Specifically, we used Canon EX3 and EX6 deep-UV (DUV) steppers with KrF excimer lasers (λ=248 nm) in the Micro Devices Laboratory at the Jet Propulsion Laboratory to fabricate the array. Dies with 8 × 8 pixels with 166-nm-wide wires were produced, with pixels having a 100 μm pitch in the vertical and horizontal directions. Two improvements were observed: 1) the time to pattern the 8 × 8 SNSPD pixels on 3.5 mm × 3.5 mm dies filling a 4-in Si wafer required ~24 hours using EBL while optical lithography wrote the same dies in approximately 15 minutes; and 2) the cost to write one 4-in wafer using EBL was comparable to the cost for one optical mask for use in the stepper to write many 4-in wafers. While fabrication times and costs will vary from facility to facility, the improvements in speed and cost for optical lithography versus EBL are apparent, and this technological advance should scale and enable fast and rapid production of kilo-pixel arrays in the future.

Display Omitted We developed a low-cost mask making process for phase-shift lithography.Multiple exposures can be used to obtain sub-150nm elliptical features.Aspect ratio of features is controlled by changing mask angles between exposures.O2 reactive ion etching can be used to further reduce size of features.This cost-effective alternative allows researchers to pattern nanoscale features. A technique for creating phase shift photolithography masks for use with a stepper or mask aligner, as well as how to achieve sub-150nm features of different aspect ratios is described. The mask utilizes two different regions, one transparent region of only the mask material, and another transparent region of SiO2, which are overlapped to create the pattern. Patterning was done by use of a Canon Stepper. By adjusting the angle between the two mask regions, the aspect ratio, which is defined as the length:width, of features was controlled. Features below 100nm were patterned, and aspect ratios were controllably tuned between 1.1 and 2.6. The feature size was also shown to be able to be reduced by 25-30nm with the use of reactive ion etching.

Increasing volume using larger substrates with decreasing process margins create new challenges for advanced packaging applications. Key step and repeat camera technology continues being introduced for the mass production of high density interconnects used for 2.5D and 3D technologies that will provide solutions for the challenges encountered. A 2X reduction stepper with unique features achieves the tighter specifications needed for many advanced packaging applications printed on large substrates. A large field-of-view optical projection system utilizes the 350–450nm light spectrum from a mercury arc to expose the circuit patterns from a reticle mask onto a substrate and image features with the optimal fidelity required for advanced packaging technologies. The imaging field prints a large 52mm x 66mm area or 59.4mm x 59.4mm in a single exposure. These features enable a system to process larger substrates in fewer shots which result in higher throughput using lower power. Details of the camera and the adjustments that are provided to extend the range of use for both high power and high fidelity applications are discussed. An extensive evaluation of measured and modeled lithographic capabilities of the step and repeat camera to achieve critical dimensions with precise image placement is provided. Limiting resolution and depth of focus results sampled over the imaging field will be provided and supported with simulation. Results of thin and thick resist patterning will be presented and compared to simulated 3D resist profiles using the MACK4 model.

Advanced process technology is required to develop and enable mass production of high-density 3D and 2.5D interconnect technologies. In this paper, Canon and IBM @ Albany NanoTech will present process optimization results for lithography applications requiring precise thick-resist profile control and precise overlay accuracy of distorted patterns on bonded process wafers. Canon will also provide additional product updates from Canon Anelva.

In the last decades the semiconductor technology has been driven by Moore’s law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP’s 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA’s into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of ±500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP’s 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Lithography equipment is undergoing some of the most significant changes since the introduction of the wafer stepper. The driving force behind these changes is the diffraction limit of optics. The resulting characteristics of new lithography equipment, to contend with the diffraction limit, are discussed. The high cost of lithography equipment has made mix-and-match lithography commonplace. Step-and-scan technology is the wave of the near-future, as a way to contend with the difficulty of manufacturing wide-field lenses. Resist processing equipment will undergoing few changes, but will often be integrated with steppers. Metrology is being stretched to its limits for technologies below 250 nm.

The successful fabrication of MIR Ge-on-Si waveguides written by both the high-resolution electron beam lithography (EBL) approach, as well as the wafer scale, high throughput approach using 365 nm i-line stepper lithography is reported. A low propagation loss of ∼2.7 dB/cm at a wavelength of 3.8 μm is shown for Ge-on-Si waveguides patterned using the i-line stepper. The waveguide etching technique, using reactive ion or deep-reactive ion etching, is also analyzed. Furthermore, the propagation loss values for both the lithographic techniques are found to be comparable. Therefore the advantage of using a simpler i-line stepper lithography for high volume fabrication is highlighted.

We present an approach to fabrication and packaging of integrated photonic devices that utilizes waveguide and detector layers deposited at near-ambient temperature. All lithography is performed with a 365 nm i-line stepper, facilitating low cost and high scalability. We have shown low-loss SiN waveguides, high-$Q$ ring resonators, critically coupled ring resonators, 50/50 beam splitters, Mach-Zehnder interferometers (MZIs) and a process-agnostic fiber packaging scheme. We have further explored the utility of this process for applications in nonlinear optics and quantum photonics. We demonstrate spectral tailoring and octave-spanning supercontinuum generation as well as the integration of superconducting nanowire single photon detectors with MZIs and channel-dropping filters. The packaging approach is suitable for operation up to 160 \degree C as well as below 1 K. The process is well suited for augmentation of existing foundry capabilities or as a stand-alone process.

This article discusses the transition of a form of nanoimprint lithography technology, known as Jet and Flash Imprint Lithography (J-FIL), from research to a commercial fabrication infrastructure for leading-edge semiconductor integrated circuits (ICs). Leading-edge semiconductor lithography has some of the most aggressive technology requirements, and has been a key driver in the 50-year history of semiconductor scaling. Introducing a new, disruptive capability into this arena is therefore a case study in a “high-risk-high-reward” opportunity. This article first discusses relevant literature in nanopatterning including advanced lithography options that have been explored by the IC fabrication industry, novel research ideas being explored, and literature in nanoimprint lithography. The article then focuses on the J-FIL process, and the interdisciplinary nature of risk, involving nanoscale precision systems, mechanics, materials, material delivery systems, contamination control, and process engineering. Next, the article discusses the strategic decisions that were made in the early phases of the project including: (i) choosing a step and repeat process approach; (ii) identifying the first target IC market for J-FIL; (iii) defining the product scope and the appropriate collaborations to share the risk-reward landscape; and (iv) properly leveraging existing infrastructure, including minimizing disruption to the widely accepted practices in photolithography. Finally, the paper discusses the commercial J-FIL stepper system and associated infrastructure, and the resulting advances in the key lithographic process metrics such as critical dimension control, overlay, throughput, process defects, and electrical yield over the past 5 years. This article concludes with the current state of the art in J-FIL technology for IC fabrication, including description of the high volume manufacturing stepper tools created for advanced memory manufacturing.

Focusing of wafer plane is an essential factor to determine the ultimate feature size of the stepper such as projection lithographic system. Based on Michelson interferometeric system, this paper demonstrates an interferometric focusing scheme for projection lithography to coaxially locate the ideal focal plane of the projective objective. The collimated incident laser beam is divided into the reference arm and object arm. The latter propagates through the objective lens and then interferes with the slightly deflected reference beam that reflected back by a fixed mirror, giving rise to an interferential pattern on the CCD. Any amounts of defocusing can be directly indicated from the demodulated phase of the interferential pattern. In this manner, the focusing sensitivity at nanometer scale is experimentally attainable, which shows great superiority over traditional methods, particularly the limited focal length of current projective objective lens.

This article reports a process for batch fabrication of a fiber pigtailed optomechanical transducer platform with overhanging. The platform enables a new class of high bandwidth, high sensitivity, and highly integrated sensors that are, compact, robust, and small, with the potential potential for low cost batch fabrication inherent in Micro-Opto-Electro-Mechanical-Systems technology. This article provides a guide to the whole fabrication process and explains critical steps and process choices in detail. Possible alternative fabrication techniques and problems are discussed. The fabrication process consists of electron beam lithography, i-line stepper lithography, and back- and frontside mask aligner lithography. The goal of this article is to provide a comprehensive description of the fabrication process, presenting context and details which are highly relevant to the rational implementation and reliable repetition of the process. Moreover, this process makes use of equipment commonly found in nanofabrication facilities and research laboratories, facilitating the broad adaptation and application of the process. Therefore, while this article specifically informs users of the Center for Nanoscale Science and Technology (CNST) at the National Institute of Standards and Technology (NIST), we anticipate that this information will be generally useful for the nano- and microfabrication research communities at large.

Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smaller TSV diameters, back-to-front overlay becomes a critical parameter because via landing pads on the first metal level must be large enough to include both the TSV critical dimension (CD) and overlay variations. In this paper we investigate the long term capability of a Dual Side Alignment (DSA) lithography system for printing 5 μm and smaller TSV features. DSA lithography is used to pattern the TSV feature, and Stepper Self Metrology (SSM) is performed to verify the overlay after photoresist development. Multiple stepper lithography fields per wafer and multiple wafers per lot are measured to obtain a statistically significant data set for wafer lot overlay analysis. In addition, multiple wafer lots were processed and measured to establish long term overlay performance and stability. In order to independently verify the SSM overlay data, dedicated electrical structures were designed and placed on a Via Last TSV test chip. These structures allow the TSV diameter and TSV overlay to be measured electrically after lot completion. Vector plots were used to compare the SSM overlay and electrical overlay data.

A stepper lithography method for thick epitaxy of special-type device was proposed. In this method, a mask with both alignment mark for proximity lithography and identification mark for stepper equipment was designed to solve the problem of precise alignment to patterns before thick-layer epitaxy and stepper lithography after thick-layer epitaxy. Using this method, the accuracy for alignment of patterns before and after thick-layer epitaxy reached 0.5 μm. This pattern alignment method special for thick-layer epitaxy is also applicable for stepper lithography of VDMOS with NBL, super-junction VDMOS, high-voltage complementary bipolar device and high-voltage BCD device.

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.

There has been 43 years of overlay metrology in microlithography, and how did we get here? This presentation covered three areas: stepper metrology improvements, improved correction potential, and extended feedback loop outside stepper. The presenter went on to discuss where we are today In terms of holistic lithography, as well as where we are going with the future of holistic lithography.

3D sequential integrations such as CoolCubeTM appear to be an alternative to planar scaling for the next generation nodes by stacking CMOS over CMOS and even transistors above transistors. This is possible thanks to high alignment accuracy depending only on the lithography stepper and not on the bonder performance, as in packaging technologies. Performance gain can be obtained either by optimizing each level independently or by the reduction in interconnect delay and thus, optimization of device partitioning and global routing. In this paper, data on the bottom transistors stability and some key enablers to realize a top transistor level at low temperature will be presented.