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For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.

In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-optimized mask was generated for each designated illumination condition as the source was swept through various parameter settings in order to find the best combination of source and mask. This approach has been successfully applied to explore and select lithography processes and design rules for advanced semiconductor technology nodes. In Luminescent's latest implimentation of ILT-enabled SMO, the same Level Set Method used in the mask optimization is used in the source optimization; in other words, the source map is represented by a level set function. During the optimization process, the level set function evolves to achieve a minimized cost function, where the cost function is defined as the difference between aerial image and ideal image (MEEF and DOF can also be used in the cost function) via a gradient flow, and the gradient flow is based on the cost function itself. This flow is interlaceded with the mask inversion flow so that a simultaneous mask & source co-optimization is achieved. In this paper a number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of ILT-enabled SMO.

As design rules of advance devices shrink down, not only process-window budget of lithography process is getting tighter, but also CD control to target is more important especially for multiple tool process environment in HVM (High Volume Manufacturing). The tool induced CD bias or CD difference between tools are derived by minute amount of residual imaging parameters even though with strict control in system. The tool to tool CD mismatch is able to be reduced to nanometer or sub-nanometer scale for critical features of concern by using released tools such as LithoTuner PMFC TM (Pattern Matcher Full Chip). During the matching process, tunable imaging parameters such as pupil shape and stage tilt can be used as matching knobs. In this paper, CD mismatch due to film stack change on same exposure tool was studied to check feasibility of PMFC application. Also, CD variation and its impact on CD mismatch by focus error as amount of intrinsic system was investigated as well. By considering the focus impact on CD proximity bias via simple mathematical ways, the CD matching process could be more accurately performed and verified.

As patterns shrink to physical limits, advanced Resolution Enhancement Technologies (RET) encounter increasing challenges to ensure a manufacturable Pr ocess Window (PW). Moreover, due to the wide variety of pattern constructs for logic device layers, lithographically weak patterns (spots) become a difficult obstacle despite Source and Mask co-Optimization (SMO) and advanced OPC being applied. In order to overcome these design related lithographically weak spots, designers need lithography based simulator feedback to develop robust design rules and RET/OPC engineers must co-optimize the overall imaging capability and corresponding design lithography target. To meet these needs, a new optimization method called SmartDRO (Design Rule Optimization) has been developed. SmartDRO utilizes SMO’s Continuous Transmission Mask (CTM) methodology and optimization algorithm including design target variables in the cost function. This optimizer finds the recommended lithography based target using the SMO engine. In this paper, we introduce a new optimization flow incorpora ting this SmartDRO capability to optimize the target layout within the cell to improve the manufacturable process window. With this new methodology, the most advanced L/S patterns such as metal (k1 = 0.28) and the most challenging contact patterns such as via (k1 = 0.33) are enabled and meet process window requirements. Keywords: RET, manufacturable PW, SMO, SmartDRO , CTM, Design (Layout) Optimization

Application of atop-surface imaging(TSI) process by silylation to ArF lithography is desirable for ULSI production with minimum feature size for sub-120nm. We evaluated lithographic performances of non-chemically amplified positive TSI photoresist and chemically amplified negative TSI photoresist, both based on phenolic polymer. When off-axis illumination was used, 120nm and 110nm L/S patterns were obtained with non-chemically amplified resist(non-CAR) and chemically amplified resist(CAR) respectively. 100nm L/S patterns of CAR were obtained with strong off-axis illumination using binary intensity mask. CAR was superior to non-CAR in terms of lithographic performances, but inferior to non-CAR in terms of resist pattern collapse. Line edge roughness(LER) of CAR was sufficiently minimized by optimizing silylation bake temperature and it was comparable to that of single layer resist. For the prevention of resist pattern collapse in dry development process, the property of adhesion and resist rigidity is impor ant. This results can help the design of matrix resin of TSI resist for sub-100nm lithography.

HTF001 (Hyundai Thermal Flow Resist), a newly developed positive KrF resist for applying the resist flow process (RFP) to define sub-100nm contact hole (C/H) required at advanced gigabit-DRAM, consists of two kinds of polymer which have functional groups to cross-linking. Cross-linking reaction in HTF001 occurs at high baking temperature needed to shrink C/H size up to sub-100nm. The flow-characteristics and the deformation of C/H profile are greatly improved by applying HTF001. Extreme fine C/H (55nm) patterns applicable to 16G DRAM, successfully obtained from an original 200nm C/H patterns with KrF (248nm) lithography, show good pattern profiles without severe bowing, and still keep up the initial CD (Critical Dimension) uniformity after the resist flow. Moreover, it is successfully transcribed to vertical oxide C/H without CD bias, when we etch the oxide substrate of 5000A.

Recently reported ArF positive photoresists can be classified into three groups: derivative methacrylate copolymers (methacrylate resist), methacrylate copolymers functionalized with pendant alicyclic moieties (alicyclic resist), and cycloolefin-maleic anhydride copolymers (cycloolefin resist). Each system has its own advantages and drawbacks in the viewpoint of lithographic properties.Methacrylate resists have been used for the assessment of ArF lens performance. However, it is hard to apply them in real device process because of their low plasma-etch resistance. Previous studies have reported that alicyclic resists possess adequate etch resistance with the help of cyclic carbon units, however these resists show poor adhesion and seldom dissolve in 2.38% TMAH developer. The cycloolefin resists will be good candidate for addressing the trade-off between etch resistance and requisite material properties for lithographic performance because these resists, unlike methacrylate-based resists, contain large quantities of alicyclic structures directly in the polymer backbone and such properties as dissolution and adhesion can be readily controlled by incorporation of -COOH and -OH functional groups into cycloolefin structures.We have synthesized poly(2-hydroxyethyl 5-norbornene-2-carboxylate / t-butyl 5-norbornene-2-carboxylate / 5-norbornene-2-carboxylic acid / maleic anhydride; HNC / BNC / NC / MA) resists with a variety of functional groups and obtained lithographic performance by using ArF stepper(0.6NA). In this paper, we will describe the basic idea for designing of the novel cycloolefin resist and demonstrate lithographic capabilities, especially in terms of process window for 130nm feature. In addition, the etch resistance of this resist will be shown. We believe that off-axis illumination should be applied to 130nm device technology to obtain wider process window

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last three decades, DRAMs(Dynamic Random Access Memories) have been quadrupling in level of integration every three year. The 16 Mb DRAM (0.5 μm design rules) is into volume manufacturing. Early 64 Mb DRAM (0.35 μm design rules) manufacturing is now on target. Logic circuits follows a similar trend, although 2 or 3 years later. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC's (Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography and post optical lithography technology, such as E-beam lithography and X-ray lithography for the next century.

ArF excimer laser(λ=193nm) lithography is emerging following KrF DUV lithography(λ=248nm ). 193nm lithography has proven its potential for feature sizes down to 0.15μmlines/spaces patterns using high NA(O.6) because of resolution improvement. However, in practical use of ArF technology, there are problems involved in the properties of photoresist. To solve these problems, we synthesized ArF polymer resin, poly(2- (2-hydroxyethyl) carboxylate-5-norbornene / 2-t-butylcarboxylate-5-norbornene/2-carboxylic acid-5-norbomene/Maleic anhydride), all of the main chains are composed of alicyclic unit. 2-(2-Hydroxyethyl) carboxylate-5-norbornene was found as a very suitable adhesion promoter. Using this resist, 0.15μm L/S pattern was obtained at 14mJ/cm2 doses, using an ArF stepper on the developer, 2.38wt% tetramethyl ammonium hydroxide aqueous solution.

A positive-tone wet silylation process for I-line lithography is developed, using safe solvents and the commercial photoresist AZ 5214E (by Hoechst). The process is capable of resolving 0.3 μm lines and spaces on photoresist. Various silylating conditions, solution concentrations and two silylating agents namely HMCTS and B(DMA)DS have been tried. Silicon concentration, focus and exposure latitudes have been defined.

The combination of off-axis illumination (OAI) schemes with ‘weak’ phase shifting techniques is promising to improve the process latitudes of both dense and isolated features. In this paper, the performance of this combination to print 0.25 μm poly levels for logic circuits is investigated experimentally and by simulations, using DUV stepper ( λ = 0.248 μm , 0.42 NA ). Various resist types have been addressed, mainly with respect to proximity issues.

Patterning of contact hole using KrF lithography system for the sub 90nm technology node is one of the most challenging tasks. Contact hole pattern can be printed using Off-Axis Illumination(OAI) such as dipole or Quasar or Quadrupole at KrF lithography system. However this condition usually offer poor image contrast and poor Depth Of Focus(DOF), especially isolated contact hole. Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip CD variation reduction. The insertion of SRAF in a contact design is mostly done using rule based scripting. However the rule based SRAF strategy that has been followed historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow sustainable manufacturing. Especially in case of random contact hole, rule-based SRAF placement is almost impossible task. We have used an inverse lithography technique to treat random contact hole. In this paper we proved the impact of SRAF configuration. Inverse lithography technique was successfully used to treat random contact holes. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described. As a conclusion, we suggest methodology to set up optimum SRAF configuration with rule and inverse lithography technology.

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Source Mask Optimization techniques are gaining increasing attention as RET computational lithography techniques in sub-32nm design nodes. However, practical use of this technique requires careful considerations in the use of the obtained pixilated or composite source and mask solutions, along with accurate modeling of mask, resist, and optics, including scanner scalar and vector aberrations as part of the optimization process. We present here a theory-to-practice case of applying ILT-based SMO on 22nm design patterns.

As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.

The lithographic performance of phase shifting and transmission masks are compared. This paper describes the ultimate resolution and process latitudes, that can be obtained by combining a phase shift mask with the DESIRE process at 248 nm. Special emphasis is put on the influence of coherence. Both simulation and experimental results are given.

Multiple focus exposures[1], optimization of the partial coherence[2–4] of the stepper and the use of surface imaging[5] have been studied as possible ways to improve depth of focus and exposure latitude for deep-UV lithography at sub-0.5 μm dimensions. Simulation and experimental results are compared. The multiple focus technique gives a marginal improvement in depth of focus, but at the expense of resolution and exposure latitude. Surface imaging combined with higher coherence factors gives the best resolution with the widest latitude.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance and need to be enabled for production as one of the leading candidates for low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (IS™) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT n eeds to be studied at full chip level with various aspects including mask data fracturing, MRC co nstraints, writing time, and inspection. The computation of ILT mask usually starts with the calcu lation of an optimized contoured mask then followed by manhattanization step to convert contour into horizontal-ver tical segments. By varying the segmentation length during manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of segmentation length impact on writing time and lithography perfor mance at full-chip is presented. MRC is another important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and inspectability at various selected MRC rules are also presented in the paper. Keywords: Inverse lithography technology (ILT), Sub-resolution assist feature (SRAF), Resolution enhancement technology (RET), Lithography simulation

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM and RET flow required to continue shrinking designs in the low-k1 lithography regime. The ability to model and minimize MEEF during lithography optimization and RET application is essential to obtain a usable process window (PW). In Inverse Lithography Technology (ILT), MEEF can be included in the cost function as a nonlinear factor, so that the inversion minimizes MEEF, in addition to optimizing PW and edge placement error (EPE). ILT has been shown to optimize masks for a given source. Using ILT for contemporaneous Source and Mask co-Optimization (SMO) can provide further benefit by balancing the complexity of mask and source. Results demonstrating the benefits of "MEEF-aware" ILT and SMO for advanced technology nodes are presented in this paper.

In this paper, an overview of Inverse Lithography Technology (ILT) based on Level Set Methods (LSM) is provided. Applications of ILT in the advanced lithography process are then shown for several different devices, including DRAM, SRAM, FLASH, random logic, and imaging devices. ILT is used to correct the main patterns, as well as automatically insert SRAFs using model-based mathematical methods. The process of SRAF generation in ILT is unified with the process of inversion. With the help of ILT, SRAFs can be inserted where physically needed, independent of source parameters or target patterns. Results that demonstrate the adaptive nature of ILT SRAF insertion capability are presented. Wafer verification results were collected by multiple advanced semiconductor manufacturing companies at advanced technology nodes, including 45nm and 32nm nodes, and compared with their current OPC solution. Final wafer results presented here demonstrate that ILT improves pattern fidelity, enlarges process window, and provides remarkable control for line-end shortening.

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

Evaluation of lithography process or stepper involves very large quantity of CD measurements and measurement time. In this paper, we report on a application of Scatterometry based metrology for evaluation of binary photomask lithography. Measurements were made on mask level with ODP scatterometer then on wafer with CD-SEM. 4 to 1 scaling from mask to wafer means 60nm line on wafer translates to 240nm on mask, easily measurable on ODP. Calculation of scatterometer profile information was performed by a in-situ library-based analysis (5sec/site). We characterized the CD uniformity, linearity, and metal film thickness uniformity. Results show that linearity measured from fixed-pitch, varying line/space ratio targets show good correlation to top-down CD-SEM with R 2 of more than 0.99. ODP-SEM correlation results for variable pitch shows that careful examination of scatterometer profile results in order to obtain better correlation to CD SEM, since both tools react differently to the target profile variation. ODP results show that global CD distribution is clearly measurable with less outliers compared to CD SEM data. This is thought to be due to 'averaging' effect of scatterometer. The data show that Scatterometry provides a nondestructive and faster mean of characterizing lithography stepper performanceprofiles. APSM 1st level (before Cr removal) 'dual-space' CDs and EPSM rectangular contacts were also measured with and results demonstrates that Scatterometer is capable of measuring these targets with reasonable correlation to SEM.

Scatterometers are widely used for line/space or 2D structure measurements in both wafer and mask industries. This technology is now gaining more acceptance and is being applied 3D structures such as contacts and pads. Contact CDs and trench depth in photomasks are critical monitoring parameters in mask industry and are discussed here. We are reporting contact CDs and profile results measured from targets from Binary, PSM, and Crless plates. The strategies of model creation such as using simple trapezoid versus more advanced shapes affect how well SWA and footings can be measured and reported from these structures. We are reporting CD and profile information obtained with Scatterometer, and then comparing CD SEM, AFM, and cross section SEM. Multiple different modeling configurations were used with different levels of complexity, and we report on optimum modeling strategy to obtain profile information from 3D structures. The relationship between the modeling strategy versus cross correlation between different parameters is discussed. CD linearity, uniformity, and other correlation parameters to the reference CD SEM tool are reported. Target CDs ranged from 60nm up to 600nm. CD uniformity reported from Scatterometry is 20~30% less than that from CD SEMs. This CD uniformity improvement is due to the fact that scatterometer beam samples dozens to hundreds of samples and 'averages' profile parameters, thus eliminating local effect such as line edge roughness. Contact depth are also measur ed and compared to AFM, in which the bias between the two tools are usually around 3nm or less. In terms of smallest target CD measurable, in this paper we report routine measurement of small contacts with middle CD down to 65nm (bottom CD close to 50nm) with both RP and SE mode. Application of scatterometry method to mask contacts and pads leads to accurate and fast measurement of 3D profiles, and opens up possibility of in-line monitoring of profile information due to the higher runrate compared to traditional metrology tools. Keywords: contacts, scatterometry, metrology, binary, PSM, Crless.

Linewidth and etch depth control on the photomask is rapidly becoming a major concern in mask processing. In this paper, we report on a Scatterometry based metrology system that provides line width and etch profile measurements on Embedded PSMs on Intel's 65nm and 45nm node test masks. Measurements were made with Nanometric's Atlas-M reticle measurement system. Spectrum data obtained from plates were analyzed using Timbre Technologies’ ODP analysis software. We characterized the CD uniformity, linearity, sidewall angle and thickness uniformity. Significant reduction in time per measurement is achieved when compared to CD-SEM. ODP Scatterometry reported a 2x reduction in the CD Uniformity compared to that reported from the SEM. This reduction is typically due to outliers reported by the CD-SEM that is averaged out in ODP Scatterometry. Good correlation to top-down CD-SEM and cross-sectional SEM is reported. R-squared correlation of >0.99 (ODP scatterometry to top down CD-SEM) is reported. Profile measurements from ODP show excellent match to cross-section SEM. The data show that Scatterometry provides a nondestructive way to monitor basic etch profile combined with relatively little CD metrology lag.

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography. As the requirement on critical dimension (CD) and side wall profile control becomes ever stringent as minimum feature sizes keep shrinking following the Semiconductor Industry Association (SIA) roadmap, the patterning of the EUV mask absorber material, cost of ownership (COO) of mask, and the capability for defect free EUV masks become the crucial path in enabling the overall success of EUV lithography. The purpose of this study is to understand the etch characteristics in TaN-based EUV mask absorber etch, which will enable us to determine robust process condition in terms of CD performance and profile control. In this paper, CD bias performance in TaN-based EUV mask absorber etching is investigated within inductively coupled plasma (ICP) of fluorine-containing and chlorine-containing gas chemistries. The effects of etch parameters, such as plasma source power, bias power, and pressure, on the CD bias are evaluated through design of experiments (DOE). Some other etching characteristics like etch rate and selectivity are also correlated to the CD performance and etch profile to understand the basic etch mechanism in TaN etch. Latest etch results of the TaN-based absorber are also presented.

In this paper, two negative-tone chemically amplified resists (CAR) are evaluated. The methodology and results are compared and discussed. The resists include EN-024M from TOK, and NEB 31 from Sumitomo. Both resists show high contrast, good dry etch selectivity, and high environmental stability. EN-024M showed good coating uniformity while NEB31 showed a coating uniformity problem. This was a round “dimple” approximately one centimeter in diameter of different thickness and density at the center of the plate. We addressed the “dimple” coating problem as described in the paper. Optimum PAB and PEB temperatures and nominal to maximum doses for isolated features were determined by running a matrix of PAB and PEB temperatures along with a dose series. We evaluated the process and compared the lithographic performance in terms of dose sensitivity, dose and bake latitude, resolution, resist profile, OPC (Optical Proximity Correction) pattern fidelity, CD uniformity, environmental stability, Line Edge Roughness (LER) and etching bias and resistance.

High resolution etching of MoSi for photomask processing places new requirementson etching processes. As resist features are sized to 100nm and below, it is firstnecessary to duplicate these features first into a chrome over-layer. After resist isstripped, this chrome over-layer is used for etching MoSi. Both chrome and MoSietched profiles require near-vertical sidewalls, good CD (critical dimension)uniformity, good linearity, and CD mean-to-target (MTT). Additional requirementsof etched MoSi include minimal roughness on exposed quartz, selectivity to chromeand quartz, phase angle target and phase angle uniformity, etch depth globaluniformity, and etch depth uniformity as a function of feature size.An ETEC integrated process is used for the application of resist, patterning, and allsubsequent processing. Chemically amplified resist is patterned with the 50kVMEBES ® Quadra ™ or MEBES eXara ™ raster scan electron beam writer, allowing forpatterning of small features with vertical resist profiles. Plates are etched in a Tetra

In the lithographic processing, application of a bottom anti-reflective coating (BARC) has proven to provide a number of benefits, such as elimination of reflective notching generated by reflections from highly reflective substrates, reduced swing effects caused by thin film interference, and therefore improved line-width control. To achieve such benefits, the organic BARC materials should have strong absorption at the exposure wavelength, high etch rate and matching to commercial chemically amplified resist. In design concept, the formulation of organic BARC material requires a minimum of two functional parts i.e., a chromophore to control the reflection and a cross-linking part to avoid intermixing with resist cast on it. In this paper, we report the performance of new organic BARC materials designed to work for lithographic applications at 248 nm as well as 193 nm simultaneously.

The effect of mixed PAGs on the performance of ArF photoresists based on cycloolefin/maleic anhydride (COMA) copolymers were investigated. Several different PAGs were prepared according to the size of photogenerated acid moiety and structure of light sensitive chromophore, and the impact of PAG property on lithographic performance was investigated in terms of the acid size, acid generation efficiency, and hydrophobicity of PAG. The diffusion according to the size of generated acid and hydrophobicity of PAG were found to be the most profound factors of the pattern profile and line edge roughness (LER) of developed resist pattern. Resolution capability as well as PED stability can be improved though adjustment of acid size, PAG hydrophobicity. Additionally, profile difference between dark and bright field according to mask type can be suppressed by the use of PAG with lower acid generation efficiency. However, lithographic performance, such as LER, pattern profile, and PED stability show the dissimilar trend with acid size and hydrophobicity of PAG. Thus, when PAG mixture is employed in a photoresist formulation, it is observed that both pattern profile and LER were improved simultaneously, which has been difficult to achieve for previously reported OCMA- based ArF resists.

This paper describes that attenuated phase shift masks (APSM) improve process margin compared to binary mask (BIM) in KrF and ArF lithography. We present the real problems to occur in the mask fabrication, process and mask error factor (MEF). As a result, sub-120nm cell patterns were delineated with 8% exposure latitude (EL) and ~0.6 ?m local depth of focus (LDOF) using 0.70NA KrF and APSM. The performance of ArF lithography (NA=0.63) shows the similar process margin with 10% EL and -0.6 ?m LDOF. Using APSM, we could obtain 14.4% EL and -0.6 ?m LDOF. We obtained process enhancement of 30% by using APSM. However, process instability is analyzed in a viewpoint of mask making and process issue such as mask fabrication capability, CD uniformity, and MEF. In simulation and experiment, 0.63NA ArF lithography shows resolution improvement compared to 0.70NA KrF. It is possible to obtain lOOnm pattern using ArF and APSM. Also, one of common issues is to reduce the MEF, which is decided by exposure and resist process condition. MEF is increased to about 4 or more in the sub-120nm range. This effect has influence on CD uniformity and EL margin. Reducing the MEF on the wafer, we have to optimize exposure tool, process, and mask. Shorter wavelength and APSM are one of candidates to minimize MEF. Therefore, ArF APSM is looking forward to high performance lithography.

The patterning potentialities of sub-100nm pattern for ArF lithography was evaluated with conventional alternating PSM (alt-PSM) for dense lines and spaces (L/S) and phase edge PSM (PE-PSM) for isolated lines of memory device. In dense L/S pattern,110nm pattern was defined with relatively small depth of focus(DOF) window(~ 0.2 ?m) due to phase error of mask. As pattern sizes was changed from 130nm to 200nm, critical dimension (CD) difference between two neighboring spaces was varied and it was assumed that micro loading effect was occurred in Qz etching. The linearity was guaranteed to dense L/S of 110nm and isolated line of 90nm, and Iso-Dense bias was controlled within 15nm. The 60nm and 70nm isolated lines of PE-PSM ware defined with good process windows in the case of OA_X size(X-direction size of Cr open area) of 0.5 ?m. The 55nm isolated line was also defined. The pattern shift of isolated lines was occurred with 4~7nm as phase of mask was varies within 190 ~ 200 ° . Though the alt-PSM with high numerical aperture (NA) for ArF lithography was strong candidates for sub-1 OOnm lithography of memory device, the issues of mask fabrication such as tighter phase control and minimizing etch loading effect would be big obstacles. On the contrary, there were many possibilities of sub-100nm patterning in PE-PSM with good process windows, however tighter control of pattern shift due to phase error must be studied intensively.

Optical lithography at resolution limit is a non-linear pattern transfer. One of the important issue is a mask critical dimension control because of nonlinear amplification of mask critical dimension error during image transferring on wafer. This amplification of mask error is called the MEF. This mask error factor has been widely used as an important parameter for indicating tighter CD control for the photomask for low-kl lithography generation.

The defect control of the attenuated-PSM is compared with that of the conventional binary intensity mask (BIM), because the fabrication process for the att-PSM tends to generate more defects than that of the BIM. To repair a defective att. PSM, a similar method used for BIM has been applied. However, this process may cause degradation of pattern fidelity with the repair pattern on the mask are transferred on the wafer, if the transmission and phase of repaired area are not well controlled. In this paper, we have investigated the effect of repairing process on the pattern fidelity to define contact holes using a KrF lithography with an att. PSM. The defects in the various distances form contact hole patterns and of various sizes were repaired. The experimental printability and simulation data from an aerial image model were compared for repaired defects. And the repair tool reliability and the simulation accuracy of the att. PSM was examined using CD-SEM. From the experimental results, repaired defects having larger size than the threshold. One or within a certain range from the pattern induced the pattern deformation. Therefore, the size of defect and the distance between the pattern and defect should be considered in repair process for the Att. PSM fabrication. Based on the experimental and simulation results, the requirements for the repair tool will be proposed.

We estimated the process margins of various cell structures and process problems for full chip process under extremeresolution limit of exposure tool. Therefore, optimizing off axis illumination (OAI) condition for various structures obtainedthe fme pattern and wider process margin using simulation and experiment. From our experiment, we should use as highernumerical aperture (NA), smaller R and smaller r as possible to reduce critical dimension (CD) difference between denseand isolated patterns. Process margins are obtained more than 8% exposure latitude (EL) and 0.5 tin depth of focus (DOF)for each cell. However, we can consider using of attenuated phase shift mask (PSM) to improve the exposure and DOFmargin. We fmd that real full chip process induces the critical problems such as isolated line (I/L) and space (L'S) patternvariation due to lens aberration, partial coherence effect, mask error effect, and optical proximity effect. These effects playa role to determine the design rule of cell and periphery structures. In spite of good lens quality, variation of I/L and USpattern for various exposure conditions is almost 4Onm or more compared to line and space (L/S) pattern. These phenomenaare becoming the critical issue to fulfill the full chip process of l3Onm lithography. By optimizing mask error effect,isolated and dense pattern bias (ID bias), and OAI, we can achieve l3Onm technology with 248nm KrF lithography.KEYWORDS : KrF, Design rule, ID bias, OAI, Full chip process, High NA, Process margin

In this paper we investigated the feasibility of printing sub-0.13 micrometers device patterns with ArF and KrF lithography by using experiment and simulation. To do this we evaluated various cell structures with different sizes from 0.26 micrometers to 0.20 micrometers pitch. In experiment 0.60NA ArF and 0.70NA KrF exposure tools, commercial and in house resists and bottom anti-reflective coating (BARC) materials are used. To predict and compare with experimental data we also used our developed simulation tool HOST base don diffused aerial iamge model. We found that ArF lithography performance is a little bit better than KrF and therefore 0.70NA KrF lithography can be used up to 0.12 micrometers design rule device and 0.60NA ArF lithography can be used up to 0.11 micrometers . But to get more than 10 percent expose latitude, 0.13 micrometers with KrF and 0.12 micrometers with ArF are the minimum design rule size. However to obtain process margin we had to use extreme off-axis illumination (OAI) which results in large isolated- dense bias and poor linearity including isolated pattern. Using higher NA can reduce ID bias and mask error factor. For contact hole it is more effective to use KrF lithography because resist thermal flow process can be used to shrink C/H size. Our developed ArF resist and BARC shows good performance and we can reduce k1 value up to 0.34. Through this study we verified again that ArF lithography can be applied for sub-0.13 micrometers device through sub-0.10 micrometers with high contrast resist and 0.75NA exposure tool.

In this study, we will introduce a new definition, as 'Degree of Patterning Performance (DOPP)' for analyzing process capability. DOPP represents the total performance, which can estimate whether it could be available to adapt any device ona certain integration process. The degree of difficulty on some projects can be represented by DOPP, which considers design rule, field size, mask error, lens aberration, illumination imperfection, resist performance, and the others. Via DOPP, one can estimate whether some project can be available on mass production or not, and machine performance is normal or not. And also, one can quantitatively analyze how effective several causes of CD variation are on total patterning performance respectively. The simple DOPP metric can be used widely on various situations, which will be introduced in detail on this paper.

Ultimate limitation of lithography has been studied by using the diffused aerial image model (DAIM). Assuming that only the 0th and 1st order diffraction beams in the off-axis illumination technique contribute to the resist patterns, aerial image is calculated for dense line and space patterns. And then DAIM is applied to achieve final image. By using this diffused aerial image, exposure latitude and mask error effect can be analyzed quantitatively. In the case of perfect image, which can be achieved from, for example, diffraction free x-ray lithography or electron beam lithography without Coulomb repulsion and back scattering effect, same approaches are possible to get the exposure latitude and mask error effect. Under the validation of DAIM, most important parameter, which characterizes dense L/S patterns, is the diffusion length of acid. In order to realize sub-o.1 micrometers pattern with enough process margins, it is required to enlarge exposure latitude and to reduce mask error effect. Therefore, reducing h acid diffusion length of chemical amplification resist (CAR) or new conceptual resist instead of CAR will be needed for sub-0.1 micrometers era.

Recently, the miniaturization of the design rule of memory devices pushes the minimum feature sizes down to sub- wavelengths of the exposure tools. The design of a memory device comprises not only the dense patterns with critical small size in the cell region but also the random patterns in the peripheral region; the latter also need sub- wavelength lithography technology as well as the former. And the optical proximity correction (OPC) has been strongly required for the random patterns in the peripheral region where the same energy is exposed as in the cell region. Therefore, the high accuracy of simulation model used in the OPC is necessary for the full chip OPC tools. However traditional aerial image simulation has a limitation to the application due to its lack of accuracy because it does not take into account a resist process. We introduced novel lithography simulation model in 1998, which describes resist process by diffusion and chemically amplification function.

The compatibility of novel organic bottom anti-reflective coatings (BARC), HEART003 and HEART004 developed by Hyundai Electronics, with various chemically amplified resists (CAR) was reported. The incompatibility between organic BARC and CARs is caused by the differences of residual activity on the surface of organic BARC after baking process and the types of dissolution inhibitors in the polymer of CAR and photo acid generators (PAG) used in their formulation. In KrF lithography, the HEART003 was much compatible with acetal type resist than annealing type resist because it's neutral acidity on the surface of BARC. The incompatibility with annealing type resist was caused by weak residual acidity on the surface of BARC, relatively. Thus we tried to adjust the feasible residual acidity on the surface of BARC and optimum thermal baking condition. The modified HEART003 has excellent compatibility not only with acetal type resist, but also with annealing type resist in the same platform. In ArF lithography, the HEART004 has also good compatibility with cycloolefin type and (meth)acrylate type ArF resist by modification of its formulation.

ArF DUV ((lambda) equals 193 nm) lithography is rapidly emerging after 248 nm lithography because of the demand for further resolution improvement and wider Depth Of Focus (DOF). However, the 193 nm lithography requires innovative development in various areas, such as laser sources, resist chemistry, new PSM shifter materials, and optics materials. In this study, we evaluated TiSi-nitride based new attenuated PSM in terms of mask making process and its lithographic performance for ArF lithography. We used two kinds of TiSi- nitride based attenuated PSM blanks having 6% and 9% transmittance, respectively. Chemical durability of TiN/SiN film was evaluated. We selected optimal dry etching condition for mask making with good mask profile (side wall angle greater than or equal to 85 degrees) and Quartz (Qz) substrate roughness. The DOF margin at 9%-PSM was larger than those of others (6%-PSM and BIM) and Exposure Latitude (EL) of PSM was larger than that of BIM. Therefore, we concluded that TiSiN- based attenuated PSM was effective for ArF lithography.

Photomask is one of the most critical technologies for lithography. Optical lithography at resolution limit is a non- linear pattern transfer process. OPC (Optical Proximity Correction) technology has been used in the semiconductor industry for controlling the shape of pattern, and eliminating the line shortening and corner rounding effects for submicron feature. Therefore, OPC technology is an approach for improving lithography performance that has been received much attention recently. We investigated the lithographic performance in terms of EL (Exposure Latitude), DOF (Depth of Focus), and mask error effects for various mask fabrication. It was observed that mask error gave severe influence on the lithographic performance and the OPC simulation error also strongly depended upon the mask quality.

Critical issues for 150nm DUV lithography using 0.70 NA KrF and 0.60 NA ArF had been investigated. Aberration, coherence variation, mask error effect, and process margin for each case had been analyzed. Current projection lens and illumination optics are getting better and better. However, for 150nm lithography using high NA scanner, a large portion of beam should be traced on the outside of lens pupil and traced on the resist surface with a large incident angle. In such a case, lens aberration effect was observed on field edge, even though strehl ratio of projection lens and coherence variation on field edge had been improved. These effects had been investigated. One other critical issue in high NA scanner is depth of focus. The common depth of focus between dense and isolated patterns in real process using high NA scanner is mainly affected by photoresist thickness. That issue had been also investigated. Another important issue for 150nm DUV lithography is mask error effect. In the case of same design rule, lower (lambda) /NA lens is more favored than higher (lambda) /NA. Mask error issue in high NA KrF and ArF was also analyzed. Total comparisons between high NA KrF and 0.60 NA ArF have been discussed.

With KrF and off-axis illumination (OAI) technique we should set up 150nm lithography process without using phase shift mask. But isolated-dense bias (ID bias) makes 150nm lithography process difficult. We investigated ID bias trend at different OAI condition and found that it could be reduced by optimizing OAI condition. We represent OAI as quadrupole center (sigma) R and pole size radius r. With high NA, small R and small r we can reduce ID bias but cannot eliminate completely at 150nm lithography. Also we found out that ID bias of duty patterns are more severe than that of dense and isolated patterns. Using OAI at a certain space width between lines, the width of lien has its minimum. This line thinning phenomena at this weak zone depends on OAI condition such as NA, R and coherence value. We compared simulation data with experimental result and could see the same phenomena at simulation data. Therefore OPC is necessary to avoid this weak zone. By experiment and simulation with NA higher than 0.65 and Optical Proximity Correction, we could set up 150nm lithography process with below 0.20micrometers periphery pattern design rule.

In order to improve the overlay accuracy in electron beam lithography, we have investigated the optimization of alignment key that included a ratio of alignment key according to scanning beam size, an optimum key depth/width, and material's dependency. The alignment repeatability of key, has the same ratio with scanning beam size, appears good results as compared with the other ratio. Scanning beam size also correlates with an alignment key width. As a process sequence of CMOS device, the key width of under layer is changed by the thickness of deposited materials, because of the deposition on side-wall. Therefore, the scanning beam size should be optimized for each step. In each material, there exists the critical thickness not affecting on the alignment reading repeatability. The standard deviation(3 σ), which is calculated by measurement of key position with critical thickness, is less than 20nm. We have results of the critical thickness of various materials. Si02 and Si3N4 do not affect on the alignment signal, but doped WSix, Al, and doped poly-silicon are very sensitive because of back-scattering electrons. Using the optimized align key of WSix/doped poly-Si, the standard deviation (3 σ) was less than 10nm. Otherwise, non-conducting layer must be etched more than 7000A. In this case, the standard deviation(3 σ) is larger than that of conducting materials, as more than 20 nm. We have results of optimum condition of alignment key in order to enhance the overlay accuracy. The standard deviation(3 σ) of total overlay accuracy is less than 50nm which corresponds to 150nm design rules device fabrication.

We have investigated the effect of line edge roughness (LER) of active patterns used for shallow trench isolation to the electrical performance of MOS transistor applicable for 1 giga-bit DRAM. Three different processes for resist patterning were applied for comparative analysis to form the active pattern in MOS transistor; the first method applied a conventional single layer resist (SLR) process, the second TIPS with two step dry development, and the third another TIPS with three step dry development. The third process adopted an additional step to break-through thin silicon dioxide which may contribute to the LER. The LER data of an active pattern before and after nitride substrate etching and their profiles were investigated among these processes. The third method shows the almost same LER and CD uniformity of the active pattern as those of SLR. The electrical properties. Only, threshold voltage variation of MOS transistor by the second method shows the worse results than those of SLR. Considering the ratio of LER in isolated active pattern with channel width of 0.3 micrometers to its average CD value, we think that its ratio should be controlled well below 7 percent for TIPS to make an useful technology for real device. Based on these studies, we believed that the well-controlled TIPS process using three step dry development is a strong candidate for device production of ArF and EUV lithography, if the advantages of TIPS technology over the SLR process are considered in the respect of lithography.