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Device scaling of oxide-channel thin-film transistors (TFTs) toward sub-micrometer regime has been an urgent issue to realize higher-resolution displays and 3-D structured electronic devices. The channel-shortening effect is a serious problem in implementing the oxide TFTs with short channel lengths. In this work, the short-channel effects (SCEs) of the In-Ga-Zn-O (IGZO) TFTs were investigated with the variations in channel composition when the channel length was varied from 3 μm to 500 nm. Effective channel lengths were examined to decrease with increasing the In contents, in which the reduction of the effective channel length was estimated to be 240 and 720 nm when the In/Ga ratio increased 0.7 to 1.4. The drain bias-dependent roll-offs in turn-on voltages, which typically correspond to drain-induced barrier-lowering (DIBL), also showed significant channel composition dependence. When the In/Ga ratio within the channel increased from 0.2 to 1.4, the DIBL coefficients were estimated from 22 to 244 mV/V for the devices with a channel length of 1 μm. The channel composition-dependent variations in the effective channel length were suggested to result from the inter-diffusion and redox reactions at interfaces between the channel and electrode layers. Alternatively, the contact resistances were also examined to play major roles in determining the SCEs with scaling the devices, especially when the In contents decreased in the channel composition. Thus, properly controlling the channel composition can be concluded as such an important issue for compromising both technical strategies to reduce the channel resistance and to suppress the reduction of effective channel length.

Thin-film transistor (TFT)-driven full-color organic light-emitting diodes (OLEDs) with vertically stacked structures are developed herein using photolithography processes, which allow for high-resolution displays of over 2,000 pixels per inch. Vertical stacking of OLEDs by the photolithography process is technically challenging, as OLEDs are vulnerable to moisture, oxygen, solutions for photolithography processes, and temperatures over 100 °C. In this study, we develop a low-temperature processed Al2O3/SiNx bilayered protection layer, which stably protects the OLEDs from photolithography process solutions, as well as from moisture and oxygen. As a result, transparent intermediate electrodes are patterned on top of the OLED elements without degrading the OLED, thereby enabling to fabricate the vertically stacked OLED. The aperture ratio of the full-color-driven OLED pixel is approximately twice as large as conventional sub-pixel structures, due to geometric advantage, despite the TFT integration. To the best of our knowledge, we first demonstrate the TFT-driven vertically stacked full-color OLED., To realize organic light-emitting diodes (OLEDs) with improved resolution for display applications, a method for achieving high yield device fabrication is needed. Here, the authors report vertically-stacked transistor-driven full-color OLEDs with photolithography-processed intermediate electrodes.

From the very first time that graphene was used as a transparent electrode for OLED applications, the emergence of active-matrix (AM)-graphene OLED displays has been envisioned. Realizing this expectation, however, turned out to be difficult. Two obstacles are the growth and transfer of a large-area graphene film and the patterning of a graphene film into pixels. To solve these problems, a process of patterning a graphene film without surface contamination was developed. The fabrication of OLED panels by the patterned graphene anode on Gen 2(370 × 470 mm)-sized and flexible substrates was successfully demonstrated. In this work, oxide TFT arrays were combined as a switching backplane, and a pixelated graphene OLED was used as an emissive layer, to realize AM-graphene OLED displays. To explore the technical feasibility of flexible AM-graphene OLED displays, the aforementioned components were formed on a flexible substrate. For commercial-level production, all the processes that were used were chosen to be compatible with the conventional display processes.

We developed a high definition holographic display with two different approaches. First approach is to adjust a wellknown display technology using a liquid crystal as an optical modulator. While merit of display technology is a large panel size, the challenge is to define a small pixel pitch and to reduce a crosstalk effect of a liquid crystal. Second approach is to adapt a silicon technology with a new optical modulator, Ge2Sb2Te5. Although we can easily define a small pixel pitch, we have to confront a small panel size. We will explain our solutions to overcome these issues.

Holographic display is known as the most realistic 3D display by creating real 3D image in front of observer. But there are tremendous technical hurdles in realizing electronic hologram. It is required to achieve very small pixel pitch SLM (spatial light modulator) for realizing electronic hologram using flat panel display. All the components of the unit pixel should be carefully redesigned and improved to maintaining same performance in spite of reduction of pixel pitch. The size of hologram image depends on the size of SLM. Therefore, the resolution of the SLM increases very fast as the reduction of pixel pitch in SLM. The driver chip and architecture should be developed to manage the large number of pixels with high speed. Novel unit pixel design for achieving 1μm pixel pitch will be presented. VST (vertically stacked transistor) structure will be introduced. In VST structure, the driving TFT is stacked on the data line. VST structure has the merits for reducing horizontal pixel pitch without introducing expensive high-definition lithography tool. The technology compatible with 0.5μm critical dimension can be used for fabrication of 1μm pixel pitch SLM. Alternative structure for achieving small pitch pixel is the adopting VTFT (vertical channel thin film transistor). VTFT means that the channel direction is vertical to SLM plane. The footprint of VTFT is very small, for required area is only the overlap region of active layer and source/drain layer. Cross-talk between adjacent pixels can interfere the rotation of LC molecule. This phenomenon will be very critical for accurate phase modulation for 1μm pixel pitch SLM. Novel concept for reducing cross-talk will be also presented with experimental results.

A phase modulation device was proposed for the implementation of hologram image for display applications. A Ge2Sb2Te5 (GST) film as thin as 7 nm was prepared between the ITO films to form the cavities corresponding a unit pixel. Nitrogen was incorporated into the GST for improving the thermal stability of the GST active region. The effects of the nitrogen doping on the physical properties of GST was investigated with the variations in doping amounts. The nitrogen incorporation was found to reduce the surface micro-roughness and to improve the thermal stability of the GST even after the crystallization by effectively suppressing the excessive grain growth. As results, the number of repeatable operations for the fabricated phase modulation device was evidently improved from 10 to 69 cycles when a 2.7-at% nitrogen was doped into the GST.

We present high-mobility back channel etch Al–In–Zn–Sn–O/In–Zn–O (IZO) double-layer channel thin-film transistors (TFTs). The field-effect mobility of 53.2 $\text{cm}^{2}/\text{V} \cdot \text{s}$ , threshold voltage of 0.5 V, and subthreshold swing of 0.15 V/decade were obtained with a thin IZO-inserted double-layer channel TFT. The positive bias stability was improved with an IZO-inserted double-layer channel. We fabricated 13-stage ring oscillators, which exhibited an oscillating frequency of 296 kHz at ${V} _{\text {DD}} = {20}$ . These results demonstrate that the proposed double-layer channel oxide TFT can be used for demanding applications such as backplane devices for ultrahigh resolution display.

Holographic projection displays provide high diffraction efficiency. However, they have a limited projection angle. This work proposes a holographic projection display with a wide angle, which gives an image of size 306 m m × 161 m m at 700 mm and reduced speckle noise. The solution uses single Fourier lens imaging with a frequency filter and hologram generation utilizing complex coding and nonparaxial diffraction. The experiment was performed with a 4K phase-only spatial light modulator (SLM) to prove the high efficiency of the developed numerical tools. Optical reconstruction shows high resolution and high image quality achieved from a single frame. Hence, displaying video at a full frame rate of the SLM is possible.

We fabricated high performance 2-µm-channel oxide thin-film transistors (TFT) on glass substrate for 7-μm-pixel-pitch spatial light modulator (SLM) panel for digital holographic applications. Furthermore, we succeeded in the demonstration of the sub-micron TFTs, which is an inevitable route to the next-generation spatial light modulation devices with near 1-μm pixel pitch.

The mechanism of formation of metal–oxide–metal (M–O–M) bonds in solution-processed metal oxide semiconductors can vary depending on the types of precursors used. To date, metal-alkoxides or metal-chloride precursors have mainly been studied; therefore, efforts to improve the device characteristics of oxide thin-film transistors (TFTs) have been limited to these types of precursors. On the other hand, systematic studies to optimize the experimental conditions (e.g. thickness and annealing atmosphere) of oxide TFTs made by using new types of precursors have rarely been reported. In this study, we successfully demonstrate high-performance solution-processed Zn–Sn–O TFTs by using a metal-carboxylate precursor, tin(II) 2-ethylhexanoate, and optimizing the oxide thickness and thermal annealing conditions. To determine the optimum thickness of Zn–Sn–O, we prepared 3 types of active layers with different thickness combinations of ZnO and SnO2. In addition, we found that oxygen gas in the annealing process maximizes the formation of M–O–M bonds and decreases the number of trap sites in the thickness-optimized active layer, leading to dramatically enhanced device performances. As a result, the optimized Zn–Sn–O TFTs based on tin(II) 2-ethylhexanoate exhibit excellent mobility exceeding 22 cm2 V−1 s−1, which is an order of magnitude higher than that of the previously reported Zn–Sn–O TFTs based on the same precursor and very comparable to the mobility levels obtained from conventional solution-processed metal-oxide TFTs. We believe that our approach will enrich the current family of tin precursors and provide another option for resource-friendly, low-cost, and high performance Zn–Sn–O semiconductors.

A switchable diffraction device capable of driving with segment electrodes has been proposed and its operating characteristics were analyzed. The switchable diffraction device is based on a variable cavity structure using reversible electrodeposition technology and two kinds of diffraction gratings are designed to be selectively switched according to the driving electrode. The fabricated device was able to switch the diffraction patterns without any interference between the electrodes, which means that the interference between the electrodes will not be a problem in further device integration with driving circuits. However, when the electrode isolation is not perfect due to parasitic resistance between the electrodes, a weak interference between the electrodes is observed in the diffraction pattern. Therefore, it is expected that ensuring complete insulation between the electrodes will be a very important in the integration of the device. The proposed device can be used as a light control device, an image switchable hologram, etc. Furthermore, it is expected to be applied to reconfigurable metasurfaces through integration with active matrix circuits in the future.

A spatial light modulator (SLM) is the key component for a digital holographic display system. It requires both ultrahigh- resolution fine pixel integration and large-area panel to get a wide viewing angle and large realistic 3D images. Because these requirements collide with each other, it is very difficult to develop the digital holography system satisfying the standard of the general public. Unlike conventional SLMs, which are based on small size semiconductor ICs, we have developed larger size, highresolution SLM on glass (SLMoG) using both semiconductor and display fabrication technologies. 1-μm channel length oxide TFTs are integrated for pixel switching and the liquid crystal (LC) of high refractive index anisotropy was used to modulate the phase of incident light. Multiple high-speed interface boards and large channel driver ICs are used to drive large size holographic image data. 2.16-inch 16K SLMoG panel with 3-μm horizontal pixel pitch was successfully developed for the first time. Without the aid of additional instruments, it was possible to observe a simple 3D objects with the naked eye. For even wider viewing angle and larger size SLMoG, the proof of concept SLMoG panel for still image hologram with smaller pixel pitches was developed to evaluate cross-talk between adjacent LC pixels.

In this paper, a new light-adaptable display (LAD) structure with minimum power consumption is proposed for the future advertising service, and the demonstrated results are reported. An organic light-emitting diode with color reflection (colored OLED) was applied for the reflective- and emissive-mode device, and a guest-host liquid-crystal device (GH-LC) was adopted for the light shutter device. The current efficiency and reflectance of the colored OLED were 35.15 cd/A at 457 cd/m2 luminance and 63% for the yellow color, respectively. The measured contrast ratio of GH-LC was 15.5:1 at dark-room conditions, respectively. Transparent oxide thin-film transistors were used for the backplane, and their average mobility was 9.08 cm2/V s, with a 0.5 standard deviation. Through the optimization of the fabrication process and the structures of each device, the LAD adaptively operating according to the environmental illuminance from dark to 10,000 nits was successfully demonstrated. Moreover, a new LAD driv...

We fabricated high performance back channel etch (BCE) IZO/AIZTO double-layer channel oxide thin-film transistors (TFTs) and analyzed their electrical characteristics and photostability of the devices. The field-effect mobility of 53.2 cm2/Vs was obtained, and we expect IZO/AIZTO double-layer BCE TFT can be used as a backplane devices for next generation high performance display applications.

New circuit architecture composed of nonvolatile memory thin-film transistors (M-TFTs) and oxide–semiconductor TFTs (Ox-TFTs) has been proposed to realize low-power consumption and compact size for dynamic driving circuit applications. In order to compensate the slow operation speed of the nonvolatile M-TFTs in the dynamic driving circuits, we proposed the read-out modulation (ROM) scheme. The device operation characteristics of the M-TFTs were confirmed under various specified conditions to effectively apply the ROM, in which a top-gate structure was fabricated to be ferroelectric poly(vinylidene fluoride-trifluoroethylene) gate insulator/Al2O3/In–Ga–ZnO active layers. Full fabrication processes for the M-TFTs were optimized, so that they can be integrated with Ox-TFTs on the same glass substrate. The memory device characteristics, including the current ratios between ON- and OFF-programmed drain current ( $I_{D}$ ) values ( $I_{p-\mathrm {\mathrm{\scriptscriptstyle ON}}}/I_{p-\mathrm {\mathrm{\scriptscriptstyle OFF}}})$ before and after the ROM, drain-bias dependence of the $I_{p-\mathrm {\mathrm{\scriptscriptstyle ON}}}/I_{p-\mathrm {\mathrm{\scriptscriptstyle OFF}}}$ , and the program $I_{D}$ scalability, were confirmed for the fabricated M-TFT. These results suggest the feasibility of a low-power display driver circuit embedded with the nonvolatile M-TFTs.

Technical strategies for improving the device characteristics of the In–Ga–Zn-O (IGZO) vertical channel thin-film transistors (VTFTs) were presented and investigated. The vertical sidewall was constructed by dry-etch process and subsequently covered with IGZO, Al2O3, and AZO as active, gate insulator, and gate electrode layers by means of conformal atomic-layer-deposition. An abrupt profile and flat back-channel were achieved by employing the spin-coated polyimide (PI) spacer. The Off-current was additionally alleviated simply by cutting the area of an active layer. The fabricated IGZO VTFT using PI spacer with an “active-cut” structure exhibited an On/off ratio of $10^{3}$ , a linear mobility of 7.1 cm2/Vs, and a subthreshold swing of 1.2 V/decade.

We propose rewritable full-color computer-generated holograms (CGHs) based on color-selective diffraction using the diffractive optical component with the resonant characteristic. The structure includes an ultrathin layer of phase-change material Ge2Sb2Te5 (GST) on which a spatial binary pattern of amorphous and crystalline states can be recorded. The CGH patterns can be easily erased and rewritten by the pulsed ultraviolet laser writing technique owing to the thermally reconfigurable characteristic of GST. We experimentally demonstrate that the fabricated CGH, having a fine pixel pitch of 2 μm and a size of 32.8 × 32.8 mm2, reconstructs the three-dimensional holographic images. In addition, the feasibility of the rewritable property is verified by erasing and rewriting part of the CGH.

SLM (Spatial Light Modulator) with ultra fine pixel pitch (circa 1 micron meter) has been thought as a big issue to realize electronic hologram with wide viewing angle. Two types of approach are proposed for accomplish SLM panel with 1 micron meter pitch pixel. SLM with LC light modulator controlled by TFT based backplane constructed on glass substrate is proposed according to the methods of scaling down flat-panel display technology. Introduction of sub micron meter patterning processes, the SLM panel with 3 micron meter pitch pixel was successfully developed for the first time. The SLM with 2 inch diagonal length had the resolution of 16K by 2K. Hologram with depth was reconstructed with manufactured SLM. Oxide semiconductor TFTs of 1 micron meter channel length with high performance have been developed for the SLM. Technical issues to accomplish 1 micron meter pitch pixel will be discussed. PCM (phase change material) has been used for memory devices and information recording devices. In former case, information is recorded and read using electrical signal. For latter case, information is recorded and read using light (laser) signal. We propose a SLM with PCM such that information is recorded using electrical signal and read using light signal. The light modulation of PCM pattern recorded by pulsed laser was successfully demonstrated using reconstruction of hologram images. Operation of arrayed pixels with PCM pattern driven by Si MOSFET is under development. Technical challenges for SLM with PCM will be discussed.

For environmental reason, buildings increasingly install smart windows, which can dim incoming daylight based on active electrochromic devices (ECDs). In this work, multi-layered graphene (MLG) was investigated as an ECD window electrode, to minimize carbon dioxide (CO2) emissions by decreasing the electricity consumption for building space cooling and heating and as an alternative to the transparent conductor tin-doped indium oxide (ITO) in order to decrease dependence on it. Various MLG electrodes with different numbers of graphene layers were prepared with environmentally friendly poly(3,4-ethylenedioxythiophene):poly(styrene-sulfonate) (PEDOT:PSS) to produce ECD cells. Tests demonstrated the reproducibility and uniformity in optical performance, as well as the flexibility of the ECD fabrication. With the optimized MLG electrode, the ECD cells exhibited a very fast switching response for optical changes from transparent to dark states of a few hundred msec.

We report the electrical characteristics of backchannel etch (BCE) metal–oxide–semiconductor thin-film transistor (TFT) comprised of aluminum-doped tin–zinc–indium oxide (ATZIO). It has high etch selectivity in wet chemical etchants, which consist of H3PO4, CH3COOH, and HNO3. This is contrary to the conventional metal–oxide–semiconductors of indium–gallium–zinc oxides, which are highly soluble in the acidic chemicals. As a result, no etch stop layer is needed to protect the backchannel from the wet etchant damage during the source and drain patterning in the bottom-gate-staggered TFT structure. This provides the possibility of oxide TFT fabrication process made as simple as that of the current amorphous silicon TFT using three or four photomasks with short channel length and less parasitic capacitance. The electrical characteristics of our ATZIO BCE-TFTs have the mobility of 21.4 cm2/ $\text{V}\cdot \text{s}$ , subthreshold swing (S.S) of 0.11 V/decade, and threshold voltage of 0.8 V. In spite of the BCE structure, they have excellent stability against bias temperature stress, which shows the threshold voltage shifts of +0.75 V and −0.51 V under the prolonged positive (+20 V) and negative (−20 V) gate bias stresses for 10 000 s at 60 °C, respectively.

Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 10 7 was obtained, and a memory margin of 6.6 × 10 3 was retained even after the lapse of 10 5 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

Wide band gap metal oxide semiconductor TFTs will play a major role in the development of the high resolution and high performance flat panel display. Metal oxide semiconductor TFTs with high mobility and good stability were developed at ETRI through extensive investigation of the materials, device structure, and interface engineering.

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Amorphous indium gallium zinc oxide thin-film transistors (TFTs) were fabricated and characterized on flexible poly(ethylene naphthalate) (PEN) substrates. A hybrid inorganic/organic double-layered barrier layer structure was proposed for enhancing the permeability and the surface roughness of the PEN substrates, which was composed of a 3 μm-thick spin-coated organic layer and a 50 nm-thick atomic-layer-deposited Al2O3 inorganic layer. The saturation mobility, subthreshold swing, and on/off ratio of the TFTs on the PEN substrates with the proposed hybrid barrier structure were found to be approximately 15.5 cm2 V−1 s−1, 0.2 V dec−1, and 2.2 × 108, respectively. These good TFT performances were not degraded even under the mechanical bending situation at a curvature radius of 3.3 mm and after the repetitive bending cycles. Furthermore, the variations in turn-on voltage of the TFT were evaluated to be approximately as small as −0.1 and +1.6 V under the negative and positive-bias stress tests, respectively.

Active matrix organic light-emitting diodes (AMOLEDs) are considered to be a core component of next-generation display technology, which can be used for wearable and flexible devices. Reliable thin-film transistors (TFTs) with high mobility are required to drive AMOLEDs. Recently, amorphous oxide TFTs, due to their high mobility, have been considered as excellent substitutes for driving AMOLEDs. However, the device instabilities of high-mobility oxide TFTs have remained a key issue to be used in production. In this paper, we present the charge-trapping and device instability mechanisms of high-mobility oxide TFTs with double active layers, using In-Zn-O (IZO) and Al-doped Sn-Zn-In-O (ATZIO) with various interfacial IZO thicknesses (0-6 nm). To this end, we employed microsecond fast current-voltage (I-V), single-pulsed I-V, transient current, and discharge current analysis. These alternating-current device characterization methodologies enable the extraction of various trap parameters and defect densities as well as the understanding of dynamic charge transport in double-active-layer TFTs. The results show that the number of defect sites decreases with an increase in the interfacial IZO thickness. From these results, we conclude that the interfacial IZO layer plays a crucial role in minimizing charge trapping in ATZIO TFTs.

The development of digital holography is anticipated for the viewing of 3D images by reconstructing both the amplitude and phase information of the object. Compared to analog holograms written by a laser interference, digital hologram technology has the potential to realize a moving 3D image using a spatial light modulator. However, to ensure a high-resolution 3D image with a large viewing angle, the hologram panel requires a near-wavelength scale pixel pitch with a sufficient large numbers of pixels. In this manuscript, we demonstrate a digital hologram panel based on a chalcogenide phase-change material (PCM) which has a pixel pitch of 1 μm and a panel size of 1.6 × 1.6 cm2. A thin film of PCM encapsulated by dielectric layers can be used for the hologram panel by means of excimer laser lithography. By tuning the thicknesses of upper and lower dielectric layers, a color-selective diffraction panel is demonstrated since a thin film resonance caused by dielectric can affect to the absorption and diffraction spectrum of the proposed hologram panel. We also show reflection color of a small active region (1 μm × 4 μm) made by ultra-thin PCM layer can be electrically changed.

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain.

A scan driver circuit that generates stable output waveforms with the depletion-mode oxide thin-film transistor (TFT) is reported. The output waveforms of the conventional scan driver deteriorate as the threshold voltage of the TFT becomes negative. For the proper operation of a scan driver circuit composed of oxide TFTs, the TFTs in the circuit should be turned off with negative gate-to-source bias. In addition, the output of each stage should not be affected by the adjacent stages. In this study, a new scan driver circuit that satisfies these two criteria was designed and fabricated. The new scan driver circuit works successfully and exhibits no ripple in the output waveforms even though the threshold voltage of the TFTs is as low as −3 V.

For this research, we have developed key technologies for a 1.5 µm pixel pitch spatial light modulator (SLM) using Ge2Sb2Te5 (GST) phase change material. To uniformly modulate each pixel, we designed a lateral pixel structure in which a heating current flows through a bottom indium tin oxide layer. To check hologram reconstruction both after multilevel fabrication processes and before implementing full source and driver circuits, we fabricated an 8K×2K hologram on the topology by changing the GST film's phase using laser irradiation. To overcome the limitation of SLM size, we tested a physical tiling structure and found that flatness of tiled SLMs was the most important factor in the realization of holographic displays.

A new pixel architecture and driving scheme for a low-power liquid crystal display (LCD) with a low refresh-rate is proposed. The proposed pixel architecture comprises two oxide thin-film transistors (Ox-TFTs), two ferroelectric memory TFTs (Fe-MTFTs), and two capacitors. Both TFTs have the same indium gallium zinc oxide film as an active layer. The Fe-MTFT exhibits a hysteresis property owing to the ferroelectric gate insulator that enables it to operate as a memory. A prototype LCD with 6 $\times $ 5 pixels is fabricated in this letter. The field-effect mobility of Ox-TFTs is 11 cm $^{\mathrm {\mathbf {2}}}\text{V}^{\mathrm {\mathbf {-1}}}\text{s}^{\mathrm {\mathbf {-1}}}$ . The memory window of Fe-MTFT is 5 V with a gate-voltage sweep from −20 to 20 V. After programming the Fe-MTFTs, the fabricated LCD successfully operates at a 0.5-Hz refresh-rate.

We report the simplest shift register circuit compatible with metal-oxide thin-film transistors (TFTs). Since the oxide TFT often exhibits depletion-mode characteristic, it is impossible to guarantee stable operation of the shift register when we resort to conventional circuit scheme. In order to resolve this problem, we employed two different low-voltage levels for the clock signals. As a result, we could turn off the depletion-mode oxide TFTs completely with sufficient voltage margin. According to the simulation results, the new shift register composed of only 6 TFTs operates properly over the threshold voltage (VT) range of −5–+9 V. The fabricated circuit also worked successfully even though VT of the TFTs ranged from −5 V to −3 V.

In oxide thin-film transistors (TFTs), light illumination effect is a big concern due to its operating condition. Light illumination can change many electrical properties in oxide TFTs such as mobility and threshold voltage (V th ). In many researches, Oxygen vacancy is suspected as a main cause of the changes by light illumination. Recently, the back channel formation by field-induced macroscopic barrier model is reported under light illumination. This is also related to Oxygen vacancy. In this letter, we investigate the gradual changes in DC and CV characteristics depending on the dual-channel thicknesses. For this purpose, we use the aluminum-doped indium zinc tin oxide (AIZTO)/indium zinc oxide (IZO) dual-channel TFTs. The main goal of this paper is to find the main cause of the changes by light illumination in various dual-channel thicknesses.

The effects of electrode materials on the device stabilities of In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) were investigated under gate- and/or drain-bias stress conditions. The fabricated IGZO TFTs with a top-gate bottom-contact structure exhibited very similar transfer characteristics between the devices using indium-tin oxide (ITO) and titanium electrodes. Typical values of the mobility and threshold voltage of each device were obtained as 13.4 cm(2) V(-1) s(-1) and 0.72 V (ITO device) and 13.8 cm(2) V(-1) s(-1) and 0.66 V (titanium device). Even though the stabilities examined under negative and positive gate-bias stresses showed no degradation for both devices, the instabilities caused by the drain-bias stress were significantly dependent on the types of electrode materials. The negative shifts of the threshold voltage for the ITO and titanium devices after the 10(4)-s-long drain-bias stress were estimated as 2.06 and 0.96 V, respectively. Superior characteristics of the device using titanium electrodes after a higher temperature annealing process were suggested to originate from the formation of a self-limiting barrier layer at interfaces by nanoscale observations using transmission electron microscopy.

Transparent zinc tin oxide thin-film transistors (ZTO-TFTs) [Zn:Sn = 4:1-2:1] have been fabricated so as to estimate the electrical instability under constant current stress. The relative intensity of the drain current noise power spectra density has been shown to have a typical 1/f-noise character, and it is implied that the mobility fluctuation in ZTO-TFT [Zn:Sn = 4:1] can be enhanced by a short-range ordering in amorphous Zn-Sn-oxide, causing a larger shift of the threshold voltage (deltaV(th)).

The effects of zinc on the zinc-doped CaTiO 3 :Pr 3+ phosphors have been investigated by varying the zinc concentrations from 0 to 100 mol%. The variation of zinc concentration influences the crystallinity and morphology of the phosphors. The crystallinity and PL intensity increase as zinc content increases from 0 to 25 mol%. (Zn,Ca)TiO 3 :Pr 3+ at 25 mol% Zn exhibits nearly 3.6 times enhanced PL intensity compared to CaTiO 3 :Pr 3+ . Moreover, the red emitting phosphor developed in this study can be very effectively excited at the wavelengths of 400 nm. We think that (Zn,Ca)TiO 3 :Pr 3+ can be used as a complementary phosphor in the red region for the white LEDs.

Using ZnO, and three compositional In 2 O 3 -Ga 2 O 3 -ZnO (IGZO, In:Ga:Zn=1:1:1, 2:1:2, 2:2:1, atomic ratio) semiconductors, we have made and evaluated several double layered oxide thin-film transistors (TFTs). The drain current was mainly affected by the nearer channel material to a gate insulator. From the positive bias stress (PBS) tests, however, the electrical stability showed a complicated result, depending on both channel structures and post-heat treatments.

An organic/inorganic hybrid dual-gate (DG) nonvolatile memory thin-film transistor (M-TFT) was proposed as a device with high potential for implementing large-area electronics on flexible and/or transparent substrates. The active channel and bottom and top gate insulators (GIs) of the M-TFT were composed of In-Ga-Zn-O, Al2O3, and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)], respectively. It was confirmed that the fabricated DG M-TFT showed excellent device characteristics, in which the obtained field-effect mobility, subthreshold swing, and on/off ratio were approximately 32.1 cm2 V-1 s-1, 0.13 V/dec, and 108, respectively. It was also successfully demonstrated that the DG configuration for the proposed M-TFT could effectively work for improving the device controllability by individually controlling the bias conditions of the top gate and bottom gate (BG). The turn-on voltage could be dynamically modulated and controlled when an appropriate fixed negative voltage was applied to the BG. The required duration of the programming pulse to obtain a memory margin of more than 10 could be reduced to 100 μs. These results correspond to the first demonstration of a hybrid-type DG M-TFT using a ferroelectric copolymer GI/oxide semiconducting active channel structure and demonstrate the feasibility of a promising memory device embeddable in a large-area electronic system.

Employment of the memristor for the next-generation large-area electronics can be expected to release various devices with interesting functions. In this article, for the first time we proposed a fully transparent memristor cell, which was composed of one-memory thin-film transistor (TFT) and one-switch TFT using an oxide semiconducting active channel. A poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] was used as a gate insulator for the memory TFT and the channel conductance of the TFT was modulated by changing the quantity and direction of ferroelectric polarization. The fabrication procedures were designed so that the proposed transparent memristor cell could be implemented at process temperature below 200°C. It was successfully conformed that the fabricated memristor cell exhibited good TFT behaviors and modulated output characteristics programmed into the memory TFT.

This paper reports on the structural and optical properties of ZnCuO thin films that were prepared by co-sputtering for the application of p-type-channel transparent thin-film transistors (TFTs). Pure ceramic ZnO and metal Cu targets were prepared for the co-sputtering of the ZnCuO thin films. The effects of the Cu concentration on the structural, optical, and electrical properties of the ZnCuO films were investigated after their heat treatment. It was observed from the XRD measurements that the ZnCuO films with a Cu concentration of 7% had ZnO(002), Cu2O(111), and Cu2O(200) planes. The 7% Cu-doped ZnO films also showed a band-gap energy of approximately 2.05 eV, an average transmittance of approximately 62%, and a p-type carrier density of approximately 1.33 x 10(19) cm-3 at room temperature. The bottom-gated TFTs that were fabricated with the ZnCuO thin film as a p-type channel exhibited an on-off ratio of approximately 6. These results indicate the possibility of applying ZnCuO thin films with variable band-gap energies to ZnO-based optoelectronic devices.

We propose a memory-in-pixel (MIP) circuit to reduce the power consumption of liquid crystal displays (LCDs). With the property of ferroelectric TFT (FeTFT), a simple structure with low operating frequency is achieved. Its feasibility is confirmed by SPICE simulation.

We report highly stable and high mobility aluminum-doped indium zinc tin oxide (AIZTO) thin-film transistor with field effect mobility larger than 30 cm2/Vs in the bottom gate, etch-stopper structure. The electrical instabilities against positive gate bias stress, negative gate bias stress, and negative gate bias under illumination stress are investigated..

We proposed a charge-trap-type memory transistor with a top-gate structure composed of Al2O3 blocking/ZnO charge-trap/IGZO active/ Al2O3 tunneling layer. The memory ON/OFF ratio higher than six-orders-of magnitude was obtained after the programming when the width and amplitude of program pulses were 100 ms and ±20 V, respectively. Excellent endurance was successfully confirmed under the repetitive programming with 104 cycles. The memory ON/OFF ratio higher than 103 was guaranteed even after the lapse of 104 s. Interestingly, the retention properties were affected by the bias conditions for read-out operations.

Vertical channel ZnO thin-film transistors (TFTs) were fabricated on glass and flexible substrates. Conformally deposited thin films prepared using atomic layer deposition were used for the active layer, gate insulator, and gate electrode. Owing to the very short channel (0.5 μm) and very thin (20 nm) gate insulator layer, the ON-current of the vertical channel ZnO TFT was 57 μA at the gate and drain voltages of 3 and 4 V, respectively. Vertical channel oxide TFTs may be promising for device applications with low power consumption.