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Ternary content addressable memory (TCAM) is one type of associative memory and has been widely used in caches, routers, and many other mapping-aware applications. While the conventional SRAM-based TCAM is high speed and bulky, there have been denser but slower and less reliable nonvolatile TCAMs using nonvolatile memory (NVM) devices. Meanwhile, some CMOS TCAMs using dynamic memories have been also proposed. Although dynamic TCAM could be denser than the 16T SRAM TCAM and more reliable than the nonvolatile TCAMs, CMOS dynamic TCAMs still suffer from the row-by-row refresh energy and time overheads. In this article, we propose dynamic TCAM using nanoelectromechanical (NEM) relays (DyTAN), and utilize one-shot refresh (OSR) to solve the memory refresh problem. By exploiting the unique NEM relay characteristics, DyTAN outperforms the existing works in the balance between density, speed, and power efficiency. Compared with the 16T SRAM-based TCAM, the 5T CMOS dynamic TCAM, the 2T2R TCAM, and the 2FeFET TCAM, evaluations show that the proposed DyTAN reduces the write energy by up to $2.3\times $ , $1.3\times $ , $131\times $ , and $13.5\times $ , and improves the search energy-delay-product (EDP) by up to $12.7\times $ , $1.7\times $ , $1.3\times $ , and $2.8\times $ , respectively.

Structured light (SL) based three-dimensional (3D) imaging technology has been widely employed in many fields of computer vision. However, currently available SL based depth sensors are sensitive to imaging noises, which severely limits the performance of subsequent advanced vision tasks. In this letter, we propose a robust and practical SL illumination pattern coding method based on epipolar geometry. The proposed pattern can effectively alleviate coding redundancy in traditional global random speckle SL patterns and make the stereo matching more robust to noise. Meanwhile, this coding strategy supplies sufficient non-local similar blocks, which inspires us to propose a uni-direction block-stacking 3D filtering algorithm to further improve the 3D imaging quality. To verify the proposed algorithms, we developed a prototype using the off-the-shelf projector and camera. Both simulation and real scene experimental results show that the proposed methods can achieve high-quality 3D imaging performance under different noisy conditions.

This brief presents the concept of one-shot refresh (OSR) for dynamic memories. The uniqueness of OSR that differs from the conventional row-by-row refresh operations, is that OSR is able to refresh all rows in the entire array by just one single refresh without the need to read out the stored data in each row. By doing so, significant energy savings could be achieved, and the time window accessible for regular read and write operations is widened with less disruption by the refresh traffic. We show that a few devices could be used to update existing designs to gain the OSR capability. These devices all exhibit hysteretic I-V characteristics and support the OSR data-independent refresh without the need to read out data first. The enabler is the proposed circuit technique for refresh and standby. As a proof of concept, we showcase an OSR-enabled embedded dynamic random-access memory (eDRAM) using the nano-electromechanical (NEM) relay, a type of CMOS-compatible device. Comparative evaluations show the merits of OSR more thoroughly.

Purpose The smart image sensor (SIS) which integrated with both sensor and smart processor has been widely applied in vision-based intelligent perception. In these applications, the linearity of the image sensor is crucial for better processing performance. However, the simple source-follower based readout circuit in the conventional SIS introduces significant nonlinearity. This paper aims to design a low-power in-pixel buffer circuit applied in the high-linearity SIS for the smart perception applications. Design/methodology/approach The linearity of the SIS is improved by eliminating the non-ideal effects of transistors and cancelling dynamic threshold voltage that changes with the process variation, voltage and temperature. A low parasitic capacitance low leakage switch is proposed to further improve the linearity of the buffer. Moreover, an area-efficient SIS architecture with a sharing mechanism is presented to further reduce the number of in-pixel transistors. Findings A low parasitic capacitance low leakage switch and a gate-source voltage pre-storage method are proposed to further improve the linearity of the buffer. Nonlinear effects introduced by parasitic capacitance switching leakage, etc., have been investigated and solved by proposing low-parasitic and low-leakage switches. The linearity is improved without a power-hungry operational amplifier-based calibration circuit and a noticeable power consumption increment. Originality/value The proposed design is implemented using a standard 0.18-µm CMOS process with the active area of 102 µm2. At the power consumption of 5.6 µW, the measured linearity is −63 dB, which is nearly 27 dB better than conventional active pixel sensor (APS) implementation. The proposed low-power buffer circuit increase not only the performance of the SIS but also the lifetime of the smart perception system.

Thin-film transistor (TFT) circuits are important for flexible electronics which are promising in the area of wearable devices and Internet of Things. However, most flexible TFT technologies only have unipolar devices and the process variation and defective rate are relatively high, which impose challenges to TFT circuit design. In this paper, we propose a novel logic array design based on pseudo-CMOS logic to address the problems of unipolar TFT circuit design. A multilayer interconnection architecture is presented to improve the routability of circuit and the area efficiency. Cell mapping and wire routing algorithms, which aim to map the logic gates of circuit to logic array and then route the interconnection wires, are devised to improve the performance of circuit in consideration of parameter variations of TFT and meanwhile enhance the routability. The experimental results show that the proposed logic array along with design methodologies can reduce more than 80% area compared with transistor level scheme and help to improve performance significantly.

Ternary content addressable memory (TCAM) has been a critical component in caches, routers, etc., in which density, speed, power efficiency, and reliability are the major design targets. There have been the conventional low-write-power but bulky SRAM-based TCAM design, and also denser but less reliable or higher-write-power TCAM designs using nonvolatile memory (NVM) devices. Meanwhile, some TCAM designs using dynamic memories have been also proposed. Although dynamic design TCAM is denser than CMOS SRAM TCAM and more reliable than NVM TCAM, the conventional row-by-row refresh operations land up with a bottleneck of interference with normal TCAM activities. Therefore, this paper proposes a custom low-power dynamic TCAM using nanoelectromechanical (NEM) relay devices utilizing one-shot refresh to solve the memory refresh problem. By harnessing the unique NEM relay characteristics with a proposed novel cell structure, the proposed TCAM occupies a small footprint of only 3 transistors (with two NEM relays integrated on the top through the back-end-of-line process), which significantly outperforms the density of 16-transistor SRAM-based TCAM. In addition, evaluations show that the proposed TCAM improves the write energy efficiency by 2.31x, 131x, and 13.5x over SRAM, RRAM, and FeFET TCAMs, respectively; The search energy-delay-product is improved by 12.7x, 1.30x, and 2.83x over SRAM, RRAM, and FeFET TCAMs, respectively., To be published in 24th Design, Automation and Test in Europe Conference (DATE) in 2021

Memristor based Processing-In-Memory (PIM) systems give alternative solutions to boost the computing energy efficiency of Convolutional Neural Network (CNN) based algorithms. However, Analog-to-Digital Converters' (ADCs) high interface costs and the limited size of the memristor crossbars make it challenging to map CNN models onto PIM systems with both high accuracy and high energy efficiency. Besides, it takes a long time to simulate the performance of large-scale PIM systems, resulting in unacceptable development time for the PIM system. To address these problems, we propose a reliability-aware training framework and a behavior-level modeling tool (MNSIM 2.0) for PIM accelerators. The proposed reliability-aware training framework, containing network splitting/merging analysis and a PIM-based non-uniform activation quantization scheme, can improve the energy efficiency by reducing the ADC resolution requirements in memristor crossbars. Moreover, MNSIM 2.0 provides a general modeling method for PIM architecture design and computation data flow; it can evaluate both accuracy and hardware performance within a short time. Experiments based on MNSIM 2.0 show that the reliability-aware training framework can improve 3.4x energy efficiency of PIM accelerators with little accuracy loss. The equivalent energy efficiency is 9.02 TOPS/W, nearly 2.6~4.2x compared with the existing work. We also evaluate more case studies of MNSIM 2.0, which help us balance the trade-off between accuracy and hardware performance.

Compute-in-memory (CiM) is a promising approach to alleviating the memory wall problem for domain-specific applications. Compared to current-domain CiM solutions, charge-domain CiM shows the opportunity for higher energy efficiency and resistance to device variations. However, the area occupation and standby leakage power of existing SRAMbased charge-domain CiM (CD-CiM) are high. This paper proposes the first concept and analysis of CD-CiM using nonvolatile memory (NVM) devices. The design implementation and performance evaluation are based on a proposed 2-transistor-1-capacitor (2T1C) CiM macro using ferroelectric field-effect-transistors (FeFETs), which is free from leakage power and much denser than the SRAM solution. With the supply voltage between 0.45V and 0.90V, operating frequency between 100MHz to 1.0GHz, binary neural network application simulations show over 47%, 60%, and 64% energy consumption reduction from existing SRAM-based CD-CiM, SRAM-based current-domain CiM, and RRAM-based current-domain CiM, respectively. For classifications in MNIST and CIFAR-10 data sets, the proposed FeFETbased CD-CiM achieves an accuracy over 95% and 80%, respectively., Comment: Accepted by IEEE Transactions on Circuits and Systems II in 2021

Flexible capacitive pressure sensing system (FCPSS) is promising in the area of healthcare, robotics, and Internet of Things (IoT). As the size of the sensing array increases, designing energy-efficient FCPSS is getting challenging. This work provides a comprehensive solution for low-power FCPSS design, where major contributions are as follows. 1) Crosstalk-induced measurement error in a crossbar structure FCPSS is first studied and an accurate and low-power linear iterative algorithm is proposed for on-chip sensing array calibration (SAC). 2) Binary Neural Network (BNN)-based spatial-temporal adaptive sensing scheme for FCPSS is first proposed to utilize the sparsity of sampling and to further improve energy efficiency. Combined with the clock-gating-friendly low-power sensor interface, the system consumes 31.39 μJ energy and gains 95.04% capacitor measurement accuracy for each sensing operation on a 10×10 array, achieving 116× energy reduction compared with the state-of-the-art technology.

Large-scale graphs play a vital role in various applications, but it is limited by the long processing time. Graph sampling is an effective way to reduce the amount of graph data and accelerate the algorithm. However, previous work usually lacks theoretical analysis related to graph algorithm models. In this study, GraphSDH (Graph Sampling with Distribution and Hierarchy), a general large-scale graph sampling framework is established based on the vertex-centric graph model. According to four common sampling techniques, we derive the sampling probability to minimize the variance, and optimize the design according to whether there is a pre-estimation process for the intermediate value. In order to further improve the accuracy of the graph algorithm, we propose a stratified sampling method based on vertex degree and a hierarchical optimization scheme based on sampling position analysis. Extensive experiments on large graphs show that GraphSDH can achieve over 95% accuracy for PageRank by sampling only 10% edges of the original graph, and speed up PageRank by several times than that of the non-sampling case. Compared with random neighbor sampling, GraphSDH can reduce the mean relative error of PageRank by about 17% at a sampling neighbor ratio (sampling fraction) of 20%. Furthermore, GraphSDH can be applied to various graph algorithms, such as Breadth-First Search (BFS), Alternating Least Squares (ALS) and Label Propagation Algorithm (LPA).

Memristor based neuromorphic computing systems give alternative solutions to boost the computing energy efficiency of Neural Network (NN) algorithms. Because of the large-scale applications and the large architecture design space, many factors will affect the computing accuracy and system's performance. In this work, we propose a behavior-level modeling tool for memristor-based neuromorphic computing systems, MNSIM 2.0, to model the performance and help researchers to realize an early-stage design space exploration. Compared with the former version and other benchmarks, MNSIM 2.0 has the following new features: 1. In the algorithm level, MNSIM 2.0 supports the inference accuracy simulation for mixed-precision NNs considering non-ideal factors. 2. In the architecture level, a hierarchical modeling structure for PIM systems is proposed. Users can customize their designs from the aspects of devices, interfaces, processing units, buffer designs, and interconnections. 3. Two hardware-aware algorithm optimization methods are integrated in MNSIM 2.0 to realize software-hardware co-optimization.

For implantable devices, miniaturization is a key design consideration, which facilitates keyhole surgery and relieves the surgical pain. Wireless power transfer is a commonly used way for implants, and a high power transfer efficiency (PTE) could help to minimize or even remove the battery inside the human body. Conventionally, the required power is delivered transcutaneously to a medical implant by inductive coupling or capacitive coupling, but the PTE is extremely low when targeting at a very small implant through a thick tissue layer. In this paper, we propose a new technique by utilizing the body tissue as the power transfer channel, where a pair of medical electrodes are attached on the body surface to supply power to a miniaturized implant with a differential input. The PTE is remarkably improved by the current loop through the body tissue without violating the IEEE specific absorption rate standard. Measurement results show that the tissue-channel technique achieves 0.39% PTE for a 1-mm-sized implant locating 5 cm deep inside the tissue.

In modern integrated circuit (IC) designs, intellectual property (IP) cores are often outsourced and designed by third-party vendors, resulting in the partial relinquishment of the control over the IC design flow. Thus, reliable verifications are required to mitigate the threat of hardware Trojans (HTs) which may be inserted into IP cores by malicious vendors. Existing trustiness verification methods cannot take the merit of high efficiency and accuracy at the same time. In this paper, we propose a multilevel fast trustiness verification framework based on feature analysis to detect HTs in third-party digital IP cores. The proposed framework combines flip-flop level and combinational logic level feature analysis to achieve both high efficiency and accuracy. Experimental results demonstrate that both explicitly and implicitly triggered HTs can be detected in very short time with a negligible false positive rate. More importantly, our framework has the unique advantage of being scalable to defend against future and stealthier HTs by adding new features into the framework.

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (B&R), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule B&R energy. This new nvDFF promises area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications.

An analog memory based on the high linearity source-follower buffer topology is proposed, which is applied to the emerging Analog Convolutional Neural Network (CNN) for buffering parameters and operation results. The proposed memory consists of a source-follower type buffer, which delivers an appreciably enhanced accuracy over that of the conventional buffer, and a storage capacitor to meet the Analog CNN processing demands of accurate short-term storage and multi-reading capability. The enhanced linearity of the proposed buffer is achieved by adopting high-threshold cascode (HTC) structure and low parasitic capacitance switch (LPCS). Moreover, a low leakage bootstrap (LLB) structure is integrated to enhance the turn-off performance of switch, which reduces the leakage and improves the accuracy of buffer significantly. Simulated with 180 nm CMOS mixed-signal process, the proposed analog memory unit achieves power consumption of 3.6 μW and output error of 0.4%, with the input voltage swing of 1.1 V .

In wireless body area network, capacitive-coupling body channel communication (CC-BCC) has the potential to attain better energy efficiency over conventional wireless communication schemes. The CC-BCC scheme utilizes the human body as the forward signal transmission medium, reducing the path loss in wireless body-centric communications. However, the backward path is formed by the coupling capacitance between the ground electrodes (GEs) of transmitter (Tx) and receiver (Rx), which increases the path loss and results in a body posture dependent backward impedance. Conventional methods use a fixed inductor to resonate with the backward capacitor to compensate the path loss, while it's not effective in compensating the variable backward impedance induced by the body movements. In this paper, we propose a self-adaptive capacitive compensation (SACC) technique to address such a problem. A backward distance detector is introduced to estimate the distance between two GEs of Tx and Rx, and a backward capacitance model is built to calculate the backward capacitance. The calculated backward capacitance at varying body posture is compensated by a digitally controlled tunable inductor (DCTI). The proposed SACC technique is validated by a prototype CC-BCC system, and measurements are taken on human subjects. The measurement results show that 9dB-16 dB channel enhancement can be achieved at a backward path distance of 1 cm-10 cm.

Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs and local nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large store energy ( $\text{E}_{\mathrm {S}}$ ) and long voltage stress time on the device ( $\text{T}_{\mathrm {STRESS}}$ ), due to wide distribution in the write time of NVM device as well as unnecessary writes. Moreover, heavy parasitic load on the power rail cause long wake-up time for restoring data from NVM to FFs. This paper proposes the resistive RAM (ReRAM)-based nvFF with self-write termination (SWT) and reduced loading on power rail to: 1) reduce 93+% waste of $\text{E}_{\mathrm {S}}$ from fast switching or matched cells; 2) suppress endurance and reliability degradation resulted from overprogramming and long $\text{T}_{\mathrm {STRESS}}$ ; and 3) achieve reliable and 26+ times faster restore operation compared with previous nvFFs. We have fabricated a nonvolatile processor and a test chip with SWT-nvFFs using logic-process ReRAM in a 65-nm CMOS process. Measured results show sub-2-ns termination response time and sub-20-ns chip-level restore time.

Flexibleelectronics based on thin-film transistors (TFTs) are promising in the area of Internet of Things and wearable devices, where the pseudo-CMOS logic is widely used in the unipolar TFT circuits. Though plenty of device models exist, analytical circuit-level models are still absent, preventing the further development of design and analysis of flexible TFT circuits. In this paper, we derive the noise margin (NM), delay, and power models for pseudo-CMOS logic circuits. Furthermore, we simplify thosemodels formanual analysis and design optimization. Allmodels are validated by SPICE simulations, where the device model and its parameters are extracted from the fabricated self-assembled monolayer organic TFTs. The average errors for NM, delay, and power models are 3%, 10%, and 3%, respectively. In addition, we exploit the delay models in a voltage-controlled oscillator design and its linearity of frequency characteristic is optimized with the proposed models, demonstrating their effectiveness.

Nonvolatile processor (NVP) attracts more and more attentions for its immunity to power loss in energy harvesting scenarios. The overall performance of an NVP is determined by its sleep and wake-up speeds, which refer to how fast the NVP can turn itself off and on when a sudden power failure occurs. To the best of our knowledge, this paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP. A hybrid CMOS/ferroelectric nonvolatile flip-flop (nvFF) and a high-speed voltage detector are designed and integrated in the proposed NVP to jointly minimize its sleep and wake-up time. Measurement results demonstrate $46~\mu \text {s}$ wake-up time and $14~\mu \text {s}$ sleep time, which is up to 18 and 24 times speedup over existing works. This approach not only improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy.

The state-of-the-art 3D shape measurement system has rather shallow working volume due to the limited depth-of-field (DOF) of conventional lens. In this paper, we propose to use the electrically tunable lens to substantially enlarge the DOF. Specifically, we capture always in-focus phase-shifted fringe patterns by precisely synchronizing the tunable lens attached to the camera with the image acquisition and the pattern projection; we develop a phase unwrapping framework that fully utilizes the geometric constraint from the camera focal length setting; and we pre-calibrate the system under different focal distance to reconstruct 3D shape from unwrapped phase map. To validate the proposed idea, we developed a prototype system that can perform high-quality measurement for the depth range of approximately 1,000 mm (400 mm – 1400 mm) with the measurement error of 0.05%. Furthermore, we demonstrated that such a technique can be used for real-time 3D shape measurement by experimentally measuring moving objects.

Memristor-based logic design gives an alternative solution to improve the energy efficiency of computing systems, benefiting from combining the memory with computing units. Inspired by this thought, previous work has demonstrated various memristor-based logic families with different attributes and computation patterns. Besides, some logic synthesis tools are designed for specific memristive logic implementations. However, the poor universality and the neglect of realistic constraints in memory largely restrict the utility of these logic synthesis tools. In this paper, we propose a general logic synthesis framework for memristor-based logic design, containing a universal abstract description method for memristive logic, a mapping rules generator, and a synthesis and mapping flow. The proposed logic synthesis framework is suitable for various types of existing memristor-based logic families and takes the memory status into consideration. It is also possible to handle future memristive devices and logic families by providing the universal abstraction interface. Furthermore, we also design a circuit-partitioning-based synthesis acceleration strategy to tackle with the long synthesis time problem. Experimental results show that, our framework can generate mapping results under the restriction of limited resource, while the existing synthesis tools may fail under the same restriction, and achieve comparable synthesis results with the same resource as the existing synthesis tools, which is enough for computation and storage. And the proposed acceleration scheme can achieve ∼ 1000× speedup compared with the initial one.

Making embedded memory symmetric provides the capability of memory access in both rows and columns, which brings new opportunities of significant energy and time savings if only a portion of data in the words need to be accessed. This work investigates the use of ferroelectric field-effect transistors (FeFETs), an emerging nonvolatile, low-power, deeply-scalable, CMOS-compatible transistor technology, and proposes a new 3transistor/cell symmetric nonvolatile memory (SymNVM). With $\sim 1.67\mathrm{x}$ higher density as compared with the prior FeFET design, significant benefits of energy and latency improvement have been achieved, as evaluated and discussed in depth in this paper.

High-precision digital-to-analog converter (DAC) is a critical component in process control, data acquisition, and testing instruments. In order to achieve high resolution and a wide-temperature range, conventional designs have been adopting high-cost thin-film resistors with laser-trimming to improve the matching property and thus the DAC resolution. In this work, targeting at lowering the cost, we propose an analog resistor redundancy, full code, and piecewise-linear calibration scheme to enable the use of low-cost poly resistors in a standard CMOS process. In order to overcome the drift over a wide temperature range, a feedback circuit is proposed to guarantee that the resistance of the switch can track the resistor with temperature changes. Therefore, the DAC can be calibrated under a specific temperature and tested under an arbitrary temperature from -40℃ to 85℃ using the same calibration codes. The 16b DAC was implemented in a 0.25μm 5V CMOS process with 5V CMOS devices and poly resistors rather than thin film resistor. The test result shows that it can achieve the INL≤0.5LSB, INL≤4LSB, and INL≤4LSB at 25℃, -40℃, and 85℃, respectively, using the same calibration code. It settles in 1μs and it has below 5nV ⋅ s glitch. The current consumption is 1.7mA from 5V voltage supplies.

Focus stacking is a promising technique to extend depth of field in general photography by fusing images captured at different focusing distances. In this paper, we propose a round-trip scene-adaptive image acquisition system to automatically capture focal stack and fuse a high quality all-in-focus image. Based on scene analysis, we cover entire depth range of the scene in the forward optical scanning and refine all objects' focusing positions accurately in the backward scanning. With captured images, we firstly extract depthmap and all-in-focus image with combination of max-gradient flow and blur kernel estimation. Secondly, a superpixel-level Gaussian Fitting is proposed to determine the next location to capture. Experiments on simulated data show that our method attain high quality all-in-focus image with fewer captured images.

Process Variation (PV) may cause accuracy loss of the analog neural network (ANN) processors, and make it hard to be scaled down, as well as feasibility degrading. This paper first analyses the impact of PV on the performance of ANN chips. Then proposes an in-situ transfer learning method at system level to reduce PV's influence with low-precision back-propagation. Simulation results show the proposed method could increase 50% tolerance of operating point drift and 70% ∼ 100% tolerance of mismatch with less than 1% accuracy loss of benchmarks. It also reduces 66.7% memories and has about 50× energy-efficiency improvement of multiplication in the learning stage, compared with the conventional full-precision (32bit float) training system.

This paper proposes a novel auto loss compensation (ALC) system to enable non-contact operations for capacitive coupled body channel communication (CC-BCC). The system employs a time-division compensation mismatch indicator (CMI) to continuously monitor the compensation error, and dynamically adjust the compensation inductor through a PI controller. With the close-loop topology, the proposed ALC system has three advantages: First, the path loss induced by non-contact status and backward coupling effect can be compensated simultaneously; Second, this system can dynamically attenuate the path losses, even when the channel characteristics vary with time; Third, this system has high robustness, which is insusceptible to channel variations; The simulation results show that the loss reduction of the proposed ALC system is 18 dB higher than the conventional compensation technique in the worst case.

As different tiers are stacked together in 3-D integrated circuits, the power/ground (P/G) network simulation becomes more challenging than that of 2-D cases. In this brief, we propose a hierarchical simulation method suitable for 3-D P/G network (HS3-DPG), which takes advantage of the inherent hierarchical structure of 3-D P/G network. The port equivalent model (PEM) is introduced to mask the details of P/G grid in each tier. Besides, we introduce the locality property to further simplify the simulation. Some 3-D P/G network benchmarks extracted from industrial designs are used to verify the correctness of our method. Experimental results show that, HS3-DPG can achieve considerable speedup, while maintaining high accuracy. Simplified PEMs considering the locality property can save nearly 80% memory allocation compared with the full PEMs when the number of through-silicon-vias between the adjacent tiers becomes quite large.

The sparse matrix solver by LU factorization is a serious bottleneck in Simulation Program with Integrated Circuit Emphasis (SPICE)-based circuit simulators. The state-of-the-art Graphics Processing Units (GPU) have numerous cores sharing the same memory, provide attractive memory bandwidth and compute capability, and support massive thread-level parallelism, so GPUs can potentially accelerate the sparse solver in circuit simulators. In this paper, an efficient GPU-based sparse solver for circuit problems is proposed. We develop a hybrid parallel LU factorization approach combining task-level and data-level parallelism on GPUs. Work partitioning, number of active thread groups, and memory access patterns are optimized based on the GPU architecture. Experiments show that the proposed LU factorization approach on NVIDIA GTX580 attains an average speedup of 7.02 $\times$ (geometric mean) compared with sequential PARDISO, and 1.55 $\times$ compared with 16-threaded PARDISO. We also investigate bottlenecks of the proposed approach by a parametric performance model. The performance of the sparse LU factorization on GPUs is constrained by the global memory bandwidth, so the performance can be further improved by future GPUs with larger memory bandwidth.

Flexible electronic devices, such as the typical thin-film transistors, are widely adopted in the area of sensors, displayers, wearable equipment, and such large-area applications, for their features of bending and stretching; additionally, in some applications of lower-resolution data converters recently, where a trend appears that implementing more parts of system with flexible devices to realize the fully flexible system. Nevertheless, relatively fewer works on the computation parts with flexible electronic devices are reported, due to their poor carrier mobility, which blocks the way to realize the fully flexible systems with uniform manufacturing process. In this paper, a novel circuit architecture for image processing accelerator using Oxide Thin-film transistor (TFT), which could realize real-time image pre-processing and classification in the analog domain, is proposed, where the performance and fault-tolerance of image signal processing is exploited. All of the computation is done in the analog signal domain and no clock signal is needed. Therefore, certain weaknesses of flexible electronic devices, such as low carrier mobility, could be remedied dramatically. In this paper, Simulations based on Oxide TFT device model have demonstrated that the flexible computing parts could perform 5 × 5 Gaussian convolution operation at a speed of 3.3 MOPS/s with the energy efficiency of 1.83 TOPS/J, and realize image classification at a speed of 10 k fps, with the energy efficiency of 5.25 GOPS/J, which means that the potential applications to realize real-time computing parts of complex algorithms with flexible electronic devices, as well as the future fully flexible systems containing sensors, data converters, energy suppliers, and real-time signal processing modules, all with flexible devices.

This demonstration includes a hand gesture recognition (HGR) wristband, which can decoding the information in surface electromyography (sEMG) and micro-inertial measurement unit μ-IMU. With the complementary information from IMU, the wristband only needs two pairs of sEMG electrodes, which significantly improves the user's experiences. A capacitive coupled body channel communication (CC-BCC) module is also implemented in the system for wireless communication without antennas for low-power and security concerns. In this demonstration, visitors can intuitively understand the benefit and application of body channel communication for body area network.

Neural network accelerators have been extensively studied for artificial intelligent applications for recent years. Analogto-information systems (AIS), which could accelerate neural network computation in analog domain, are considered as one better alternative for achieving higher scalability and energy efficiency. Unlike operating in the digital domain, an AIS adopts analog computing units to construct the whole neural network for perceptual tasks. However, when designing an AIS, conventional HSPICE simulation is very time-consuming. In order to improve the design capacity, this paper presents a functional simulator, called AIsim for AIS. AIsim could efficiently simulate the noise characteristics in AIS while processing neural network algorithms. In particular, it could also guide the designers to explore the design space of analog computing units with various signal-to-noise ratio (SNR). Compared with conventional HSPICE simulator, AIsim can achieve more than 2000X simulation speedup with 2% results difference at most, for some typical benchmarks.

The training of neural network (NN) is usually time-consuming and resource intensive. Memristor has shown its potential in computation of NN. Especially for the metal-oxide resistive random access memory (RRAM), its crossbar structure and multi-bit characteristic can perform the matrix-vector product in high precision, which is the most common operation of NN. However, there exist two challenges on realizing the training of NN. Firstly, the current architecture can only support the inference phase of training and cannot perform the backpropagation (BP), the weights update of NN. Secondly, the training of NN requires enormous iterations and constantly updates the weights to reach the convergence, which leads to large energy consumption because of lots of write and read operations. In this work, we propose a novel architecture, TIME, and peripheral circuit designs to enable the training of NN in RRAM. TIME supports the BP and the weights update while maximizing the reuse of peripheral circuits for the inference operation on RRAM. Meanwhile, a variability-free tuning scheme and gradually-write circuits are designed to reduce the cost of tuning RRAM. We explore the performance of both SL (supervised learning) and DRL (deep reinforcement learning) in TIME, and a specific mapping method of DRL is also introduced to further improve the energy efficiency. Experimental results show that, in SL, TIME can achieve 5.3× higher energy efficiency on average compared with the most powerful application-specific integrated circuits (ASIC) in the literature. In DRL, TIME can perform averagely 126× higher than GPU in energy efficiency. If the cost of tuning RRAM can be further reduced, TIME have the potential of boosting the energy efficiency by 2 orders of magnitude compared with ASIC.

Flexible electronic is a promising technology for flexible and large-area sensing IoT applications, where ADC is a fundamental component This paper proposes a configurable and flexible VCO-based ADC, implemented with Oxide Thin-Film Transistors(TFT) technology. A VCO with four connecting modes is designed to configure the VCO-based ADC working under different power and resolutions. An Inkjet printing interconnection technology is introduced to enable the configurability of ADC, even after all TFT transistors are fabricated. It allows the ADC to be customized for different applications and avoids fabrication failure of devices. Experimental results show that the proposed ADC achieves a 0.8kS/s sampling rate. Its power consumption ranges from 541 to 866uW with ENOB from 3 to 6b.

Emerging memory devices enable performance improvements in memory applications and make possible chip designs using beyond von Neumann architectures. This paper explores the use of emerging memory devices in applications of nonvolatile logics and neuromorphic computing, and provides a review of several silicon examples of nonvolatile logics. This paper also discusses the challenges involved in the design of circuits for nonvolatile logics and neuromorphic computing systems based on emerging memory devices.

State-of-the-art high-accuracy three-dimensional (3D) profilometry systems typically use a lens with a fixed focal length, making it difficult for them to measure scenes with large depth variations, especially dynamically changing ones. To address this need, this Letter proposes a novel, to the best of our knowledge, autofocusing method for high-resolution 3D profilometry with a digital fringe projection technique by (1) developing a novel continuous geometric parameter model for systems using electrically tunable lenses and (2) employing a focal plane detection algorithm. The validity of the proposed method is confirmed by experiments.

Off-chip interconnect is often a bottleneck due to its limited number of pins and bandwidth. The authors present an optical orbital angular momentum (OAM)-based wireless interchip interconnect and compare it with traditional electrical and optical interconnect alternatives.

The sparse matrix solver has become a bottleneck in simulation program with integrated circuit emphasis (SPICE)-like circuit simulators. It is difficult to parallelize the solver because of the high data dependency during the numeric LU factorization and the irregular structure of circuit matrices. This paper proposes an adaptive sparse matrix solver called NICSLU, which uses a multithreaded parallel LU factorization algorithm on shared-memory computers with multicore/multisocket central processing units to accelerate circuit simulation. The solver can be used in all the SPICE-like circuit simulators. A simple method is proposed to predict whether a matrix is suitable for parallel factorization, such that each matrix can achieve optimal performance. The experimental results on 35 matrices reveal that NICSLU achieves speedups of 2.08× ~ 8.57×(on the geometric mean), compared with KLU, with 1-12 threads, for the matrices which are suitable for the parallel algorithm. NICSLU can be downloaded from http://nicslu.weebly.com.

In this chapter, we will propose parallelization methodologies for the G-P sparse left-looking algorithm. Parallelizing sparse left-looking LU factorization faces three major challenges: the high sparsity of circuit matrices, the irregular structure of the symbolic pattern , and the strong data dependence during sparse LU factorization. To overcome these challenges, we propose an innovative framework to realize parallel sparse LU factorization. The framework is based on a detailed task-level data dependence analysis and composed of two different scheduling modes to fit different data dependences: a cluster mode suitable for independent tasks and a pipeline mode that explores parallelism between dependent tasks. Under the proposed scheduling framework, we will implement several different parallel algorithms for parallel full factorization and parallel re-factorization . In addition to the fundamental theories, we will also present some critical implementation details in this chapter.

Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing E S by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (T SWT ). For the first time, an nvFF with single NVM device is presented.

Flexible electronic devices are widely adopted in fields of sensors, wearable equipments, RFID and large-area applications, for their features of bending and stretching. However, relatively fewer research works on computation with flexible electronic devices are reported, due to their poor carrier mobility and stability. In this paper, a novel circuit architecture of image filtering accelerator using Organic Thin-film transistor (OTFT), which could realize real-time image signal convolution in analog domain, is proposed.

This paper introduces balanced switching schemes to compensate linear and quadratic gradient errors, in the unary current source array of a current-steering digital-to-analog converter (DAC). A novel algorithm is proposed to avoid the accumulation of gradient errors, yielding much less integral nonlinearities (INLs) than conventional switching schemes. Switching scheme examples with different number of current cells are also exhibited in this paper, including symmetric arrays and nonsymmetric arrays in round and square outlines. (a) For symmetric arrays where each cell is divided into two parallel concentric ones, the simulated INL of the proposed round/square switching scheme is less than 25%/40% of conventional switching schemes, respectively. Such improvement is achieved by the cancelation of linear errors and the reduction of accumulated quadratic errors to near the absolute lower bound, using the proposed balanced algorithm. (b) For non-symmetric arrays, i.e. arrays where cells are not divided into parallel ones, linear errors cannot be canceled, and the accumulated INL varies with different quadratic error distribution centers. In this case, the proposed algorithm strictly controls the accumulation of quadratic gradient errors, and different from the algorithm in symmetric arrays, linear errors are also strictly controlled in two orthogonal directions simultaneously. Therefore, the INLs of the proposed non-symmetric switching schemes are less than 64% of conventional switching schemes. key words: digital-to-analog converter, gradient errors, nonlinearity, switching scheme, the integral nonlinearity

The sparse matrix solver has become the bottleneck in a Simulation Program with Integrated Circuit Emphasis circuit simulator. It is difficult to parallelize the sparse matrix solver because of the high data dependence during the numerical LU factorization. In this brief, a parallel LU factorization algorithm is developed on shared-memory computers with multicore central processing units, based on KLU algorithms. An Elimination Scheduler (EScheduler) is proposed to represent the data dependence during the LU factorization. Based on the EScheduler, the parallel tasks are scheduled in two modes to achieve a high level of concurrence, i.e., cluster mode and pipeline mode. The experimental results on 26 circuit matrices reveal that the developed algorithm can achieve speedup of 1.18–4.55× (on geometric average), as compared with KLU, with 1–8 threads. The result analysis indicates that for different data dependence, different parallel strategies should be dynamically selected to obtain optimal performance. Accepted version

A CMOS triode transconductor was developed with common mode feedback suitable for operating in low-voltage and low-power applications. The design is based on a body-driven input stage with feedback loops to extend both the signal input range and the tuning capability. The effective transconductance of the body-driven triode stage is increased using a partial positive feedback technique which also partially solves the problem introduced by the small transconductance. This design uses the UMC 0.18 μm CMOS process. Simulations show the transconductor operated with 1 V supply voltage has less than −55 dB total harmonic distortions (THD) in the complete tuning range (0 V ≤ V cont ≤ 0.43 V) for a 1 MHz 0.8 V p-p differential input. The power consumption is 70 μW for a 0.43 V control voltage.

Soft error is becoming increasingly important in the era of sub-100 nanometer very large scale integrated (VLSI) circuits. This article focuses on the impact of soft error on an OpenRisc 1200 CPU core. A C++ programming language based soft error analysis tool, with the name of SERSim, is created to perform a detailed exploration of this impact. The estimation error of SERSim ranges from 0.1% to 4.5%. With the help of SERSim, we find out that almost all the glitch widths are narrower than 200 ps in a 45 nm OpenRisc 1200 microprocessor circuit. This result is important for soft error rate reduction of VLSI circuits. The outputs of the multiplier of the OpenRisc 1200 microprocessor are found to be the most troublesome. Those outputs, which represent only 3% of the circuit outputs, produce more than half of the circuit bit error rate. A significant impact of performance requirements on circuit vulnerability to soft error is observed in our experiment. The difference helps us to analyse the estimation error of...

This paper describes a 12-bit 40-MS/s and 8-bit 80-MS/s dual-mode low power pipelined analog-to-digital converter (ADC). An improved multiplying digital-to-analog converter is used to provide the dual-mode operation. A pre-charged fast power-on switched operational amplifier is used to reduce the power consumption of the pipelined ADC to 28.98 mW/32.74 mW at 40 MHz/80 MHz sampling rates. The ADC was designed in a 1.8-V 1P6M 0.18-μm CMOS process. Simulations indicate that the ADC exhibits a spurious free dynamic range of 90.24 dB/58.33 dB and signal-to-noise-and-distortion ratio of 73.81 dB/47.85 dB at 40 MHz/80 MHz sampling frequencies for a 19-MHz input sinusoidal signal.

Due to the superlinear dependence of leakage power consumption on temperature, and spatial variations in on-chip thermal profiles, methods of leakage power estimation that are known to be accurate require detailed knowledge of thermal profiles. Leakage power depends on the integrated circuit (IC) thermal profile and circuit design style. Here, we show that piecewise linear models can be used to permit accurate leakage estimation over the operating temperature ranges of the ICs. We then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have a similar impact on the average temperature of the layer. These two observations support the proof that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with piecewise linear leakage power consumption models, enable the estimation of chip-wide leakage power consumption. These results are further confirmed through comparisons with leakage estimates based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that, when compared with a leakage analysis technique that relies on accurate spatial temperature estimation, the proposed technique yields a 59,259× to 1,790,000× speedup in estimating leakage power consumption, while maintaining accuracy.

A low voltage low power successive approximation register (SAR) analog-to-digital converter (ADC) based on a novel rail-to-rail comparator is proposed in this paper. The power consumption of the comparator is significantly reduced through dynamic operation while the speed is augmented by using an efficient regenerative latch. No biasing circuits are needed and there are no floating nodes in the comparator throughout the conversion process. The digital-to-analog converter (DAC) is formed from a binary array of MIM capacitors. The 250KS/s ADC implemented in a 0.18µm process consumes only 1.35µW of power at a supply voltage of 0.8V.

A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than −80 dB total harmonic distortion (THD) for a 1-MHz 0.4-Vp-p differential input signal. The third-order intermodulation is less than −63 dB for 0.25 Vp-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.

As semiconductor manufacturing migrates to more advanced technology nodes, accelerated aging effect for nanoscale devices poses as a key challenge for designers to find countermeasures that effectively mitigate the degradation and prolong system’s lifetime. Negative Bias Temperature Instability (NBTI) is emerging as one of the major reliability concerns. Two software tools for NBTI analyzing are proposed in this paper, one for transistor-level, and the other for gate-level. The transistor-level can be used to estimate the delay degradation due to NBTI effect very accurately, while the gate-level can be used for repeat analysis in circuit optimization because of its fast computing speed.