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Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology reveal the persisting reliability threat single-event latchup (SEL) poses to advanced technology nodes. SEL is characterized over a wide range of supply voltages and temperatures for this technology node. SEL data is analyzed to determine the holding voltage ($V_{\mathrm {HOLD}}$) required to sustain SEL, which can be as low as 0.85 V at elevated temperatures. Such low SEL holding voltage within 100 mV of nominal supply voltage poses a major reliability threat. [ABSTRACT FROM AUTHOR]

As the minimum feature size on an integrated circuit continues to shrink aggressively toward deep submicrometer, the radiation-induced single-event (SE) upset (SEU) has become a prominent concern. Various radiation-hardening-by-design (RHBD) techniques have been developed to achieve a satisfactory SE tolerance for flip-flop (FF) designs. To enable low supply voltage for ICs and overcome the “power wall,” the lowest power consumption of different RHBD techniques to meet the target SEU cross section is studied in this paper. A comparative analysis of three representative RHBD FFs and an unhardened FF fabricated at the 14-/16-nm bulk FinFET CMOS technology generation shows that at least $2\times $ power dissipation reduction may be achieved by using RHBD FFs at appropriate supply voltage without degrading SE tolerance. [ABSTRACT FROM AUTHOR]

A uniform technology-agnostic time-domain model for both linear and nonlinear all-digital phase-locked loops (ADPLLs) is presented. This time-domain model can be used for single-event upset (SEU)-induced perturbation time prediction and SEU sensitivity characterization of common ADPLL topologies. The model is validated against field-programmable gate array-based fault injection experiments and two photon absorption laser experimental results on three different types of designs. The model is applicable to rad-harden by design activities, failure mode predictions, and general ADPLL design optimizations. [ABSTRACT FROM PUBLISHER]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

At the gigahertz range of frequencies, contribution of combinational logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any combinational logic circuit. Estimated logic SEU cross section matches well with the measured logic SEU cross section. Estimated logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured logic SEU cross section. This method only needs to be calibrated once for use at a given technology node. [ABSTRACT FROM PUBLISHER]

Integrated circuits fabricated at advanced technology nodes are expected to operate in gigahertz range of frequencies. At these frequencies, single-event transient (SET)-induced errors result in significant increases in single-event (SE) cross section for flip-flop (FF) designs. For FinFET transistors, the physical structure has changed significantly from planar structure. These changes have resulted in significantly less collected charge than that for planar technologies for the same ion strike, leading to shorter SET pulse generation. These results have necessitated the evaluation of SE cross section for FF designs as a function of frequency for accurate SE predictive capability. Circuit-level simulations and heavy-ion experiments were carried out to investigate frequency dependence of SE cross section for a hardened dual-interlocked cell-based FF design with different spacing options in a 16-nm bulk FinFET technology. [ABSTRACT FROM PUBLISHER]

Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A variety of logic gate chains were designed, and SET pulse widths were obtained across a wide range of supply voltages. In light of the increased SET response at reduced supply voltages, the efficacy of filter-based mitigation is assessed by analyzing the voltage dependence of SET duration against the characteristic electrical inverter delay. [ABSTRACT FROM PUBLISHER]

Flip-flop soft errors caused due to direct strikes on flip-flops as well as soft errors caused due to latched transients from combinational logic show frequency dependence. This frequency dependence in the case of high-speed sequential circuits can derate the soft error rate by as much as 5X. Circuit variables, such as voltage, frequency, logic delay, as well as environmental factors, such as particle type and linear energy transfer that affect the frequency dependence are studied. Heavy-ion irradiation of 28-nm sequential circuits shows that the cross-section decreases with frequency for low-LET particles and increases with frequency for higher-LET particles. Competing trends involving combinational logic and flip-flops are shown to be the reason. The voltage dependence of this trend is evaluated. The key insight that emerges from this work is that at sufficiently high frequencies, the cross-section of certain sequential circuits can be lower than that at lower frequencies. Similarly, lowering voltage may not always result in increased soft error rate at certain frequencies. [ABSTRACT FROM PUBLISHER]

The ambipolar-diffusion-with-cutoff (ADC) model is extended to estimate the single-event-induced collected charge for multiple transistors for circuits simulation. The proposed improvement in the model includes both parasitic-bipolar and charge-sharing effects for a given technology. Simulation results indicate excellent agreement between the proposed model and published TCAD data for 130, 90, 65, and 40 nm technology nodes. A comparison between ADC and both rectangular parallelepiped (RPP) and integral rectangular parallelepiped (IRPP) models indicates a 2.7\times and 2.5\times lower error in estimating collected charge when compared with TCAD data. The ADC average error was estimated to be 7.1 fC and for the RPP and IRPP about 19.1 fC and 17.5 fC, respectively, across the technologies for particles with the linear energy transfer range from 1 - 30~\MeV-cm^2/\mg. [ABSTRACT FROM PUBLISHER]

For advanced technology nodes, the close proximity of semiconductor regions results in multiple regions collecting charge after an ion strike. This is especially true for static random access memory (SRAM) integrated circuits (ICs) where transistors are placed closer to each other compared to application-specific ICs (ASICs). As a result, SRAM ICs are highly vulnerable to multi-cell upsets (MCU). In this work, heavy-ion irradiations of bulk 28-nm planar and 16-nm FinFET SRAM ICs are investigated to show that small cell size for 16-nm node results in dominance of MCUs over single-cell upsets. Three-dimensional TCAD simulations showing the spread of well-potential perturbation as a function of particle LET support the experimental data. The size of the MCU cluster is also presented to determine the design parameters for error correcting codes (ECC) and interleaving for SRAM designs to meet performance requirements. [ABSTRACT FROM PUBLISHER]

With the emphasis on low-power design, achieving soft error reliability in combinational logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate combinational logic soft errors. This work shows that for certain circuits, reduction in both power and combinational logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits. [ABSTRACT FROM PUBLISHER]

Single-event transient (SET) induced harmonic errors have been observed in digitally controlled ring oscillators (DCRO). Accumulated phase error is used to characterize harmonic errors in ring oscillator circuits. An analytical model for determining minimum and maximum SET transient duration capable of generating a harmonic is described. Simulation and TPA laser experimental results on a 40-nm DCRO are shown to confirm the assertion of the harmonic vulnerability window with respect to SET pulsewidth. Further more, fault injection experimental results on three RO designs built with discrete commercial off-the-shelf components are included to demonstrate the relationship between harmonic response and SET pulsewidth. [ABSTRACT FROM PUBLISHER]

The impacts of total ionizing dose (TID), temperature and RF stress on the DC and RF performance of a commercial 32 nm RF silicon-on-insulator CMOS technology are presented. Temperature dependence is the overwhelmingly dominant single factor affecting the DC and RF performance, with the combined effects of elevated temperature and TID showing the most pronounced degradation. The most significant effect due to TID is an increase in off-state leakage current. Key DC and RF parameters of this 32 nm RF process degrade less than those of an otherwise similar 45 nm RF SOI CMOS process. The implications of the combined TID and temperature response are discussed for low-power RF design. [ABSTRACT FROM PUBLISHER]

A method for experimental determination of the phase dependence of single-event sensitivity in high-speed A/MS circuits is presented. The technique ensures testing coverage of the complete data cycle and results in a correlation of errors to the data or clock cycle of the circuit. Designers can apply the information, along with knowledge of the circuit state at the time of errors, to make informed radiation-hardening-by-design decisions. [ABSTRACT FROM AUTHOR]

Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the effects of N- and P-well contact densities on single-event latchup. Although scaling has improved latchup robustness, process-level immunity has not been achieved, indicating a continued need for latchup mitigation techniques. A simple, algorithmic approach for selecting N- and P-well contact densities is described that ensures latchup immunity while minimizing the area penalty. [ABSTRACT FROM AUTHOR]

The analysis and measurement of a radiation hardened by design 3.125 Gbps SerDes transmitter driver fabricated in commercial 90 nm CMOS is presented. The transmit driver is implemented in thick oxide 2.5 V devices. Testing and simulation of laser-induced single-event transients of a fabricated driver section are discussed. A highly-flexible data collection technique that allows post-processing of data for different error types and thresholds within a single data set is presented. This effort represents the first single-event effects measurement and analysis on a highly-scaled analoglRF CMOS circuit element operating at GHz frequencies. Sensitive nodes are identified through experiment and simulation. [ABSTRACT FROM AUTHOR]

Scaling of complementary metal oxide semiconductor (CMOS) technologies to the sub-100 nm dimension regime increase the sensitivity to pervasive terrestrial radiation. Diminishing levels of charge associated with information in electronic circuits, interactions of multiple transistors due to tight packing densities, and high circuit clock speeds make single event effects (SEE) a reliability consideration for advanced electronics. The trend to adapt and apply commercial IC processes for space and defense applications has provided a catalyst to the development of infrastructure for analysis and mitigation that can be leveraged for advanced commercial electronic devices. In particular, modeling and simulation, leveraging the dramatic reduction in computing cost and increase in computing power, can be used to analyze the response of electronics to radiation, to develop and evaluate mitigation approaches, and to calculate the frequency of problematic events for target applications and environments. [ABSTRACT FROM AUTHOR]

The minimum laser energy required to cause sustained harmonic oscillations in a 201-stage ring oscillator varies little with increasing power supply voltage when operating in the subthreshold region. These small changes in threshold laser energy in the subthreshold region suggest that the cross-section curves as a function of power supply voltage remain relatively constant. Simulations show that the minimum pulsewidth required to generate higher-order oscillations decreases as operating voltage increases. Single-event transients are wider when circuits are operating in the subthreshold region than when operating at the nominal power supply voltages. Narrower single-event transients result for strikes on PMOS transistors as compared to those for strikes on NMOS devices in the subthreshold region; the opposite is observed when circuits are operating at the nominal power supply voltages. [ABSTRACT FROM PUBLISHER]

Voltage-controlled oscillators (VCOs) have been shown to dominate the single-event transient (SET) response of mixed-signal circuits such as the phase-locked loop (PLL). An analytical model is presented to determine the VCO design parameters and the associated SET vulnerability. Additionally, radiation-hardened-by-design (RIIBD) techniques to mitigate SETs in current-starved VCOs are presented; The proposed mitigation techniques reduce the phase displacement in the output of the VCO following a single-event (SE) by approximately 66%. The availability of the analytical model and RHBD techniques will improve the SE performance of VCO and PLL designs to ensure a specified tolerance to SEs. [ABSTRACT FROM AUTHOR]

Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping. [ABSTRACT FROM AUTHOR]

The interaction between a heavy ion and the overlayer materials in an integrated circuit may result in a nuclear reaction. This reaction leads to a charge generation profile that is substantially altered from the profile generated during a direct ionization event. In this work, nuclear reactions are integrated into the modeling of the SEU response of an SRAM cell using GEANT4-based simulations. The simulated transient response is compared to the response obtained using a typical heavy ion model that includes only direct ionization. [ABSTRACT FROM AUTHOR]

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80° C after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents. [ABSTRACT FROM AUTHOR]

A new category of analog single-event transients (SETs) with millisecond-long durations have been experimentally observed in the LM6144 operational amplifier. It is the first time that events with such extreme widths are under investigation in a linear integrated circuit. Relying on heavy-ion broadbeam tests, picosecond pulsed lasers diagnostics, and computer-assisted circuit modeling, we uncover the mechanisms and causes of these anomalous voltage transients. The identification of the problematic area of the IC reveals that the bias/startup circuitry is sensitive to energetic ionizing particles and can be responsible for corrupted circuit operations when subjected to a heavy-ion strike. A circuit hardening solution with minimal impact on the layout and the electrical performances of the op amp are proposed to mitigate this effect. [ABSTRACT FROM AUTHOR]

We present experimental and simulation results on single-event transients in an analog subsystem for satellite electronic equipment. Investigations based on worst-case transient events, simulated with transistor-level circuit models, suggest design modifications for hardening. [ABSTRACT FROM AUTHOR]

We have evaluated the applicability of vendor-supplied analog circuit macromodels to single-event transient (SET) analyses. Our findings demonstrate that macromodeling is very effective for system-level SET investigations; yet it is inadequate to address details of SET initiation at the IC level. Study of both dc and transient applications show that the circuitry peripheral to the ion strike location can be macromodeled and still retain an excellent ability to accurately transmit propagating voltage transients. [ABSTRACT FROM AUTHOR]

Focuses on a study that investigated the effects of single-event transients in different stages of the integrated circuit and the effect that certain amplifier parameters have on the transient response of the output voltage. Laser data; Details of the circuit model; Simulations; Discussion.

Deals with a study which analyzed the single event effects in a moderately simple synchronous circuit, the AM2901 4-bit microprocessor. Review of related literature; Data and methodology used; Results and discussion.