1. A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS.
- Author
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Lu, Fei, Ma, Rui, Dong, Zongyu, Wang, Li, Zhang, Chen, Wang, Chenkun, Chen, Qi, Wang, X. Shawn, Zhang, Feilong, Li, Cheng, Tang, He, Cheng, Yuhua, and Wang, Albert
- Subjects
ELECTROSTATIC discharges ,ELECTRONIC circuit protection ,INTEGRATED circuits ,COMPLEMENTARY metal oxide semiconductors ,FAILURE analysis ,LINE drivers (Integrated circuits) - Abstract
This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
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