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Eddy current pulsed thermography (ECPT), a new emerging nondestructive testing and evaluation (NDT&E) technique, has been applied for a wide range of conductive materials. The acquired image sequences contain valuable information in both spatial and time domain. ECPT techniques mainly use a specific frame to detect and quantify the defects. However, selection of specific frame from transient thermal image video to maximize the contrast of thermal variation and defect pattern from complex geometrical samples remain a challenge. In order to accurately find anomalous patterns from the transient thermal pattern for defect detection and further quantitative NDE, this paper employs a single channel blind source separation algorithm. This method enables spatial and time patterns to be extracted according to the whole transient response behavior without any training knowledge. In this paper, both mathematical and physical models are discussed, and the basis of the proper selection of contrast image is given. In addition, the artificial slot and thermal fatigue natural crack are applied to validate the proposed method. [ABSTRACT FROM PUBLISHER]

Global interconnects play an increasingly important role in nanometer-scale integrated technologies. The optimization of global wire size (width and/or spacing) has been well studied. However, many optimization methodologies do not consider thermal effects. As technology scales, decreasing interconnect pitch and the introduction of low-k dielectrics have made self-heating of global interconnects an important issue. In this paper, we present a temperature-aware methodology for systematically optimizing the size of global interconnects with optimal repeater for maximizing the circuit performance. We develop techniques to calculate the full-chip temperature as a function of global interconnect width and spacing and analytically analyze the impacts of wire size on the substrate and self-heating temperature. We then reinvestigate the temperature -and size-dependent interconnect delay, bandwidth, and power consumption, and define a product of the delay per unit length, power dissipation per unit length, and reciprocal bandwidth per unit chip edge as an appropriate figure of merit for optimum wire size for various International Technology Roadmap for Semiconductors technology nodes. [ABSTRACT FROM PUBLISHER]

High frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. Equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for the important physical effects at both DC and HF. Based m the Y-parameter analysis of the equivalent circuit model, procedures of the HF model parameter extraction are also developed. With the discussed approaches, a sub-circuit RF model incorporating the modeling of parasitics is presented. This model is compared with the measured data for both y parameter and f[sub T] characteristics. Good model accuracy is achieved against the measurements for a 0.25µm RF CMOS technology. The non-quasi-static (NQS) modeling issue has also been discussed by using the BS1M3v3 based RF model to predict the HF characteristics of devices with serious NQS effects. Further, noise modeling issues are discussed by analyzing the theoretical and experimental results in both the flicker noise and thermal noise modeling. Modeling efforts to incorporate new physical effects are needed to predict better the flicker noise characteristics in today's MOSFETs. A detailed analysis of the HF noise parameters has been conducted to establish the relationship between the noise parameters preferred by circuit designers and obtained by HF noise measurement. Analytical calculation of the noise parameters has also been discussed to understand the noise characteristics with/without some parasitic components such as gate and substrate resistances as well as the influence of the induced gate noise. The HF noise predictivities of several HF noise models are also examined with the measured data. The results show that the BSIM3v3 based RF model can predict the channel thermal noise better than the other models. [ABSTRACT FROM AUTHOR]

Abstract: This paper describes a power management chip for wireless powering capsule endoscopy, including over-voltage protection circuit RF limiter, CMOS rectifier and low dropout regulator (LDO). Bulk commutation technique is applied to suppress the substrate leakage current problem of CMOS rectifier. A bandgap circuit used as reference for LDO is optimized carefully and has a more than −50dB PSR at 2MHz, which can effectively suppress the ripple of rectifier output used as input voltage of LDO. It incorporates a voltage controlled current source (VCCS) compensation network to make sure the loop’s stability is not dependent on the output capacitor’s Equivalent Series Resistance (ESR). The proposed chip has implemented in 0.35μm CMOS technology and the measurement results show that it can provide as high as 63.8mA output current at a 3V output voltage. The PMC has been used in a wireless powering system designed for capsule endoscope application. Experiment results show that the Power Management Chip (PMC) can deliver as high as 191mW DC energy to the load, imitating the physical condition in a biomedical environment in a human body. [Copyright &y& Elsevier]