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A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Oct2016, Vol. 63 Issue 10, p1746-1757, 12p
- Publication Year :
- 2016
-
Abstract
- This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 63
- Issue :
- 10
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 118500169
- Full Text :
- https://doi.org/10.1109/TCSI.2016.2581839