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Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm2. The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm2 fJ/conversion-step.

This paper presents a noise-reconfigurable resistive feedback amplifier with current-reuse technique for fetal ECG monitoring. The proposed amplifier allows for both tuning of the noise level and changing the power consumption according to the signal properties, minimizing the total power consumption while satisfying all application requirements. The amplifier together with its amplitude detector and dynamical biasing circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measurements demonstrate that the proposed current-reuse resistive feedback topology improves the power efficiency of the conventional resistive feedback amplifier, achieving at the same time a good noise efficiency factor (NEF $=2.8$ ) and an input impedance of 20 $\text{M}\Omega $ . The amplitude detector and the dynamical biasing circuit, which tunes the current in the amplifier according to the signal amplitude, save up to 40% of the total power consumption. The amplifier achieves a measured noise level of 0.34 $\mu \text{V}_{\mathrm{ rms}}$ in a 0.6–175-Hz band, consuming 6.3- $\mu \text{W}$ power.

This paper presents a 10 b 80 kS/s SAR ADC with low-power duty-cycled reference generation. It generates a stable reference voltage on chip for the SAR ADC and imparts very good immunity against power supply interference to the ADC. A 0.62 V-VDD 25 nW CMOS reference voltage generator (RVG) is presented, which has only ±1.5% variation over process corners. A duty-cycling technique is applied to enable 10% duty-cycling of the RVG, resulting in negligible power consumption of the RVG compared to that of the ADC. Furthermore, a bi-directional dynamic preamplifier is adopted in the SAR ADC, which consumes about half the power compared with a regular dynamic structure and maintains noise and gain performance. Compared with prior-art low-power ADCs, this work is the first to integrate the reference generation and include it in the power consumption while maintaining a competitive 2.4 fJ/conversion-step FoM. The chip is fabricated in 65 nm CMOS technology.

Miniature $\text{mm}^3$ -sized sensor nodes have a very tight power budget, in particular, when a long operational lifetime is required, which is the case, e.g., for implantable devices or unobtrusive IoT nodes. This paper presents a fully integrated signal acquisition IC for these emerging applications. It integrates an amplifier with 32 dB gain and 370 Hz bandwidth that includes positive feedback to enhance input impedance and dc offset compensation. The IC includes also a 10 bit 1 kS/s SAR ADC as well as a clock generator and voltage and current biasing circuits. The overall system achieves an input noise of $27\;\upmu \text {V}_{{\text{rms}}}$ , consumes 3 nW from a 0.6 V supply, occupies $0.20\;\text {mm}^2$ in 65 nm CMOS, and has a single-wire data interface. The amplifier achieves an noise-efficiency factor (NEF) of 2.1 and the ADC has a figure-of-merit (FoM) of 1.5 fJ/conversion-step. Measurements confirm reliable operation for supplies from 0.50 to 0.70 V and temperatures in the range of 0–85 °C. As an application example, an ECG recording is successfully performed with the system while a $0.69\; \text{mm}^2$ photodiode array provides its power supply in indoor lighting conditions.

A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to increase the on-chip inductor quality factor are proposed. To reduce the insertion loss from the transistors, the transistor switches are implemented with a body-source connection. For all 32 states, the minimum phase error is 1.5°, and the maximum phase error is 6.8°. The measured insertion loss is -20.9 ± 1 dB including pad loss at 60 GHz and the return loss is >10 dB over 57-64 GHz. The total chip size is 0.24 mm2 with 0 mW DC power consumption.

Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.

This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic operation can achieve a low average power while still supporting a large active power, needed to overcome leakage side-effects during the active period. A current biasing scheme is introduced to guarantee a proper operating point and to stabilize performance as well as power consumption over a large temperature range from -40 to 125°C. The simulated voltage reference in 65nm CMOS consumes 0.33nW at room temperature and maintains sub-nW throughout the temperature range with 2.34% active time. At 5 corners, the reference voltage Huctuates with 3% at room temperature and the temperature coefficient varies from 5.3∼31.3ppm/°C. The resistor-less voltage reference only occupies a chip area of 4600μm2. The sub-nW power consumption, small chip area and low temperature coefficient in wide temperature range make this design an eligible voltage reference solution to low-power systems like IoT.

The Phoenix project aims to develop a new approach to explore unknown environments, based on multiple measurement campaigns carried out by extremely tiny devices, called agents, that gather data from multiple sensors. These low power and low resource agents are configured specifically for each measurement campaign to achieve the exploration goal in the smallest number of iterations. Thus, the main design challenge is to build agents as much reconfigurable as possible. This paper introduces the Phoenix project in more details and presents first developments in the agent design. ispartof: pages:290-293 ispartof: Proceedings of Design Automation and Test conference 2017 pages:290-293 ispartof: Design Automation and Test in Europe (DATE) location:EPFL Campus, Lausanne, SWITZERLAND date:27 Mar - 31 Mar 2017 status: published

An on/off keying receiver has been designed in 90 nm CMOS for low-power event-driven applications. Thanks to the synchronized-switching technique and power-efficient RF gain stages, this receiver achieves -86 dBm sensitivity (10 -3 bit error rate) at 10 kbps while consuming 123 µW from a 1 V supply. The receiver is highly scalable in data rates from 1 kbps at 64 µW to 100 kbps at 146 µW power consumption. The center frequency of the receiver can be also programmed from 780 to 950 MHz, covering different sub-GHz bands worldwide. The receiver is fully integrated, although an external SAW filter can be added for better selectivity.

This special issue of the IEEE Journal of Solid-State Circuits features expanded versions of key invited papers presented at the 47th European Solid-State Circuits Conference (ESSCIRC), held at the Katholieke Universiteit Leuven, Leuven, Belgium, on September 11, 2017–September 14, 2017.

In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy consumption. This reset energy consumption can be significant and is seldom optimized in low power switching schemes. The scheme can be applied to all differentially reset and switched DACs. This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides swapping, rotation is also applied to the 2 MSBs of the DAC to enhance the linearity to 88dB SFDR. The SAR ADC operates at 0.8V VDD and 40kS/s, achieving an SNDR of 64.2dB and a FoM of 7.1fJ/conversion-step.

This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An implemented 8-bit prototype in a 90 nm CMOS technology occupies 228 µm × 240 µm including decoupling capacitors, and achieves an ENOB of 7.77 bit at a sampling frequency of 10.24 MS/s. The power consumption equals 26.3 µW from a 1 V supply, thus resulting in an energy efficiency of 12 fJ/conversion-step. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW. In that way, the energy efficiency of this converter can be maintained down to very low sampling rates.

This paper presents a power-efficient ASIC for bio-impedance spectroscopy, as well as ECG and respiration recording. The ASIC includes a wideband stimulation current source with a pseudo-random binary sequence, a low-noise instrumentation amplifier, and a low power 12b SAR ADC. This ASIC is able to measure bio-impedances from 1ω to 10kω with 0.1ω resolution, and covers a frequency range up to 125kHz. Furthermore, the ASIC can simultaneously record ECG and respiration while consuming only 31μW from a 1.8V supply.

Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact.

In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where −95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.

This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency $= 90\%$ ).The low-voltage amplifier together with its power management circuitry is implemented in a standard $0.18~\mu{\rm m}$ CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor $({\rm NEF}=1.74)$ and power efficiency factor $({\rm PEF}=1.05)$ . Experiments show that the amplifier core can provide a noise level of $0.34~\mu {\rm Vrms}$ in a 0.7 to 182 Hz band, consuming $1.17~\mu {\rm W}$ power. The amplifier together with its power management circuitry consumes $1.56 ~\mu {\rm W}$ , achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements.

This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP RF transceiver [1-3] is one of the most critical components that enables these emerging applications, as it can consume up to 90% of total battery energy. Furthermore, a low-cost radio design with an area-efficient fully integrated RF SoC is an important catalyst for developing such applications. By employing a low-voltage digital-intensive architecture, the presented SoC is fully compliant with BLE and IEEE802.15.4 PHY/Data-link requirements and achieves state-of-the-art power consumption of 3.7mWforRXand4.4mWforTX.

Autonomous wireless sensor nodes need low-power low-speed ADCs to digitize the sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (

Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.

This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing; Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format.

This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 μW at 20 MHz operation.

Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1μW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.

Autonomous wireless sensor nodes for cloud networks require ultra-low-power electronics. In particular, sensor readout interfaces need low-speed high-precision ADCs for capturing, e.g., bio-potential signals, environmental information, or interactive multimedia. For these applications, state-of-the-art SAR ADCs can provide highly power-efficient solutions (

The introduction of the IEEE802.15.6 standard (15.6) for wireless-body-area networks signals the advent of new medical applications, where various wireless nodes in, on or around a human body monitor vital signs. Radio communication often dominates the power consumption in the nodes, thus low-power transceivers are desired. Most state-of-the-art low-power transceivers support only proprietary modes with OOK or FSK modulations, and have poor sensitivity or low data rate [1,2]. In this work, a 15.6-compliant transceiver with enhanced performance is proposed. First, the data-rate is extended to 4.5Mb/s to cover multi-channel EEG applications. Second, while a best-in-class energy efficiency of 0.33nJ/b is achieved in the high-speed mode, a dedicated low-power mode reduces the RX power further in low-data-rate operation. Third, a sensitivity 5 to 10dB better than the 15.6 specification is targeted to accommodate extra path loss due to shadowing effects from human bodies.

Sensor node systems are expected to be a major growth field for semiconductor markets, and will connect to the cloud in a future cyber physical world. Wireless sensor networks (WSN) face multiple challenges from system design to low-power electronics and energy sources. Ultra-low-power radios are key elements in such systems, putting high demand on energy efficiency in different modes of operation (active, wake-up and sleep). This forum presents system perspectives and practical design aspects in various energy-efficient and short-range radio circuits and systems, including an introduction to various applications and their requirements for RF and digital signal processing in WSN systems. The technologies range from RF to digital signal processing and algorithms to give comprehensive understanding of recent advances. The forum begins with two high-level design talks on low power radio SoCs. The following four talks present ultra-low-power transceivers for body-area networks, sensor nodes, and health-monitoring applications. The last two talks cover efficient power management and emerging compression methodologies.

This paper proposes a multiple-channel frontend system with current reuse for fetal monitoring applications. The structure and specifications of the proposed frontend system are determined while taking into consideration the algorithms used for fetal electrocardiogram (fECG) detection. Two amplifier topologies based on a middle rail current source/sink (MCS) are proposed for fECG and electrohysterogram (EHG) recording. The proposed amplifiers explore power optimization in both current and voltage domain and thus achieve a better effective noise efficiency factor (NEF) while providing multiple-channels. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that the frontend system provides 3 fECG and 4 EHG recoding channels with a total power consumption of 3.1μW. The IA for fECG monitoring achieves an equivalent NEF of 1.17/1.21 for low noise and low power settings respectively.

In this paper the architecture and performance of a co-integrated 60 GHz on-chip wireless energy harvester and ultra-low power (ULP) radio in 65-nm CMOS are discussed. Integration of an on-chip antenna with wireless power receiver and wireless data transfer module is the crucial next step to achieve compact and high efficiency fully-integrated monolithic wireless sensor nodes. A single-pole-single-throw 60 GHz RF switch is proposed and simulated to decouple the power harvesting and data transfer module. The designed on-chip RF switch has -2 dB insertion loss in EM simulations, and achieves -18 dB isolation between the energy harvesting module and the data transfer module. A single on-chip monopole antenna for power reception and data transfer is proposed with an adapted layout to reduce power coupling to undesired substrate modes. The simulated antenna shows a gain of -1.68 dBi. The power harvesting performance of the co-integrated antenna, switch and Dickson type multistage rectifier is simulated and leads to a DC output voltage of 1.2 V for -5 dBm input power at 60 GHz. With 15 dBm power transmitted to the tag at 30 GHz, the output voltage is 1.14V in the measurement. This paper is the first to demonstrate the 30 GHz mm-wave wireless energy harvesting with fully on-chip wireless energy receiver.

This paper presents a low-power low-noise amplifier for neural recording applications. A single-stage current-reuse telescopic topology is proposed to achieve high DC gain and improve the noise efficiency factor (NEF) while allowing the amplifier to be scaled for high bandwidth sensing applications and/or to achieve lower thermal noise floor. The design is fabricated in a standard 0.18μm CMOS process and occupies an active area of 0.16mm2. Experimental measurements show a 430nW power consumption from a 1.2V supply, a thermal noise floor of 63.8nV/√Hz and a corresponding NEF of 1.5.

This paper presents a multistandard ultra-low-power (ULP) 2.36/2.4GHz transceiver for personal and body-area networks (PAN/BAN). The presented radio complies with 3 short-range standards: Bluetooth Low Energy (BT-LE), IEEE802.15.4 (ZigBee) and IEEE802.15.6 (Medical Body-Area Networks, MBAN). A proprietary 2Mb/s mode is also implemented to support data-streaming applications like hearing aids. Current short-range radios for Zigbee and BT-LE typically consume more than 20mW DC power, which is rather high for autonomous systems with limited battery energy. The dual-mode MBAN/BT-LE transceiver achieves a power consumption of 6.5mW for the RX and 5.9mW for the TX by employing a sliding-IF RX and a polar TX architecture. However, it suffers from limited RX image rejection and needs a PA operating at a higher supply voltage. In this paper, an energy-efficient radio architecture with a suitable LO frequency plan is selected, and several efficiency-enhancement techniques for the critical RF circuits (e.g., a push-pull mixer and a digitally-assisted PA) are utilized. As a result, the presented transceiver dissipates only 3.8mW (RX) and 4.6mW (TX) DC power from a 1.2V supply, while exceeding all of the PHY requirements of above 3 standards.

Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock.

This paper presents the first monolithically integrated RF-power harvesting 71 GHz wireless temperature sensor node in 65nm CMOS technology, containing a monopole antenna, a 71 GHz RF power harvesting unit with storage capacitor array, an End-of-Burst monitor, a temperature sensor and an ultra-low-power transmitter at 79 GHz. At 71 GHz, the RF to DC converter achieves a power conversion efficiency of 8% for 5 dBm input power.

This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm$^2$. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.

This paper presents fast start-up techniques for duty cycled Impulse Radio receivers. Three different techniques are used to improve the start-up time of individual blocks. DC coupling between the mixer and the VGA is used to ensure a fast start-up time for the whole chain, resulting in an overall start-up time below 10ns. This is the fastest startup time reported for duty cycled Impulse Radio receivers. Moreover, to the best of our knowledge, this is the first paper to detail the start-up techniques that enable ultra-low power consumption in this class of receivers. The measured power consumption is scaling proportionally to the duty cycling rate from 46mW in continuous mode down to 58uW for

A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in the new delay cells, achieving an ENOB of 4.85bit with 1.5GHz ERBW. This ADC consumes 2.7mW at a 1V supply, enabling a FoM of 93fJ/conversion-step. At 0.8V, it can work at 0.5GS/s. Even compared to the state-of-the-art of well-established architectures, it achieves similar power-efficiency.

A fully differential envelope detector (ED) operating at 2.4GHz is designed in 90nm CMOS technology. The new design uses the common-gate topology to deal with large common-mode input signals through first-order current cancellation. Thereby, a fully differential ultra-low power super-regenerative front-end is enabled. It has a measured output voltage swing of 2.8–127mV and achieves 19.6dB output SNR at sensitivity input level. The circuit consumes 3µW from a 1.2V power supply.

Minimizing the power consumption while maintaining performance is paramount in radio transceiver design for low-power wireless sensor network (WSN) applications. Given a sub-mW power budget, many radios have utilized amplitude modulation and envelope detection to eliminate the need for accurate frequency references and to reduce power consumption [1–4]. However, such radios suffer from poor frequency selectivity. They rely on front-end filters to reject out-of-band interference, while in-band interferers still corrupt the desired signal.

Applications like wireless sensor nodes require ultra-low-power ADCs. However, each application has different requirements for accuracy and bandwidth. Recent power-efficient ADCs for sensor applications are mostly designed for a fixed accuracy and a limited range of sample rates [1,2]. An efficiently scalable sample rate (10kS/s to 10MS/s) has been demonstrated before [3], but without scalability of resolution. In [4], an ADC with both flexible resolution and sample rate is reported; however, its power efficiency is not as good as the point-solutions in [1,2]. This paper describes a SAR ADC that achieves both good power efficiency (6.5-to-16fJ/conversion-step) and a wide range of flexibility (7-to-10b resolution, sample rates up to 4MS/s) to cover a large variety of applications, thereby reducing cost, design-time and overall complexity. To optimize the power efficiency for each resolution, both the DAC and comparator are reconfigurable. A 2-step conversion scheme is proposed for 9 and 10b settings to further reduce the power consumption. Finally, the use of an asynchronous architecture and dynamic circuitry ensures that the power consumption scales inherently proportional to the sample rate [3].

This paper presents a flexible SAR ADC in 90nm CMOS for wireless sensor nodes. By supporting resolutions from 7 to 10bit and sample rates from DC to 2MS/s, this design can be used for a variety of applications such as sensor interfacing and receiver frontends. Flexibility is achieved by a reconfigurable comparator and a reconfigurable DAC. Compared to prior art, this work substantially improves power-efficiency and enables low-voltage operation by employing a pseudo-differential DAC switching scheme, offset compensation and simplified asynchronous logic control. The measured chip achieves power-efficiencies of 2.8–6.6fJ/conversion-step at 2MS/s and 0.7V supply. The FOM is maintained down to kS/s-range as the leakage is only 2nW.

This paper presents an ultra-low-power (ULP) 2.3/2.4GHz multi-standard transmitter (TX) for wireless sensor networks and wireless body area networks. Several 2.3/2.4GHz wireless standards have been proposed for such applications, including IEEE802.15.6 (BAN) for body area networks, IEEE802.15.4 (Zigbee) and Bluetooth Low Energy (BLE) for sensor networks and IEEE802.15.4g (SUN) for smart buildings. Recent standard compliant short-range TXs [1-6] typically consume DC power in the range of 20 to 50mW. This is rather high for autonomous systems with limited battery energy. Implemented in a 90nm CMOS technology, the presented TX saves at least 75% of power consumption by replacing several power-hungry analog blocks with the digitally-assisted circuits. This TX is compliant with all 4 of these standards, while dissipating only 4.5mA from a 1.2V supply.

This work investigates power-efficient correction methods for ultra low-power time-interleaved SAR converters. First, analog techniques for gain and offset correction are proposed, and their impact on the overall power efficiency is analyzed. Furthermore, a layout technique for the intrinsic correction of time-skew errors in low-power converters is discussed. Finally, measurement results on a 5bit 1GS/s 16-channel time-interleaved SAR converter are reviewed.

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400 aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90 nm CMOS occupies only 0.11 mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5 GS/s at 0.75 V supply, and 1 GS/s at 1 V supply with 0.47 mW and 1.6 mW power consumption respectively. With an ENOB of 4.7 and 4.8 bits, this leads to energy efficiencies of 36 and 57 fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

An ultra-low-power RF envelope-detection radio has been designed for low-power short-range wireless applications. It introduces an interference rejection technique that improves the in-band selectivity by 24.5 dB. The transmitter adopts the power-efficient direct-modulation architecture, and the receiver maintains the simplicity and low power consumption of envelope detection receivers. In the 915 MHz ISM band at 10 kbps the transmitter output level reaches ${-}$ 3 dBm with 33.9% global efficiency, while the receiver achieves ${-}$83 dBm sensitivity with 121 $mu$W power consumption. The Tx and Rx implemented in 90 nm CMOS technology occupy 0.71 and 1.27 mm$^{2}$ , respectively.

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72μW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9μW.

This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37μW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.

An important drawback of current biopotential monitoring systems is their dependence on gel electrodes, which can dry out, cause skin irritation, and necessitate skilled personnel. These associated drawbacks increase the running costs and significantly hamper their use in consumer healthcare and lifestyle applications. Unfortunately, the use of gel-free, or dry, electrodes increases the electrode-tissue contact impedance, thus exacerbating the effects of interference and cable motion artifacts. A solution is the use of active electrodes, i.e. electrodes in which an amplifier with high input impedance, low noise and good electrode offset rejection is co-integrated (Fig. 17.1.1). Previous active electrodes employed voltage buffers to facilitate the inter-channel gain matching necessary to achieve high CMRR [1]. However, low-noise buffers consume significant power and due to their lack of gain still require a low-noise and thus power-hungry back-end to keep the total integrated noise at acceptable levels. To reduce the total power dissipation, this paper proposes a biopotential monitoring system based on active electrodes with gain.

This paper presents a low-power fast-startup wideband VGA with a 6th-order low-pass filter function for UWB radios. A DC-coupled 6-stage open-loop topology is proposed, which includes DC offset calibration and fast-startup biasing circuits. The prototype in 90nm CMOS occupies only 0.075mm2, including decoupling capacitors and digital interfacing. The circuit consumes 1.6mW from a 1V supply, achieves −1.2dB up to 37.7dB gain with a programmable bandwidth from 80MHz to 460MHz, and achieves a startup-time of 12ns.

An ultra-low power wake-up receiver for wireless sensor network applications is presented. The 915MHz OOK receiver is based on the double-sampling RF power detector architecture. Together with an on-chip ADC, the receiver achieves −86dBm sensitivity at 10kbps, while consuming 123μW. Flexible sensitivity / data-rate / power consumption options are also possible. The receiver front-end is fabricated in a 90nm CMOS technology and wire-bonded in a QFN56 package.

Wireless body-area networks (WBAN) are used for communication among sensor nodes operating on, in or around the human body, e.g. for healthcare purposes. In view of energy autonomy, the total energy consumption of the sensor nodes should be minimized. Because of their low complexity, a combination of the super-regenerative (SR) principle [1-3] and OOK modulation enables ultra low power (ULP) consumption. This work presents a 2.4GHz ULP OOK single chip transceiver for WBAN applications. A block diagram of the implemented transceiver is shown in Fig. 26.3.1. Next to the direct modulation TX [4] and SR RF [5] front-ends, this work integrates analog and digital baseband, PLL functionality and additional programmability for flexible data rates, and achieves ultra-low power consumption for the overall system.

A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant to the IEEE802.15.4a and the upcoming IEEE802.15.6 standard, is presented. The complete, duty-cycled transmitter provides +1dBm peak output power, consuming 4.4mW. The receiver front-end shows +88dBm sensitivity at 0.85Mbps and a digital synchronization algorithm enables real-time duty cycling, resulting in a mean power consumption of 3mW. © 2011 IEEE.