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The world is becoming wireless. In contrast with wired technologies, wireless technologies are widespread in several sectors and they are more and more present in many aspects of life. Wireless includes any technologies which uses no wire. They can be applied for specific applications and have been standardized. (Bluetooth or IEEE 802.15.1, WiFi or IEEE 802.11, ZigBee or IEEE 802.15.4, RFID standardized as ISO 18000, etc). One of the most valuable reasons for the growth of wireless technologies for communications is the requirements for the mobility of modern applications. These requirements, and also security, make wireless technologies one of the best candidates for these applications and for establishing secure communications in traffic vehicular environments, so for vehicle to vehicle (V2V) as well as for vehicle to infrastructure (V2I). Electronic Registration and Identification (ERI) of vehicles is a way to identify a vehicle univocally by means of some kind of wireless technology for communication. This protocol allows a wide range of interesting ITS applications, which involves secure identification of vehicles using symmetrical and asymmetrical techniques. These applications could be applied in private and public services (tolling systems, access to parking lots, information services, etc ). Figure 1 shows a schema which explains the whole architecture in order to understand how ERI standards are settled within an AVI/AEI architecture proposed in ISO 14814. A specific application programming interface of wireless communications developed for Electronic Registration of Vehicles is explained in this chapter as an example of application of this technology. The philosophy of this concept is gathered in the ISO/TS 24534 and ISO/TS 24535 standards, also named ERI standards. This family of standards establishes the architecture of reference to Vehicle Identification independently of the physical technology used, so they do not specify a particular wireless technology to develop any kind of system application (the standard just suggests DSRC technology for deployment of the protocol). In other terms, these standards are linked to the Automatic Vehicle Identification (AVI/AEI) family of standards, which are ISO 14814 to 14816. This family of standards is the framework in which ERI is included. Taking into account what is explained in the standards, ERI protocol allows establishing secure communications between the road infrastructure and the moving vehicles. This is an issue in which several Traffic administrations have been interested in. In this sense

FinFET technology has become the most promising alternative to continue CMOS scaling due to its improved short channel effects. Design flexibility reduces on FinFET based circuits such as SRAM cells due to the effective channel width is determined by an integer number of fins. In this work, the impact of fin height size of FinFET transistors on the simultaneous behavior of soft error sensitivity and SRAM cell static noise margin is investigated. 3-D TCAD Sentarus environment is used to quantify the amount of collected and critical charges of an SRAM cell due to a heavy ion strike while Mix-Mode Hspice-TCAD simulation is used for stability analysis. Even more, the influence of process variations on sensitivity to soft errors and cell stability is considered. A 10 nm-SOI Tri-Gate FinFET technology is used. Results show that increasing the fin height of FinFET transistors considerably increases SRAM cell sensitivity to soft errors but improves its stability. This suggests that the optimum fin height value of FinFET transistors of an SRAM cell depends on the best tradeoff between soft error robustness and stability.

Eight-transistor (8T) cells were introduced to improve variability tolerance, cell stability and low-voltage operation in high-speed SRAM caches by decoupling the read and write design requirements. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM. Ionizing radiation effects are nowadays a major concern for reliability and dependability of emerging electronic SRAM devices, even for sea-level applications. In this paper we demonstrate from experimental results that the 8T-SRAM also exhibits an enhanced overall intrinsic tolerance to alpha particle radiation even though its critical charge values are smaller than conventional 6T cells. We have experimentally found that the soft error rate measured in accelerated experiments with alpha particles in SRAM devices implemented in a 65 nm CMOS is 56% better for 8T cells with respect to standard 6T-cells. Even more, we show that this value can be increased up to a 200% through transistor sizing optimization.

Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different VDD and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when VDD and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of VDD and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when VDD is lowered, and increases even more when RBB is applied at Low VDD. The test conditions to improve resistive bridge detection combining Low VDD and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of VDD. The values of Low VDD and RBB can be selected considering the tradeoff between fault coverage and test time penalization.

Noise pollution caused by vehicular traffic is a common problem in urban environments that has been shown to affect people's health and children's cognition. In the last decade, several studies have been conducted to assess this noise, by measuring the equivalent noise pressure level (called L eq ) to acquire an accurate sound map using wireless networks with acoustic sensors. However, even with similar values of L eq , people can feel the noise differently according to its frequency characteristics. Thus, indexes, which can express people's feelings by subjective measures, are required. In this paper, we analyze the suitability of using the psychoacoustic metrics given by the Zwicker's model, instead of just only considering L eq . The goal is to evaluate the hardware limitations of a low-cost wireless acoustic sensor network that is used to measure the annoyance, using two types of commercial and off-the-shelf sensor nodes, Tmote-Invent nodes and Raspberry Pi platforms. Moreover, to calculate the parameters using these platforms, different simplifications to the Zwicker's model based on the specific features of road traffic noise are proposed. To validate the different alternatives, the aforementioned nodes are tested in a traffic congested area of Valencia City in a vertical and horizontal network deployment. Based on the results, it is observed that the Raspberry Pi platforms are a feasible low-cost alternative to increase the spatial-temporal resolution, whereas Tmote-Invent nodes do not confirm their suitability due to their limited memory and calibration issues.

Random Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is derived by applying statistical and physics based Montecarlo modeling to the experimental data. Results show that RTN can have a significant impact on the memory write operations and should therefore be taken into account during the memory design phase

The classical IC integration roadmap has followed the Moore law for decades bringing up an impressive transistor scaling evolution resulting in a profound transformation of our quotidian practices. Current trends face the development of integrating multi-domain magnitudes within current systems, demanding a wider diversification of the parameters being managed and enabling what has been named as the More than Moore paradigm. The monolithic integration of such diversity of magnitudes is a challenge that will enable low-cost, highly complex personal systems. A view for the specific microelectromechanical domain will be shared.

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal VDD. A specific VWL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a VWL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65 nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of VWL with a small impact on read time.

Micro and nanoelectromechanical system (M/NEMS) devices constitute key technological building blocks to enable increased additional functionalities within integrated circuits (ICs) in the More-Than-Moore era, as described in the International Technology Roadmap for Semiconductors [...]

The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed. The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed on signal paths.

Wireless Sensor Networks (WSNs) are composed of spatially distributed autonomous sensor devices, named motes. These motes have their own power supply, processing unit, sensors and wireless communications However with many constraints, such as limited energy, bandwidth and computational capabilities. In these networks, at least one mote called a sink, acts as a gateway to connect with other networks. These sensor networks run monitoring applications and then the data gathered by these motes needs to be retrieved by the sink. When this sink is located in the far field, there have been many proposals in the literature based on Collaborative Beamforming (CB), also known as Distributed or Cooperative Beamforming, for these long range communications to reach the sink. In this paper, we conduct a thorough study of the related work and analyze the requirements to do CB. In order to implement these communications in real scenarios, we will consider if these requirements and the assumptions made are feasible from the point of view of commercial motes and their constraints. In addition, we will go a step further and will consider different alternatives, by relaxing these requirements, trying to find feasible assumptions to carry out these types of communications with commercial motes. This research considers the nonavailability of a central clock that synchronizes all motes in the WSN, and all motes have identical hardware. This is a feasibility study to do CB on WSN, using a simulated scenario with randomized delays obtained from experimental data from commercial motes.

[EN] Archaeological acoustics is the study of ancient environments that were used for performances. The combination of this study with room acoustics enables us to study the acoustic evolution of existing buildings, and make reconstructions of rooms that were destroyed or are in a poor state of conservation. This work presents the virtual acoustic reconstruction of the fourteenth century church of the Jeromite monastery of Santa Maria de la Murta in Alzira, Spain. It was abandoned in 1836 and is now in ruins. The work develops a geometrical model for acoustic simulation, together with a description of the building materials as taken from the historical documents, and an acoustic study of the church. Finally, auralizations in various locations have been made. These auralizations are built around important centres of attention in the use of the church: the organ; the choir; and the reading of a church service from the presbytery., This work has been performed by members of the microcluster Grupo de analisis cientifico de bienes culturales y patrimoniales y estudios de ciencia de la conservacion (Ref. 1362) belonging to the Valencia International Campus of Excellence. Financial support is gratefully acknowledged from the Spanish "I+D+I MICINN" projects CTQ2014-53736-C3-1-P and CTQ2014-53736-C3-2-P supported by ERDF funds. The authors wish to thank Dr. Jose Luis Moya Lopez and Mr. Manuel Planes Insausti (Microscopy Service of the Universitat Politecnica de Valencia) for the technical support.

EU Directive 49/2002 and Spanish law 37/2006 urge cities to develop strategic noise maps and action plans to evaluate noise exposure and to establish noise abatement procedures in critical areas. However, noise mapping involves costly and cumbersome measurement procedures that can become a real issue in practice. This paper describes a distributed noise monitoring system based on WASN (Wireless Acoustic Sensor Network) and the application of a geo-statistical methodology for statistical spatial-temporal prediction of noise levels in semi-open areas, such as a typical, small Mediterranean city (Algemesí, València, Spain). This methodology is applied to the study of the spatial evolution in time of the noise pollution. To this end, a spatial statistical model is developed by using the noise pollution measurements obtained over a set of points located at some strategic locations. The geo-statistical time model allows for estimating specific noise levels and characterizing the spatial-temporal variation of the noise pollution. The results show that the developed model provides a good approximation of the measurements obtained experimentally.

Resistive bridges are a major class of defects in nanometer technologies that can escape test, posing a serious reliability risk for CMOS IC circuits. The increase of process parameter variations represents a challenge for resistive bridge detection using traditional test methods, and requires more efficient test methods to be developed. In this work, we show that resistive bridge detection improves by correlating the defect-induced extra circuit delay with the power supply voltage value and the reverse body bias (RBB) applied. A Timing Critical Resistance ( R crit t ) is defined as a metric to quantify the resistive bridge detection enhancement in the presence of process variations under a delay based test. We show that the smaller the supply voltage, the higher the resistive bridge detection which further enhances by applying RBB. Results are presented for a 65 nm CMOS technology.

Failure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests.

We present a single event transient (SET) propagation model that can be used to quantify the propagation likelihood of a given noise waveform trough CMOS logic gates. This analysis is key to predict if an SET induced within a combinational block is capable of causing an SEU. The model predicts the output noise characteristics given the input noise waveform for each gate, and can be applied to any CMOS technology through a one-time library parameter extraction process. Pulse propagation is described through continuous analytical functions that convert an SET pulse height and width at the gate input to an SET pulse height and width at its output. The noise transfer curves have relatively simple analytical continuous expressions suitable for an easy adoption within CAD tools, thus allowing the investigation of pulse propagation through an entire logic block. Comparison between simulations and model show a very good agreement for a commercial 65 nm technology.

We analyze and compare the impact of radiation-induced transient effects based on evaluating the critical charge parameter for 6T and 8T SRAMs during hold, read and write operations. Results on a commercial 65 nm CMOS technology show that 6T and 8T cells offer quite similar robustness when they are in hold. However, the critical charge observed in other operation modes is reduced a 55% respect to the hold operation. For this reason, we provide a thorough analysis of the critical charge behavior in 6T and 8T SRAMs to determine the dependence of memory radiation robustness with memory state. Single event upsets and single event transients have been considered in the analysis, showing that 8T have better performance than 6T. The dependence of critical charge with memory state for high workload memories modifies the overall memory SER estimation indicating the significance of analyzing the memory robustness as a memory state function. In general, the SER estimation results show that the robustness behavior of 8T-based cells is better than robustness behavior of 6T-based cells.

The study of rooms devoted to sound transmission has become a discipline in which all the fundamentals areas of current scientific research in acoustics converge. To demonstrate how this convergence arises in this work, we present a complete and detailed acoustics study of the Sant Jaume Basilica in Algemesí (Valencia, Spain), a building which has been declared a site of cultural interest. Starting from this overall perspective, the first part of this paper describes the features of the room studied (chosen for its complexity), the usual parameters for the analysis of room acoustics, and two measurement methodologies and two simulating methods widely used by the scientific community. Based on the theoretical results (obtained from modelling) and measurements following the recommendations of ISO 3382 Standard [1], we study the errors in 'just noticeable differences' in acoustic parameters that a listener may perceive. The aim of the study is to highlight the drawbacks and successes of the procedures used. From the perspective of comparing the results, the purpose of this study is not to assess the experimental procedures themselves or the modelling systems, but rather to demonstrate, using the four possible measurement-calculation combinations, whether the differences obtained between the theoretical values and experimental values are within a reasonable range of acceptability., The translation of this paper was funded by the Universidad Politecnica de Valencia, Spain.

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell-size increase. The other solution is based on multithreshold voltage selection showing a moderate immunity improvement at the cost of no impact on the cell area. The combination of both techniques is shown to be optimum when considering other design metrics like static noise margin, read/write stability, access time, and leakage. Results are demonstrated on 90- and 65-nm commercial technologies.

In this article, we analyze the impact of within-die thermal gradients on clock skew, considering temperature's effect on active devices and the interconnect system. This effect, along with the fact that the test-induced thermal map can differ from the normal-mode thermal map, motivates the need for a careful consideration of the impact of temperature gradients on delay during test. After our analysis, we propose a dual-VDD clocking strategy that reduces temperature-related clock skew effects during test. Clock network design is a critical task in developing high-performance circuits because circuit performance and functionality depend directly on this subsystem's performance. When distributing the clock signal over the chip, clock edges might reach various circuit registers at different times. The difference in clock arrival time between the first and last registers receiving the signal is called clock skew. With tens of millions of transistors integrated on the chip, distributing the clock signal with near-zero skew introduces important constraints in the clock distribution network's physical implementation and affects overall circuit power and area

Silicon-on-insulator (SOI) is emerging as a strong technology candidate for low-power high-performance applications. In this work, based on experimental data, we review the fundamental aspects of leakage current in deep-submicron SOI CMOS technologies discussing the underlying physical mechanisms and their dependence with bias, temperature and operating frequency. These mechanisms and their evolution with technology scaling are compared to those of bulk CMOS. Subsequently, we evaluate the merits of parametric I-DDX testing techniques based on current monitoring when applied to these technologies. (C) 2003 Published by Elsevier Ltd.

We present a Built-In-Current-Sensor (BICS) based on monitoring a signature of the supply current peak of CMOS OpAmps using the oscillation-test-strategy. The BICS takes a weighted sample of the current through two OpAmp current branches and monitors a signature of the peak value under oscillation. Two current-based comparators and some digital circuitry are used to provide a pass/fail flag. Simulation results demonstrate a high defect coverage with a very small impact both on the OpAmp nominal operation and the area overhead.

A comparison of the merits and possibilities of considering the output voltage and the negative supply current as test observables when using the Oscillation-test technique is carried out. The method is applied to CMOS opamps considering an exhaustive analysis of catastrophic defects (opens, shorts), GOS and floating gates using HSPICE. We analyze deviations in both frequency and signal amplitude of each observable comparing their sensitivity to defects. Results show that the supply current peak value provides the highest defect coverage for a single opamp oscillator, while the oscillating frequency provides the highest fault coverage for a double opamp oscillator.

The usual parameters in room acoustics are used to quantify the acoustic characteristics of rooms and their relation to the subjective perception of transmitted signals. Audio features (calculated with MIRToolbox) have been designed to study the relationships between the characteristics of musical audio files and their subjective perception. Both musical characteristics and acoustic parameters are oriented towards acoustic perception. By using auralizations with calibrated models of auditoriums and tools from the MIRtoolbox it is possible to jointly work with the calculation of audio features and room parameters. In this work, the statistical correlations between C80, STI, D50, EDT, RT and certain audio features have been analyzed. The Pearson r values are higher than 0.8 in all cases. These high correlations enable acoustic parameters to be calculated from the musical characteristics of auralized audio signals., This study was supported with FEDER funds, the Spanish Ministry of Science and Innovation supported the present study in a Coordinated Investigation Project Framework (Grant Nos. BIA2003-09306-C04 and BIA2008-05485).

Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening. One is related to increasing the number of fins of the transistors composing the cross-coupled inverters. This option provides a significant increase of the cell critical charge (Q crit ), but with a cost in area. The other alternative increases the transistors fin height. Results show that a similar Q crit gain is achieved by increasing the fin height instead of the number of fins without area overhead. The impact of process variations has been considered. Q crit distribution has been modeled through an statistical approach based on Design of Experiments. Results are presented for a 10nm-SOI Trigate FinFET technology.

Bridge defects are an important manufacturing defect that may escape test. Even more, it has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods. Therefore, advances in test methodologies to deal with nanometer issues are required. In this work the feasibility of using Low VDD and body bias in a delay based test to detect resistive bridge defects in CMOS nanometer circuits is analyzed. The detection of bridge defects using a delay based test in nanometer circuits is strongly influenced by: (1) spatial correlation of the process parameters such as length, width and oxide thickness of the transistor, (2) random placement of dopants, and (3) the signal correlation due to reconvergent paths. Because of this, in this work a Statistical Timing Analysis Framework (STAF) is used to analyze the possibilities of detection of bridge defect using a delay based test. The STAF considers different values of VDD and body bias. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage that gives a more realistic measure of the degree of detection of the defect. This methodology is applied to some ISCAS benchmark circuits implemented in a 65nm CMOS technology. The obtained results show the feasibility of the proposed methodology.

The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.

This undergraduate textbook for electrical and computer engineering students is dedicated solely to digital CMOS electronics. It covers many of the topics of graduate level textbooks, but in an introductory style specifically crafted (and course tested) for undergraduates. Students will not need a prerequisite in analog electronics, allowing instructors flexibility in course scheduling. This book blends the academic and industrial experience of the authors to define a base of electronics instruction for the CMOS chip industry. CMOS Digital Integrated Circuits: A First Course teaches the fundamentals of modern CMOS technology by focusing on central themes and avoiding excessive details. Extensive examples, self-exercises, and end-of-chapter problems assist in teaching the current practices of industry and subjects taught by graduate courses in microelectronics. Computer engineering curriculums can remove the analog electronics prerequisite altogether when adopting this book. Key Features: CMOS technology written specifically for (and tested by) undergraduates; Equal treatment to both types of MOSFET transistors that make up computer circuits; Power properties of logic circuits; Physical and electrical properties of metals; Introduction of timing circuit electronics; Introduction of layout; Real-world examples and problem sets.

We present a glitch propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the glitch output characteristics given the input noise waveform for each gate in a 65- nm technology library. These noise transfer curves are fitted to known functions to have a simple analytical equation and compute the propagation. Comparison between simulations and model shows a good agreement.

We present a new 8-transistor (8T) SRAM cell design that uses pMOS devices as cell pass transistors controlled by the write word-line signal. The main advantage of this schema is the composition of a balanced 8T SRAM cell having four nMOS and four pMOS transistor that enables a more compact layout and area reduction. An exhaustive analysis about the impact on key parameters such as leakage consumption, write and read stability margins, read delay time and single event upsets for the new cell is reported. A trade-off between cell area reduction and write noise margin improvement is observed, while the remaining parameters are not impacted.

Physical defects widely encountered in today’s CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.

Although many integrated circuit processing or in-field defects change the functional behaviour of the circuit and may be detected by classical testing techniques, small spot and break defects in the active area of the transistors may just cause electrical parameter changes. In our work, experimental results are presented in order to characterize the behaviour of a class of such faulty devices. A fault model for gate oxide shorts is presented and used to analyse the conditions under which a typical CMOS inverter becomes functionally faulty. Static current inspection testing technique is considered for this kind of fault, proposing a static current circuit checker.

We present the design and operation of a monitor circuit that captures the effect of ionizing particles on sensitive CMOS IC internal nodes. The circuit implements a Single Event Effects (SEE) detector and a quick sampling block that captures the SEE induced waveform shape currents during a certain time window. These values can be read externally through a dedicated decoding circuitry. The circuit has been designed and fabricated on a 130nm technology. Preliminary experimental results and detailed simulations are provided to demonstrate the feasibility of the system implemented.

Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed as a detection scheme for single event upsets in SRAM. In this paper, Power-Bus current transients in SRAM memories for Single Event Upset Detection have been analyzed in a 65nm CMOS technology. The different types of current roles which are applied during the simulation is discussed. The results show the important contribution of leakage currents in the response of the memory cell to an external event.

The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. In this work it is shown that this failure mechanism is very alive and relevant to modern technologies. The small nanometer technology capacitances and the increased leakage currents result in faster discharges of the floating high impedance node making fault detection more difficult. A test vector strategy is proposed to improve the detection of this fault for technologies with gate current leakage.

We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all pmos or all nmos transistors of the cell. The first technique does not affect the cell layout. The second one increases the minimum width of all pmos by a factor c p and the minimum width of all nmos by a factor c n . This prevents the formation of diffusion bends, allowing structured layouts. Both techniques provide an improvement in SEU robustness.

The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology [1–3]. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. This defect defies a guaranteed 100% detection. We will show that this mostly discarded failure mechanism is very relevant to modern ICs. Current leakage in nanoscale technologies influence significantly the behavior of this fault.

The electronic registration and identification (ERI) systems allow carrying out a remote, secure and univocal identification of a vehicle through electronic devices. This paper presents the implementation of the ERI standard (ISO 24534 & 24535) in an API to develop applications. The implementation took into account the different components of the system to build the architecture of the identification system. Several applications have been developed in order to test this API with several low-cost technologies (Wifi, Bluetooth and RFID).

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12mm technology showing excellent results., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

CMOS technology scaling has been a constant since its initial development in the early 70’s as an effort to obtain ICs working at higher operating frequencies that perform more operations per unit area. Each advance in CMOS technology scaling is called a technology generation, or a technology node, and pursues the ability of fabricating smaller transistors. A new technology generation doubles the number of transistors per unit area, increases operating frequency by more than 40%, reduces the energy per transition by more than 60%, while reducing transistor cost. Technology nodes are reached at a constant pace, a rule known as Moore’s law, which currently brings one new generation every 18 months. Moore’s law is possible thanks to the scalability of the basic unit used to implement digital switches: the MOSFET transistor. Today ICs contain transistors having minimum geometries of 90 nm (1nm = 10 –9 m), and industry is now rapidly moving into the 65 nm technology node. Chips today contain hundreds of millions of transistors and operate at frequencies on the order of 5 GHz. They incorporate a variety of circuit blocks

In this work we present an analytical formulation to estimate quickly and accurately the impact of crosstalk induced delay in submicron CMOS ICs gates taking into account time skew. Crosstalk delay is computed from the additional charge injected from the aggressor gate on the victim gate during simultaneous switching. The model provides a very good agreement with HSPICE simulations for a 0.18 /spl mu/m technology.

We present a novel technique to accurately describe the leakage power in CMOS nanometer Integrated Circuits (ICs) considering process variations. The model predicts a leakage power increment due to process variations with high accuracy. It is shown that leakage increases considerably as channel length variations become larger due to technology scaling. The present work also describes accurately the dependence of leakage dispersion with process variations. The model developed shows that, even if channel length variations are kept small the leakage dispersion is considerably large. Finally, the concept of “Hot Gates” (HGs) is introduced, showing that HGs will be an important reliability factor in near future nanometer technologies.

Timing failures have been with CMOS ICs forever. Initially, timing failures were comparatively minor, but are now are a plague in many products. This article summarizes the timing properties of the subcircuits that together affect overall timing performance. We then discuss the subtleties of real failures. Test engineers must understand the design issues to deal with IC timing failures.

In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses a ring-oscillator composed of complex gates instead of inverters to optimize their linearity. Simulation results from a 0.18$\mu$m CMOS technology show that the non-linearity error of the sensor can be reduced when an adequate set of standard logic gates is selected., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

As chips become faster, the need to test them at their intended speed of operation has been recognized. High-speed operation, together with the higher switching activity typically induced during test, can result in a die-thermal distribution significantly different from that achieved during normal operation. Differences in thermal map distribution between normal- and test-mode operations give rise to a non-uniform impact on the relative path delay within logic blocks. The impact of test-induced hot spots may artificially slow down non-critical paths or speed-up critical ones with respect to the clock making the whole die to fail (pass) delay testing for a good (bad) part. The non-uniform thermal-induced delay is especially important for clock circuitry, the most critical block, which is impacted even if exact zero-skew clock routing algorithms are adopted. In this work we analyze the impact of thermal map temperature changes on the clock delay identifying a new delay-fault mechanism. We propose a technique to minimize the impact of different test- and normal-mode thermal maps by making the clock tree speed independent of temperature gradients. This technique allows applying confidently delay test patterns to the die regardless of the thermal-map test-induced modification.