Search

The electrooptical characterization of three groups of CMOS image sensors with front-side illumination based on the different technologies namely CMOS 0.35 [mu]m-technology, novel CMOS/SOI 0.35 [mu]m-technology and CMOS 0.5 [mu]m-technology is reported. It is found that there is strong dependence of quantum efficiency of the photodiodes on the architecture of the image sensor which are useful for designing and modeling CMOS/SOI image sensors.

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed. Index Terms--Cyclotron, heavy ion, microprocessors, silicon on insulator.

Heavy-ion-induced SET-pulse widths in NOR-logic cells fabricated by a 0.2-[micro]m FD-SOI technology are directly measured by using an on-chip self-triggering Flip-Flop circuit. The pulse widths are distributed from 0.3 to 1.0 ns under a constant LET of 40 MeV x [cm.sup.2]/mg. Index Terms--Direct measurement, heavy ion irradiation, silicon on insulator technology, single event transient.

This paper discusses the practical limits of proton and heavy ion induced single event upset cross sections in SEU hardened deep submicron SOI SRAMs. Non-conventional 'double-hit' mechanisms are hypothesized to explain test results. Index Terms--SEU, SOI, SRAM, upset mechanism.

We designed logic cells hardened for SEUs/SETs using hardness-by-design (HBD) methodology with OKI's 0.15 [micro]m Fully Depleted CMOS/SOI commercial process and these cells were evaluated with sample devices. Our previous work demonstrated that SET-free inverters could be successfully applied as SEU-immune latches. In this work, the logic cells were optimized for SEU/SET immunity up to an LET of 64 MeV/(mg/[cm.sup.2]), demonstrating that the process was suitable for space applications with a little penalty. Index Terms--Commercial process, fully depleted CMOS/SOI, hardness-by-design, SET, SEU.

Current components of heavy-ion-induced transient currents in a 0.2-[micro]m fully-depleted SOI MOSFET are analyzed in the time domain. The analysis demonstrates that the transient currents have another slow-decay current component that is different from the two conventional current components: a prompt discharge current and a slow-decay parasitic bipolar current. The slow-decay component revealed here is a flow of deposited carriers stored in the body region to maintain quasi-neutrality, and it drastically widens the transient pulse. Index Terms--Heavy ions, parasitic bipolar transistor, silicon on insulator (SOI) technology, single event transients, time domain analysis, transient currents.

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored. Index Terms--Alpha particle, modeling, radiation event, single-event upset, soft error.

Delayed charge collection from ionizing events outside the deep trench can increase the SEU cross section in deep trench isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect can be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer in the substrate can reduce the delayed charge collection from events that occur outside the deep trench isolation by almost an order of magnitude, implying an approximately comparable reduction in the SEU cross section. Index Terms--Deep trench isolation, Ion Beam Induced Charge Collection (IBICC), silicon germanium, Single Event Upset (SEU), substrate engineering.

The statistical transient response of floating body SOI and bulk devices is measured under proton and heavy ion irradiation. The influence of the device architecture is analyzed in detail for several generations of technologies, from 0.25 [micro]m to 70 nm. The effects of the measured transients on SET sensitivity are investigated. The amount of collected charge and the shape of the transient currents are shown to have a significant impact on the temporal width of propagating transients. Finally, based on our measured data, the threshold LET and the critical transient width for unattenuated propagation are calculated for both bulk and floating body SOI as a function of technology scaling. We show that the threshold LETs and the critical transient widths for bulk and floating body SOI devices are similar. Body ties can be used to harden SOI ICs to digital SET. However, the primary advantage of SOI technologies, even with a floating body design, mostly lies in shorter transients, at a given ion LET, for SOI technologies than for bulk technologies. Index Terms--Collected charge, heavy ion and proton irradiation, single event transient, SOI and bulk transistors, statistical response, transient current, transient width.

N-channel trigate SOI MOSFETs have been irradiated with [sup.60]Co gamma rays at doses up to 6 Mrad(Si[O.sub.2]). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 [micro]m. At 6 Mrad(Si[O.sub.2]), the current drive reduction in the same devices is 10% if [V.sub.G] = 0 V during irradiation and 20% if [V.sub.G] = 1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (ll0)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [ < 1 Mrad(Si[O.sub.2])]. At higher doses, the usual mobility degradation caused by interface trap generation is observed. Index Terms--MOSFETs, semiconductor device radiation effects, silicon on insulator technology.

This paper investigates the total ionizing dose response of advanced nonplanar triple-gate transistors with short gate length, as a function of device geometry. Experiments and three-dimensional (3-D) simulations using a radiation dedicated code are used to analyze the buildup of a trapped charge in the buried oxide and its impact on the device electrical characteristics. The behaviors of three prospective nonplanar devices are detailed and compared to the total ionizing dose degradation of a planar fully depleted single-gate architecture. The [OMEGA]-gate FET is shown to be the most tolerant to a 500 krad(Si[O.sub.2]) total dose exposure thanks to the efficient control provided by the lateral gates over the electrostatic potential throughout the Si film and essentially at the Si fin/BOX interface. Index Terms--Fully depleted, multiple-gate transistors, nonplanar architectures, silicon-on-insulator (SOI), total ionizing dose tolerance.

X-ray total ionizing dose effects in both fully-depleted and partially-depleted SiGe HBT-on-SOI transistors are investigated at room and at cryogenic temperatures for the first time. Devices irradiated in grounded and forward-active mode configurations exhibit a different behavior depending on the collector doping of the device. The degradation produced by 10 keV x-rays is compared to previously reported 63 MeV proton results on the same fully-depleted SiGe HBT-on-SOI devices, showing decreased degradation for proton irradiation. Both collector and substrate bias are shown to affect the two-dimensional nature of the current flow in these devices, resulting in significant differences in the avalanche multiplication characteristics (hence, breakdown voltage) across temperature. Index Terms--Heterojunction bipolar transistors, radiation effects, SiGe HBT, silicon-on-insulator technology, SOI, TCAD.

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by ionizing radiation exposure have diminished by aggressive semiconductor scaling, the question remains whether there may be unknown, potentially worse threats lurking in the deep sub-micron regime. This manuscript provides a basic overview of some of the materials, devices, and designs that are being explored or, in some cases, used today. An overview of radiation threats and how radiation effects can be characterized is also presented. Last, the paper provides a detailed discussion of what we know now about how modern devices and materials respond to radiation and how we may assess, through the use of advanced analysis and modeling techniques, the relative hardness of future technologies. Index Terms--1/f noise, high-k, interface traps, oxide trapped charge, radiation, RILC, shallow trench isolation, silicon-on-insulation (SOI), total ionizing dose.

We designed logic cells hardened for single-event upsets/singe-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 [micro]m fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR. Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/[cm.sup.2]). Index Terms--Commercial process, fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI), hardness-by-design (HBD), single-event transient (SET), single-event upset (SEU).

Low-power radiation-hardened sequential digital circuits supporting multiple supply voltages, integrated logic, and a low standby power state are presented. By basing the design on proven radiation hard circuits, single event effects hardness is guaranteed. The circuit is based on differential cascode voltage switch logic, which provides an integral level shift and allows storage at the full supply voltage supported by the process, while allowing the combinatorial logic supply voltage to scale for power savings. When compared to a conventional master-slave flip-flop design, the proposed flip-flop design provides up to 80% energy reduction with logic operating at reduced voltage and speed. Fifty-percent energy reduction is obtained without compromising speed when operating with all circuits at maximum voltage. Index Terms--Flip-flop, low power, low standby power, multiple power-supply voltages, radiation hardening, silicon on insulator.

Partially depleted (PD) 0.15 [micro]m CMOS silicon-on-insulator (SOI) SRAMs were exposed to heavy ions, 14 MeV neutrons, and protons. The upset threshold and saturated cross section LET values were determined from heavy ion exposures. The SRAMs were then exposed at various angles of incidence with respect to a 14 MeV neutron source to a total fluence of 4 x [10.sup.13] n/[cm.sup.2]. The number of upsets from front exposure was more than double the number from back exposure. Following neutron exposure, proton upset measurements were performed. For a given fluence, the number of proton induced upsets was essentially identical to the number of neutron induced upsets. Index Terms--Random access memories, silicon-on-insulator technology, single event upset.

The degradation of deep submicrometer (0.1 [micro]m) fully depleted silicon-on-insulator n-MOSFETs subjected to 2-MeV electron irradiation at different temperatures is reported. The radiation-induced damage is investigated by studying the static characteristics of devices with different geometries and bias conditions. The change of the front and back-channel parameters, the impact of the gate coupling effect and the gate-induced floating body effects and the irradiation temperature dependence of these degradations are clarified. It is found that the degradation of the electrical properties tends to be small for high temperature irradiation compared with that for room temperature. Index Terms--Electron irradiation, gate coupling, high-temperature irradiation, fully depleted silicon-on-insulator (FD-SOI), MOSFET.

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a Ti[Si.sub.2] Schottky gate and display good depletion mode characteristics with a threshold voltage of -0.5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The transistors have been irradiated with 50 keV X-rays to a total ionizing dose in excess of 1 Mrad(Si). After irradiation the threshold voltage of both the top Schottky gate and the back MOS gate shift to more negative values. The shift in threshold is attributed to radiation induced fixed oxide charge at the interface between the SOI channel and the buried oxide. Index Terms--MESFETs, silicon-on-insulator technology, X-ray effects.

Total ionizing dose effects are investigated for the first time in deca-nanometer fully depleted (FD) silicon-on-insulator (SOI) devices. Charge trapping and the influence of device architecture are investigated in transistors with and without external body contacts. A radiation-induced high current regime is measured in floating body devices, both at high and low drain voltages. The mechanism responsible for the onset of this high current regime is investigated by 2D numerical simulations, and shown to result from the combined effect of short gate length and floating body potential in the intrinsic Si film. Transistors with a doped Si film are less sensitive to the high current regime. The use of external body contact in the device architecture completely stops the onset of high current regime, whatever the device gate length. Index Terms--Fully depleted, NMOS transistors, silicon on insulator, total dose irradiation.

This paper investigates the sensitivity of SOI and Bulk SRAMs to neutron irradiations with energies from 14 to 500 MeV. The technology sensitivity is analyzed with both experiments and Monte Carlo simulations. In particular, simulations include the nuclear interactions of neutrons with both silicon and oxygen nuclei In-St and n-O), in order to investigate the influence of isolation upper layers on the device sensitivity. The device cross-sections are analyzed for mono-energetic neutron irradiations and discussed in terms of nuclear interaction type (n-St and n-O) and distribution of the secondary ion recoils. We also investigate the dimensions of the interaction volume around the sensitive cell as a function of the device architecture. Index Terms--Bulk technologies, SOI technologies, neutron effects, soft error rate (SER), single-event upset (SEU), Monte Carlo methods.

The SEU sensitivity of 0.2 [micro]m fully depleted silicon on ensulator (FD-SOI) devices to proton and neutron irradiations is investigated in a large energy range (14-500 MeV). The comparison to bulk devices with similar gate lengths shows an improvement of a factor of 50 with the presence of body ties. Monte Carlo simulations were performed to confirm that the low sensitivity of FD-SOI is mainly due to the reduced sensitive volume. These results were extrapolated to deca-nanometric technologies to predict the behavior of advanced SOI processes. We found that fully depleted devices will be far less sensitive than partially depleted technologies to the terrestrial radiative environment. Index Terms--Neutron, proton, SEU, SOI, SRAM.

We present the first experimental data about the wear-out of a 0.1 [micro]m partially depleted SOI CMOS technology after heavy ion irradiation. We show that accelerated life tests based on high electric fields yield significant differences between irradiated and nonirradiated devices, even though no or only minor changes are visible in the characteristics of the devices after irradiation. First, the time to breakdown of the front gate oxide is significantly lower in the irradiated samples. The fresh devices experienced breakdown after 5-8 x [10.sup.22] electrons/[cm.sup.2] were injected across the oxide during high field electrical stress. In the irradiated oxide, the breakdown was reached at much lower injected charge values, between 0.5 x [10.sup.22] electrons/[cm.sup.2] and 1.5-1 x [10.sup.22] electrons/[cm.sup.2] depending on the ion fluences. This translates into a lifetime reduction of 10%-20% of its initial value. Furthermore, the degradation kinetics of the threshold voltage and transconductance peak are strongly affected by ion strikes. In particular, a sudden shift of the threshold voltage and an acceleration in the degradation of the transconductance peak were observed upon the application of an electrical stress, which have no correspondence in nonirradiated devices. An acceleration in the degradation of the parasitic back transistor was observed as well. These phenomena were interpreted in terms of latent damage left by the irradiation in the oxides that make up SOI devices. Index Terms--CMOS devices and integrated circuits reliability, gate oxide reliability, radiation effects on MOSFETs, silicon on insulator.

Expensive and time-consuming three-dimensional (3-D) simulations have been previously employed to characterize single-event upsets of integrated circuits. This paper outlines a more practical engineering approach to SOI single-event effects modeling that involves simple closed-form one-dimensional (1-D) solutions to the carrier transport equations. Using Fourier analysis, the transport equations have direct 1-D closed form solutions for 'low injection' conditions. One-dimensional numerical solutions are also obtained for 'high injection' conditions (i.e., when the excess injected carrier concentration exceeds the background doping), including other nonlinearities such as the dependence of mobility on both the background concentrations and excess carrier concentrations. The 1-D equations for low injection are reasonable approximations for high injection in n-type material, but not for high injection in p-type material. However, a simple 1-D equation can still be used for high injection in p-type material. The 1-D equations are used with existing simple SPICE models, including models for the parasitic bipolar transistors. The 1-D model agrees well with predictions from 2-D and 3-D simulations. A circuit cell layout can be broken into various regions with differing SEU sensitivities, each with its own characterizing 1-D equation. This simple method leads to a theoretical prediction of cross-sectional area versus upset linear energy transfer (LET) that is in good agreement with experimental heavy ion SEU data for an SRAM. The method also accounts for strike angles in three dimensions. Index Terms--SEU, SEE, SPICE, SRAM, SOI, modeling, Medici.

A new analytical model for the surface potential and the threshold voltage of a silicon-on-insulator (SOI) MOSFET with electrically induced shallow source/drain (S/D) junction is presented to investigate the short channel effects (SCEs). The results reaffirm that the application of induced S/D extension to the SOI MOSFET will successfully control the SCEs for channel lengths even less than 50nm.

A description of a surface potential-based compact model is presented for high-voltage LDMOS transistors. The model combines the low-voltage MOS region with the high-voltage drift region of an LDMOS transistor.

The advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters is analyzed. A method for full comparison between conventional and GC SOI MOSFETs is presented, considering HD3 evolution with on-resistance tuning under low voltage of operation.

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was fabricated, and the S/D asymmetric effect induced by gate misalignment was studied. It was found that for a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side.

This paper investigates the charge collection mechanisms occurring in heavy ion irradiated metal oxide semiconductor (MOS) devices. The parasitic bipolar effect, inherent to the structure of SOI transistors, is shown to exist in bulk NMOS transistors as well. We experimentally show that the drain junction of an OFF-state bulk MOS transistor collects more charge than an identical junction isolated from neighboring elements. In other words, the proximity of the source junction and the triggering of the bipolar-like structure are responsible of charge amplification. A higher current peak on the drain is observed, and this enhancement effect is high enough to invalidate usual charge collection models based only on funnel and diffusion transport. Thus, the proximity of other junctions has to be considered to improve charge collection model in bulk technologies. Index Terms--Bipolar amplification, bulk and SOI transistors, charge collection, heavy ion irradiation, transport by funnelling and diffusion.

We have studied the 1/f noise and total-dose response associated with the buried oxides (BOX) of fully depleted nMOS silicon-on-insulators (SOI) transistors. Silicon implantation in the BOX creates a higher density of oxygen vacancy-related defects that reduce the net oxide-trap charge, but increase the back-channel 1/f noise. The 1/f noise of MOSFETs fabricated on silicon-implanted SOI BOX shows little change after 1 Mrad(Si[O.sub.2]) irradiation. Silicon implantation also creates shallow electron traps in the BOX, leading to large bias instabilities. Whether these traps are filled or empty does not significantly affect the 1/f noise. A detailed study of the 1/f noise, temperature dependence of charge trapping, and radiation response of these SOI nMOSFET transistors shows that charge exchange with shallow electron traps in the BOX occurs mostly via tunneling. Low frequency noise in the double-gate (DG) mode of device operation is also investigated, and found to help mitigate the 1/f noise in fully depleted SOI MOSFETs. Index Terms--1/f noise, charge trapping, electron traps, oxygen vacancies, radiation effects, Si implantation, silicon-on-insulator (SOI), total ionizing dose.

The existing models for simulating spiral inductors fabricated in Silicon processes are presented. The new models presented contain only four to six elements and unlike the classic PI model, provide a broadband match to measured independence behavior in both differentially driven and single-ended circuit applications.

An analysis of gate misalignment effect on the threshold voltage of double-gate ultrathin fully depleted silicon-on-insulator in nMOS devices using a compact model considering the fringing electric field effect, biased at zero-bias V(sub DS) is reported. The two-dimensional simulation results show that a closed-form compact model considering the fringing electric field effect in the nongate overlap region is derived using the conformal mapping transformation approach to provide an accurate prediction of the threshold voltage behavior.

The investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption is reported. The study shows that with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current.

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs was developed to investigate the short-channel effects (SCEs). The study demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL).

The authors have developed a simple technique to quantify strain in bonded Si films and used it to compare the strain induced by two distinct wafer bonding methods. This method consists of patterning sets of moire gratings on silicon-on-insulator (SOI) substrates prior to bonding using a G-line stepper. After planarization, bonding, and etch-back, the same lithography step is performed on the flipped patterns. The resultant interference between upper and lower gratings produces moire fringes which is a measure of the strain. In the experiments, the sensitivity of the measurement is approximately 20 nm. This approach has been used to compare two methods of wafer bonding. The first method, a manual bonding technique, yielded strain of up to 100 nm/mm. The second method employed a commercial-grade bonder and resulted in film strains below 40 nm/mm. In the bonding schemes the authors have studied, they believe strain results mainly from induced wafer bow during bonding and stress contributions of deposited films. This scheme was developed to address wafer strain that arises from a direct-alignment double-gate MOSFET fabrication scheme (Meinhold, 1994). Index Terms--Moire, overlay, SOI, strain, stress, wafer bonding.

A procedure is proposed for obtaining identification (ID) numbers using polycrystalline silicon (poly-Si) thin-film transistors (TFT).

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices. Index Terms--Dose rate effects, radiation effects, silicon-on-insulator (SOI), single event effects, total dose effects.

On-resistance of vertical high-voltage DMOS transistors on SOI substrates are examined and reported.

A new concept involving single-layer strained SGOI MOFSETs is described and discussed.

The feasibility and operation of ultimately thin double-gate SOI MOSFETs is described and discussed.

A new approach involving substrate transfer for RF technologies is described and discussed.

A low-thermal-budget 3-D fabrication technique for mixed-signal applications is described and discussed.

Research is described involving the influence of process options on the analog and RF performances of SOI MOSFETs.

The silicon-on-insulator (SOI) film generation lifetime, the surface generation velocities at the upper and lower interfaces, and the effect of HF and iodine solution surface passivation and hydrogen annealing are determined with the help of pseudo-MOSFET structure. The structure characterizes the quality of silicon-on-insulator (SOI) films by measuring the generation lifetime.

The fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates is possible with the use of wafer bonding and H-induced layer transfer techniques. In Si-on-SiGe-on-insulator (SSOI) MOSFETs, the mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) is demonstrated.

It is shown that combined application of the SiGe source and the delta-doped p[superscript +] region on the source side in the body of a partially depleted (PD) silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) can greatly improve breakdown voltage, and high immunity to single transistor latch can be achieved.