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A detailed analysis of hot-carrier effects in deep submicron N and P channel SOI MOSFETs is presented, for gate lengths down to 0.1 mum. The two-stage time dependence of degradation is also investigated to provide reliable lifetime prediction methods that can be used under various hot-carrier stress conditions. Saturation levels are reliant on gate length, thus degradation time dependence needs to be carefully determined.

Hot carrier induced degradation is more complex in SOI devices than in bulk devices due to the thin Si-film effects. The reliability of SOI technologies are assessed, focusing on the hot-carrier effects (HCE) in deep submicron SIMOX and Unibond MOSFETs, hot carrier immunity of PD devices and analysis of the degradation N and P channel transistors. An investigation of the aging/recovery mechanisms for P-channel MOSFETs is also made.

Gate-induced transient effects in floating-body and nonideally body-tied partially-depleted MOSFETs have been studied. These phenomena are caused by time-dependence threshold voltage resulting from changes in body potential due to capacitive coupling to the gates. A physical compact model of the carrier generation and recombination has been formulated to simulate the behavior of the MOSFETs to front and back gate pulses.

Research was conducted to examine hot-carrier effects resulting from parasitic bipolar transistor action in deep submicron N-channel silicon-on-insulator metal oxide semiconductor field effect transistors for a range of temperature and gate length. Device aging was heavily influenced by variations in the leakage currents. Moreover, variations of threshold voltage shifts for a stress in off-state showed unusual behaviors.

There are close connections between the dose-induced threshold voltage shift of fully-depleted NMOS transistors and charge trapping in the buried oxide. Coupling between the front and back gate transistors is responsible for the significant shift in the fully-depleted SOI/NMOSFET which results from radiation-induced charge trapping in the buried oxide. Research indicates that the lateral parasitic transistor is more affected than the main active transistor by the buried oxide trapping.

A link between extracted threshold voltage and surface potential flat-band voltage in MOSFET compact modeling is described.