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A hybrid Analog to digital converter (ADC) is presented for long-wave infrared focal plane arrays. A two-stage quantization structure is applied in the folding integration process, which results in better chargehandling capacity and higher linearity compared with conventional designs while using fewer transistors at the pixel level. By employing a circular-adder-based counting structure with 3T dynamic memory cells, hardware consumption can be reduced. A pixel circuit of pitch 15μm has been designed using the 0.18mm Complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the pixel-level ADC is 0.214μW, and the charge-handling capacity is 1Ge-. Simulation results demonstrate a signal-to-noise ratio of 90dB and a nonlinearity of 0.11%.

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35µm CMOS technology. It occupies an area of 2.113i?0.81mm2. Measurement results show that the proposed channel can process up to 1MHz counting rate and provide a conversion gain of about 170mV/fC at a power dissipation of 330µW with a 3.3V power supply. Ac-coupled to a silicon PIN detector, it successfully detects s-rays.

A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

MEMS sensors often suffer from distance mismatch that the proof mass does not lie in the right middle of the two fixed plates. The mathematical formulae presented in this paper show that this asymmetry of MEMS sensor does not influence the linearity of accelerometer as a whole, and only introduces an offset. This is true not only for continuous time closed loop, but also for time divided architecture. For this kind of asymmetric sensors, Matlab/Simulink models are established. Simulation results confirm theoretical formulae. To testify this theory, a readout circuit of time divided architecture is designed and fabricated using 0.35µm HV CMOS process. Test results show that the nonlinearity of the tested accelerometer with the asymmetric sensor is within 0.3%.

Matlab/Simulink tool has been widely used in system modeling of circuit design. However, its application in the discrete-time circuit is not enough mature. Based on the continuous-time circuit simulation results by Matlab/Simulink, an s-z transformation method for the discrete-time accelerometer system design is proposed in this paper. In this method, a switched-capacitor readout circuit for closed-loop micromechanical capacitive accelerometer is designed and fabricated in a 0.35µm 15V CMOS process. The accelerometer operates under ±6.5V supply with a full scale of ±50g and the equivalent noise acceleration (ENA) is tested to be 54µg/√Hz at 60Hz.

Linearity which determines the system precision is one of the main performance parameters of accelerometers especially the wide-range ones. The design parameters of the interface circuit have a great effect on the linearity of the accelerometer system utilizing time-division force feedback (TDFF). In this paper, the nonlinearity resulting from time-division force feedback is discussed and the formulae reflecting the relationship between the system linearity and the design parameters are derived, which can help the designers to adjust timing parameters according to the linearity demand. The theory is verified by Matlab/Simulink numerical simulation. Based on the design formulae presented, a ±30g closed-loop TDFF capacitive micro-accelerometer is implemented in 0.35µm high-voltage CMOS process, which operates under ±6.5V supply and achieves linearity of 99.72%in the self-test mode.

A 14-bit Column-level ADC for Infrared Focal Plane Array (IRFPA) is proposed in this paper. Correlated switch structure is designed, which helps to cancel the offset generated by injected charge and then achieves accurate sampling and holding. Odd-even structure is realized to make longer converting time after sampling. Comparators with two-stage pre amplifiers use low power supply voltages, which ensures low power operation, as well as low noise. Conversion accuracy of the ADC circuit can reach 14-bit. The structure is used for a 640×512 array.

In order to design accelerometers, electromechanical hybrid simulation with the sensor and interface circuit together is required. In this paper a Verilog-A model for the accelerometer sensor is presented, and based on the Verilog-A model presented, an open-loop capacitive accelerometer with a full-scale range of ±2g is presented. The Verilog-A model, characterizing the properties of the sensor, is compared to be right with the Matlab model published before. The accelerometer is tested to achieve the equivalent noise acceleration (ENA) about 7.7µg/√Hz.

A programmable readout circuit for capacitive accelerometer is presented. The inequality of initial capacitance of sensor's differential capacitor pair is properly compensated. The gain of CSA and the cut-off frequency of LPF are both adjustable. To lower noises, amplifier of CSA is carefully designed. Its equivalent input noise density is 12.7nV/ √ Hz. A rail-to-rail buffer is chosen to enlarge the measurement range. EEPROM instead of pads is exploited, which saves about 33 percent of the layout area.

A 12-bit 20MS/s low power pipelined analog-digital converter (ADC) is presented. A front-end sampling network is proposed to eliminate the need of SHA. Passive capacitor error-averaging technique (PCEA) and Opamp sharing scheme are employed to achieve high resolutions and low power and area. The drawback of conventional Opamp sharing technique is resolved with polarity inverting scheme by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um mix-signal CMOS technology, the ADC dissipates 71mw from a 5V supply, and achieves a peak SNDR of 69.8dB with a 0.5MHz full-scale sine input at 20MS/s.

A 12-bit 20 MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5 ?m CMOS technology, the ADC dissipates 65 mw from a 5 V supply, and achieves a peak SNDR of 70.1 dB with a 1 MHz full-scale sine input at 20 MS/s.

A 10-bit 80 MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5 um technology, the ADC dissipates 210 mw of power from a 5 v supply, and achieves a peak SNDR of 56 dB at 80 Ms/s.

A novel data-sparsification method for multi-channel radiation detector readout ASICs is proposed. Based on the self-triggering approach, the scheme operates as follows: when one channel is being read out, the trigger signal from other channels is delayed one or more clock cycles and then processed. In this way, the dead time, during which the circuit fails to respond to the input, is reduced and so is the error rate. A 16-channel readout ASIC has been designed in a 0.5um DPTM CMOS technology. The feasibility of this novel sparse readout method is verified by simulation. Theory analysis and calculation show that the error rate is approximately 2.5%, and is reduced by about 37% compared with the conventional scanning scheme, assuming a 16-channel system with an event rate of 100 K/s per channel.

This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.

A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.

In this paper, instead of the traditional experience-based trial-and-error ESD design approach, a novel ESD protection design methodology is proposed, which resolves the costly and time-consuming problems of high-performance ESD protection development in deep-submicron CMOS technology. And this novel design method is conducted and verified in a 0.5-mum CMOS technology to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be great than 4.5kV. To effectively improve latchup free capability, latchup prevention design is also discussed

A novel method to adjust gain in CMOS infrared (IR) readout integrated circuit (ROIC) which is suitable for the application of small pixel size has been proposed in this paper. Current mirror is inserted in the pixel to adjust gain. Two comparators have been added outside of the pixel and provide the decision to select different gains. Adjustable gain makes the design of following signal process circuit easier and allows long integration time to increase SNR. With this method of automatic gain adjust, ROIC can deal with the current that varies from 40nA to 300nA, with the integration capacitor of 2pF and the integration time of 40/spl mu/s. An experimental 4/spl times/4-pixel ROIC has been designed and it will be fabricated with 0.5/spl mu/m DPDM n-well CMOS process.

A design model is proposed to exactly simulate operating principles of gate-coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor C/sub n/ and coupling resistor R/sub n/ can be calculated to improve the efficiency of GCNMOS ESD protection circuit.

A novel dual-window readout structure is presented in this paper. The ROIC with this structure can work in two modes: normal mode and windowing mode. The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode. Furthermore, the positions and sizes of these sub-arrays can be specified by users. This feature allows image system to trace two fast moving objects without using two ROICs. An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 0.5/spl mu/m DPTM n-well CMOS process.

Design of CMOS high-speed self-regulating voltage-controlled oscillator (HSSR VCO) using negative skewed delay scheme is presented in this paper. With a SMIC standard logic 0.18-/spl mu/ 1.8V CMOS process, the simulation results show that the HSSR VCO can work at 2.2 GHz with good linearity in frequency-voltage space as over an acceptable tuning range as well as a built-in compensation for the delay variation caused by supply fluctuation.

An improved CMOS snapshot readout structure called RRSCA (Reset Row-by-row Snapshot Charge Amplifier) for infrared focal plane array (IRFPA) is presented in this paper. The pixel circuits in RRSCA readout structure are reset row by row after each row's pixel signals were readout to the column stage in parallel and pixel circuit is very simple including only three MOSFETs. Thus, the RRSCA readout structure is very suitable for the readout circuit design with large-format and very small pixel size such as 30*30 or 25*25 mm2. An experimental 130 t 130 RRSCA chip has been fabricated with 1.2-mm Double-Poly Double-Metal (DPDM) n-well CMOS technology. Both simulation results and experimental results are presented.

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.