A cost-efficient 12-Bit 20Msamples/s pipelined ADC

A 12-bit 20 MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5 ?m CMOS technology, the ADC dissipates 65 mw from a 5 V supply, and achieves a peak SNDR of 70.1 dB with a 1 MHz full-scale sine input at 20 MS/s.