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The EU crystalline silicon (c-Si) PV manufacturing industry has faced strong foreign competition in the last decade. To strive in this competitive environment and differentiate itself from the competition, the EU c-Si PV manufacturing industry needs to (1) focus on highly performing c-Si PV technologies, (2) include sustainability by design, and (3) develop differentiated PV module designs for a broad range of PV applications to tap into rapidly growing existing and new markets. This is precisely the aim of the 3.5 years long H2020 funded HighLite project, which started in October 2019 under the work program LC-SC3-RES-15-2019: Increase the competitiveness of the EU PV manufacturing industry. To achieve this goal, the HighLite project focuses on bringing two advanced PV module designs and the related manufacturing solutions to higher technology readiness levels (TRL). The first module design aims to combine the benefits of n-type silicon heterojunction (SHJ) cells (high efficiency and bifaciality potential, improved sustainability, rapidly growing supply chain in the EU) with the ones of shingle assembly (higher packing density, improved modularity, and excellent aesthetics). The second module design is based on the assembly of low-cost industrial interdigitated back-contact (IBC) cells cut in half or smaller, which is interesting to improve module efficiencies and increase modularity (key for application in buildings, vehicles, etc.). This contribution provides an overview of the key results achieved so far by the HighLite project partners and discusses their relevance to help raise the EU PV industries' competitiveness. We report on promising high-efficiency industrial cell results (24.1% SHJ cell with a shingle layout and 23.9% IBC cell with passivated contacts), novel approaches for high-throughput laser cutting and edge re-passivation, module designs for BAPV, BIPV, and VIPV applications passing extended testing, and first 1-year outdoor monitoring results compared with benchmark products. This project has received funding from the European Union's Horizon 2020 Programme for research, technological development, and demonstration under Grant Agreement no. 857793.

Contactless plating with electroless solutions can provide self-aligned high-efficiency contacts with very low silver content, using simple and inexpensive equipment. With prior surface activation, it can even be used to metallize both sides of bifacial silicon solar cells simultaneously. However, we observe in such a coplating process with nickel, where surface activation is achieved by immersion plating and thickening by electroless plating, that V oc and fill factor can sometimes significantly decrease with immersion-plating time. To understand the reason for this electrical degradation, we studied the impact of immersion plating on the microstructure of the plated silicon surface. The evolution of the Si-Ni interface was studied by scanning and transmission electron microscopies, energy-dispersive X-ray analysis, secondary ion mass spectrometry, and scanning spreading resistance microscopy. Our attention focused on metal in-diffusion, silicon roughening and etching as the origin for increased recombination. Etching was found to have a significant impact on V oc. The thickness of N + Si etched during Ni deposition can in fact suppress in a few locations most of the field-effect passivation underneath the contacts. This means that a thicker surface field with doping beyond 1019/cm3 must be foreseen under the plated areas, or that the amount of Si lost in the reaction must be reduced. Our observations also confirm that immersion plating can hinder silicide formation and allow Ni in-diffusion, which may be a concern for reliability.

Perovskite/crystalline-silicon (c-Si) tandem solar cells offer a viable roadmap for reaching power conversion efficiencies beyond 30%. In this configuration, however, the silicon cell now mainly receives an infrared rich illumination spectrum where the absorption coefficient of silicon is poor. To boost the light absorption in this wavelength interval, transmitted through the top cell, a solution is to introduce a dedicated nanoscale texture on the front side of the silicon bottom cell and tweaking the optical elements in its design. These optical elements are manifold, with tunable geometrical dimensions, layer thicknesses, and refractive indices. For optically optimizing nanostructured silicon solar cells, electromagnetic wave solving methods, such as the rigorous coupled-wave analysis (RCWA), are normally used but they become computationally infeasible when several design variables are involved in an optimization problem. In this work, a natural selection algorithm, known as the genetic algorithm, is coupled with RCWA for extracting the optimal values of various design parameters in four-terminal perovskite/c-Si tandem devices in parallel. Both two-side-contacted and interdigitated back-contacted silicon heterojunction cell structures, featuring an inverse nanopyramid grating texture on the front, are optimized for five interdependent variables using a genetic algorithm for the bottom cell application and benchmarked against their random pyramid textured analogs. Our study shows that an optimized inverse nanopyramid grating texture can outperform the standard random pyramid texture when considering incidence angle variations. More importantly, the study illustrates how a genetic algorithm can support modeling complex solar cell structures with numerous degrees of freedom.

Carefully tailored periodic nanostructures on the light wavelength scale, such as diffraction gratings, benefit from wave optics for efficiently trapping the weakly absorbing infrared photons in crystalline-silicon (c-Si) absorbers. In contrast with the conventional random pyramid texture, diffraction gratings can be designed to target specific wavelength ranges by the selection of the grating pitch. Absorption enhancement at infrared wavelengths in a silicon solar cell is especially desired when it operates below a perovskite top cell in a tandem device. In this article, inverse nanopyramid gratings of 800 nm pitch are proposed as an alternative front-surface texture to random pyramids in silicon heterojunction devices with interdigitated back contacts that are to be used as bottom cells in four-terminal perovskite/c-Si tandem devices. By doing so, we report a short-circuit current density gain of 0.53 mA/cm 2 with respect to the random pyramid texturing for the bottom c-Si cell. The rationale to substitute random pyramids by inverse nanopyramid gratings is, however, not justified in single-junction operation despite achieving the power conversion efficiency of 22.3% since the degraded optical performance at shorter wavelengths offsets the absorption enhancement at longer wavelengths, resulting in similar levels of short-circuit current densities for both texture types. ispartof: Ieee Journal Of Photovoltaics vol:10 issue:3 pages:740-748 status: Published online

Metal oxides are interesting materials for use as carrier-selective contacts for the fabrication of doping-free silicon solar cells. In particular, MoOx and TiOx have been successfully used as hole and electron selective contacts in silicon solar cells, respectively. However, it is of paramount importance that good thermal stability is achieved in such contacts. In our work, we combined i-a-Si:H/MoOx based hole contacts with electron contacts featuring i-a-Si:H/TiOx/low work function metal (ATOM) to fabricate doping-free cells, termed MoIyATOM cells. We found that the thermal stability of the ATOM contact was improved when the i-a-Si:H was annealed (300 degrees C for 20 min in N-2) before depositing TiOx (Le. pre-TiOx annealing), which reduces the hydrogen content in i-a-Si:H by about 27 Vorei, and thereby the H-related degradation of the ATOM contact characteristics. Moreover, it was found that reducing the thickness of the low-work function metal on top of the TiOx enhanced the thermal stability of the ATOM contact. With these adaptations, the MoIyATOM cell efficiency was improved by 3.5 %(abs), with the highest efficiency of 17.6%. Moreover, the cells show improved thermal stability after the above-mentioned pre-TiOx annealing, which is confirmed by annealing tests at cell level as well as damp-heat tests at module level. The insights of this study could be used to tailor other metal-oxide based electron or hole contacts. The authors thank Praveen Dara and Johan Meersschaut for ERD measurement. Moreover, the authors gratefully acknowledge the financial support of imec's industrial affiliation program for Si-PV. The work in this paper was partially funded by the Kuwait Foundation for the Advancement of Sciences under project number CN18-15EE-01. Imec is a partner in EnergyVille (www.energyville.be), a collaboration between the Flemish research partners KU Leuven, VITO, imec, and UHasselt in the field of sustainable energy and intelligent energy systems. Cho, JY (reprint author), Katholieke Univ Leuven, ESAT Dept, Kasteelpk Arenberg 10, B-3001 Leuven, Belgium; Umicore, Watertorenstr 33, B-2250 Olen, Belgium. Radhakrishnan, HS (reprint author), IMEC, Kapeldreef 75, B-3001 Leuven, Belgium. jinyoun.cho@eu.umicore.be

In early 2017, the world record efficiency for single-junction crystalline silicon (c-Si) solar cells was achieved by merging amorphous silicon (a-Si:H)/c-Si heterojunction technology and back-contact architecture. However, to fabricate such silicon heterojunction interdigitated back-contact (SHJ-IBC) solar cells, complex a-Si:H patterning steps are required to form the interdigitated a-Si:H strips at the back side of the devices. This fabrication complexity raises concerns about the commercial potential of such devices. In this work, a novel process scheme for a-Si:H patterning using damage-free laser ablation is presented, leading to a fast, simple and photolithography-free emitter patterning approach for SHJ-IBC solar cells. To prevent laser-induced damage to the a-Si:H/c-Si heterocontact, an a-Si:H laser-absorbing layer and a dielectric mask are deposited on top of the a-Si:H/c-Si. Laser ablation only removes the top a-Si:H layer, reducing laser damage to the bottom a-Si:H/c-Si heterocontact under the dielectric mask. This dielectric mask is a distributed Bragg reflector (DBR), resulting in a high reflectance of 80% at the laser wavelength and thus providing additional protection to the a-Si:H/c-Si heterocontact. Using such simple a-Si:H patterning method, a proof-of concept 4-cm(2) SHJ-IBC solar cell with an efficiency of up to 22.5% is achieved. The authors gratefully acknowledge the financial support of IMEC's Industrial Affiliation Program for Si-PV. This project has also received funding from the European Union's Horizon 2020 Research and Innovation Programme under grant agreement no. 727523 (NextBase).

A fully dry and hydrofluoric-free low-temperature process has been developed to passivate n-type crystalline silicon (c-Si) surfaces. Particularly, the use of a hydrogen (H2) plasma treatment followed by in situ intrinsic hydrogenated amorphous silicon (a-Si:H) deposition has been investigated. The impact of H2 gas flow rate and H2 plasma processing time on the a-Si:H/c-Si interface passivation quality is studied. Optimal H2 plasma processing conditions result in the best effective minority carrier lifetime of up to 2.5 ms at an injection level of 1 × 1015 cm−3, equivalent to the best effective surface recombination velocity of 4 cm/s. The reasons that enable such superior passivation quality are discussed in this paper based on the characterization of the a-Si:H/c-Si interface and c-Si substrate using transmission electron microscopy, high angle annular dark field scanning transmission electron microscopy, and deep-level transient spectroscopy.

Previously, IMEC proposed the i(2)-module concept which allows to process silicon heterojunction interdigitated back-contact (SHJ-IBC) cells on thin ( < 50 mu m) Si wafers at module level. This concept includes the bonding of the thin wafer early on to the module cover glass, which delivers mechanical support to the wafer and thus significantly improves the production yield. In this work, we test silicone and ethylene vinyl acetate bonding agents and prove them to be resistant to all rear side processes, including wet and plasma processes. Moreover, a lift-off process using a sacrificial SiOx layer has been developed for emitter patterning to replace conventional lithography. The optimized process steps are demonstrated by the fabrication of SHJ-IBC cells on 6-inch 190 mu m-thick wafers. Efficiencies up to 22.6% have been achieved on reference freestanding wafers. Excellent V-oc of 734 my and J(sc) of 40.8 mA/cm(2) lead to an efficiency of 21.7% on silicone-bonded cells, where the high V-oc indicates the process compatibility of the bonding agent. The developments that enabled such achievements and the key factors that limit the device performance are discussed in this paper. The authors would like to thank the financial support of imec's industrial affiliation program for Si-PV. This work was also partially funded by Kuwait Foundation for the Advancement of Sciences under project code: P115-15EE-01. The research has received funding from the European Union's Seventh Programme for research, technological development and demonstration under grant agreements no. 609788 (Cheetah), and also funding from the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No 657270. The authors gratefully acknowledge Joachim John for the spectral response measurements and Yiming Yang for the SEM measurements.

Utilisation of expensive silicon (Si) material in crystalline Si modules has come down to 4 g Si per watt-peak in 2018, mainly as a result of reduction in wafer thickness and kerf losses as well as increase in module efficiencies. With continued progress in conventional multi-wire sawing of ingots, wafers as thin as 100 mu m could eventually be produced. Beyond this, kerfless lift-off technologies are being investigated which enable wafer thicknesses well below 100 mu m with negligible Si kerf waste. Such thin Si wafers and foils would be much lighter in weight than today's standard 165-180 mu m-thick wafers and would exhibit considerable flexibility and fragility. This necessitates a rethink about how to handle and process thin Si into solar devices in a manufacturing line with high mechanical yield and high throughput. This paper gives a broad overview of the different approaches for fabricating solar cells on thin Si foils. In particular, three routes are discussed in detail, namely (1) freestanding processing of thin Si, (2) processing of thin Si supported mechanically on a conductive low-cost Si substrate ("wafer-equivalent" approach) and (3) processing of thin Si bonded to a transparent glass superstrate. In each case, the main challenges are explained and the recent progress in addressing them are summarised. Kerfless 50 mu m-thick epitaxial Si foils lifted-off using porous Si and thinned-down Si wafers (below 70 mu m) are used as model substrates for this work. The authors gratefully acknowledge the efforts of several people who were involved in this work over the last few years, namely Jonathan Govaerts, Stefano Granata, Menglei Xu, Ergi Donercark, Ivan Sharlandshiev, Shashi Kiran Jonnak, Shruti Jambaldinni, Robert Roozeman, Jarkko Heildcinen, Thomas Kaden, Zuzana Kovacova, Erich Neubauer, Michael Grimm and Kaori Nagaoka. The authors also acknowledge the funding received for this work from the European Commission for the H2020 project CABRISS under grant agreement No. 641972. Imec is a partner in EnergyVille (www.energyville.be), a collaboration between the Flemish research partners KU Leuven, VITO, imec, and UHasselt in the field of sustainable energy and intelligent energy systems. Radhakrishnan, HS (reprint author), Imec Vzw Partner EnergyVille, Kapeldreef 75, B-3001 Leuven, Belgium. sivarama@imec.be

A possible research path to increase the photo-generated current in silicon heterojunction (SHJ) solar cells is to replace doped layers on the front-side of the cell, which result in significant parasitic light absorption losses. MoOx is one candidate to replace the p-doped a-Si:H layer in such devices, although it is claimed to be relatively unstable to thermal treatments. We found that a MoOx film with a thickness of 6 nm is sufficient to achieve a JSC of 36 mA/cm2, which is 0.5 mA/cm2 on average higher than that of our classical SHJ reference cell. We also established a contact sintering condition for printed Ag at 160 °C after MoOx deposition, without degrading the cell performance. The champion MoOx-contacted cell yielded VOC of 724 mV and FF of 74.1%, resulting in an efficiency of 19.3%. From a detailed analysis of the interfaces of the hole contact, an interfacial a-SiOx of 1.6–2 nm was observed between a-Si:H and MoOx irrespective of the MoOx thickness (6–10 nm) before and after contact sinter annealing at 160 °C. We postulate that this a-SiOx layer acts as an interfacial dipole layer and also increases the contact resistivity at this contact. The intrinsic stability of the optimised MoOx-contacted cell is studied using a one-cell mini-module under standard damp-heat testing (85 °C/85% humidity/1000 h). More than 97 %rel of the original efficiency is maintained after 1010 h of testing, which is comparable to the behavior observed in a classical SHJ reference one-cell mini-module that was similarly tested.

We present a novel process sequence to simplify the rear-side patterning of the silicon heterojunction interdigitated back contact (HJ IBC) cells. In this approach, interdigitated strips of a-Si:H (i/p(+)) hole contact and a-Si:H (i/n(+)) electron contact are achieved by partially etching a blanket a-Si:H (i/p(+)) stack through an SiOx hard mask to remove only the p(+) a-Si:H layer and replace it with an n(+) a-Si:H layer, thereby switching from a hole contact to an electron contact in situ, without having to remove the entire passivation. This eliminates the ex situ wet clean after dry etching and also prevents re-exposure of the crystalline silicon surface during rear-side processing. Using a well-controlled process, high-quality passivation is maintained throughout the rear-side process sequence leading to high open-circuit voltages (V-OC). A slightly higher contact resistance at the electron contact leads to a slightly higher fill factor (FF) loss due to series resistance for cells from the partial etch route, but the FF loss due to J(02)-type recombination is lower, compared with reference cells. As a result, the best cell from the partial etch route has an efficiency of 22.9% and a V-OC of 729 mV, nearly identical to the best reference cell, demonstrating that the developed partial etch process can be successfully implemented to achieve cell performance comparable with reference, but with a simpler, cheaper, and faster process sequence. European Commission's Horizon 2020Framework Programme, Grant/Award Num-ber: 727523; IIAP‐SiPV; Kuwait Foundationfor the Advancement of Sciences, Grant/Award Number: P115‐15EE‐01

We have studied the effect of different cleanings at device level for nPERT (passivated Emitter, Rear Totally diffused) cells with a rear epitaxial emitter. Cleanings based on sulfuric acid and peroxide mixtures (SPM), which are effective but also expensive, were used as reference. We found that simplified cleanings such as those based on sulfuric acid and ozone mixtures (SOM), and those based on water and ozone (IPV), are giving similar results at device level as the expensive SPM cleaning, leading to similar J0e, J0, FSF, and lifetime values. The implied VOC values of corresponding test devices fabricated using the simplified cleanings are at the same high level as the test devices using more expensive SPM cleanings. Actual nPERT devices with moderately doped epitaxially-grown emitters with a constant doping profile (box profile) showed average efficiencies above 22.0% for both SOM and IPV cleanings. Very high VOC values of up to 695 mV and implied VOC values of up to 730 mV were shown for cells with a flat rear surface. Finally, the best nPERT cells with rear epitaxial emitter and SOM cleaning showed efficiencies up to 22.5%, as externally confirmed by ISE CalLab.

In this work, we have investigated the impact of interstitial Fe contamination on the effective minority carrier lifetime of n-type Cz silicon bulk material for high efficiency solar cells. The study covers a Fe concentration in the silicon bulk from 3.5 × 1012 cm-3 to 2.7 × 1014cm-3. We have added 5 different concentrations (30, 100, 300, 1000 and 3000 ppb) of Fe intentionally to a wet chemical process tank and measured the transfer to the silicon wafer surface mimicking a possible contamination during wet chemical processing. In order to fabricate carrier lifetime test vehicles, the silicon wafer is then passivated with thermal silicon oxide from both sides. The surface contamination is driven into the bulk by mimicking a high temperature process during solar cell manufacturing. Effective minority carrier lifetime is measured at injection levels from 1 × 1013 cm-3 to 3 × 1015cm-3. We have fitted the theoretical curve for interstitial Fe derived from the SRH theory to the measured values and extracted the Fe contamination concentration. This value is comparable to the calculated value extracted from the surface contamination measurement. For low level injection (LLI), we extracted the capture cross section for interstitial Fe to be 6.45 × 10-17 cm/s ± 2.23 × 10-17 cm/s. The measured Fe contamination levels are used for the conversion efficiency fitting of a n-type bifacial silicon solar cell using QUOKKA simulations. The simulations show that very low Fe contamination concentrations of [Fe]bulk = 3.5 × 1012 cm-3 ([Fe]surf = 6 × 1010cm-2) already degrade the solar cell efficiency by 10% relative.

Copyright © 2018 John Wiley & Sons, Ltd. In this work, the ATOM (intrinsic a-Si:H/TiO x /low work function metal) structure is investigated to realize high-performance passivating electron-selective contacts for crystalline silicon solar cells. The absence of a highly doped Si region in this contact structure is meant to reduce the optoelectrical losses. We show that a low contact resistivity (ρ c ) can be obtained by the combined effect of a low work function metal, such as calcium (Φ 2.9 eV), and Fermi-level depinning in the metal-insulator-semiconductor contact structure (where in our case TiO x acts as the insulator on the intrinsic a-Si:H passivating layer). TiO x grown by ALD is effective to achieve not only a low ρ c but also good passivation properties. As an electron contact in silicon heterojunction solar cells, inserting interfacial TiO x at the i-a-Si:H/Ca interface significantly enhances the solar cell conversion efficiency. Consequently, the champion solar cell with the ATOM contact achieves a V OC of 711 mV, FF of 72.9%, J SC of 35.1 mA/cm 2 , and an efficiency of 18.2%. The achievement of a high V OC and reasonable FF without the need for a highly doped Si layer serves as a valuable proof of concept for future developments on passivating electron-selective contacts using this structure. ispartof: PROGRESS IN PHOTOVOLTAICS vol:26 issue:10 pages:835-845 status: published

This paper compares the electrically active damage in dry-etched n-type float-zone silicon, using NF3/Ar or H2-plasma exposure and assessed by deep-level transient spectroscopy (DLTS) and recombination lifetime analysis. It is shown that the NF3/Ar-plasma damage consists of at least four different types of electron traps in the upper half of the band gap, which can be associated with vacancy- and vacancy-impurity-related complexes. In the case of H2-plasma damage, it is believed that the accumulation of point defects results in a gradual disordering of the near-surface layer. These defect levels also act as recombination centers, judged by the fact that they degrade the minority carrier lifetime. It is finally shown that lifetime measurements are more sensitive to the etching-induced damage than DLTS.This paper compares the electrically active damage in dry-etched n-type float-zone silicon, using NF3/Ar or H2-plasma exposure and assessed by deep-level transient spectroscopy (DLTS) and recombination lifetime analysis. It is shown that the NF3/Ar-plasma damage consists of at least four different types of electron traps in the upper half of the band gap, which can be associated with vacancy- and vacancy-impurity-related complexes. In the case of H2-plasma damage, it is believed that the accumulation of point defects results in a gradual disordering of the near-surface layer. These defect levels also act as recombination centers, judged by the fact that they degrade the minority carrier lifetime. It is finally shown that lifetime measurements are more sensitive to the etching-induced damage than DLTS.

In the frame of the development of thin crystalline silicon solar cell technologies, surface nanopatterning of silicon is gaining importance. Its impact on the material quality is, however, not yet fully controlled.We investigate here the influence of surface nanotexturing on the series resistance of a contacting scheme relevant for thin-film crystalline silicon heterojunction solar cells. Two dimensional periodic nanotextures are fabricated using a combination of nanoimprint lithography and either dry or wet etching, while random pyramid texturing is used for benchmarking. We compare these texturing techniques in terms of their effect on the series resistance of a solar cell through a study of the sheet resistance (Rsh ) and contact resistance (Rc) of its front layers, i.e., a sputtered transparent conductive oxide and evaporated metal contacts. We have found by four-point probe and the transfer length methods that dry-etched nanopatterns render the highest Rsh and Rc values. Wet-etched nanopatterns, on the other hand, have less impact on Rc and render Rsh similar to that obtained from the nontextured case., Authors' post-print version in Abdo et al., IEEE Journal of Photovoltaics, July 2015

We recently proposed a novel test structure for the extraction of recombination characteristics of metal-contacted areas on silicon wafers using quasi-steady state photoconductance measurements. In this test structure, photoconductance measurements are performed on several wafer areas with different contact fractions. Each area consists of a lattice of point contacts on an otherwise passivated wafer. The requirement of constant excess carrier densities throughout the quasi-neutral wafer bulk is absolutely essential for the simple extraction of figures of merit for contact recombination. In this study, we first discuss the requirements for constant injection levels during photoconductance measurements, without reference to a particular geometry. Then, we use a simple 1-D model to elucidate how injection levels vary in the test structure plane. We use the model to investigate limiting cases for which the requirement of constant injection levels is satisfied. In addition, we investigate the breakdown of the assumption of constant injection levels. We discuss the influence of nonconstant excess carrier concentrations on photoconductance measurements in the context of our test structure. Finally, we validate our model by comparison with experiments. Our analysis is particularly useful in the context of understanding the design rules for contact size and pitch in our test structure.

Argon (Ar) and oxygen (O2) plasmas are performed on silicone adhesives to eliminate the negative influence of silicone on amorphous silicon (a-Si:H) surface passivation of wafers bonded to glass. Both the Ar and O2 plasmas lead to oxidation of the silicone surface, consisting in an increase of oxygen/carbon ratio, of degree of crosslinking, and of material density. The oxidized silicone is more resilient than pristine and does not interact with the a-Si:H passivation process, allowing for state-of-the-art surface passivation of wafers bonded to glass. Similarities between the modifications induced by the Ar and O2 plasmas on the silicone indicate the secondary role of the O2 radicals in the oxidation process. Moreover, amorphous/crystalline heterojunction interdigitated back contact solar cells (a-Si:H/c-Si HJ i-BC) are fabricated on freestanding and bonded wafers treated with Ar plasma. The devices show comparable open-circuit voltages of up to 675 mV, confirming at device level the efficacy of the treatment.

Two important aspects for the success of the porous silicon-based layer transfer method in producing kerfless thin ( 15 cm −3 which corresponds to a minimum minority carrier diffusion length of ~670 µm (> 16 times the silicon thickness). With such high quality epitaxial foils combined with high detachment yield, very high efficiency solar devices on thin silicon substrates would be a reality in the near future.

In the future solar devices will be manufactured onto thin mono-crystalline silicon wafers (foils) potentially bonded to substrate carriers. In this study, the influence of the substrate carrier potential (grounded or floating) on the amorphous silicon a-Si:H surface passivation of the bonded foil is discussed for the cases of conductive and insulating substrate carriers. A conductive carrier leads to an increase in deposition rate and ion bombardment energy, which is detrimental for sample lifetime. An insulating carrier, e.g., a glass substrate, inverts the trend and improves the a-Si:H surface passivation.

We have investigated fine grained polycrystalline silicon thin films grown by direct chemical vapor deposition on oxidized silicon substrates. More specifically, we analyze the influence of the doping type on the properties of this model polycrystalline silicon material. This includes an investigation of defect passivation and benchmarking of minority carrier properties. In our investigation, we use a variety of characterization techniques to probe the properties of the investigated polycrystalline silicon thin films, including Fourier Transform Photoelectron Spectroscopy, Electron Spin Resonance, Conductivity Activation, and Suns-Voc measurements. Amphoteric silicon dangling bond defects are identified as the most prominent defect type present in these layers. They are the primary recombination center in the relatively lowly doped polysilicon thin films at the heart of the current investigation. In contrast with the case of solar cells based on Czochralski silicon or multicrystalline silicon wafers, we conclude that no benefit is found to be associated with the use of n-type dopants over p-type dopants in the active absorber of the investigated polycrystalline silicon thin-film solar cells.

The August 2014 Special Issue of Solar Energy Materials & Solar Cells is dedicated to the 2nd workshop on Silicon Materials held in Rome, Italy, during October 7-8, 2013. During the workshop several discussions were held on the main question, 'Which are the challenges for Si material research'. The discussion focused on the results of the online survey and on the outstanding contributions of experts and presenting authors. One of the most debated points was how to select technologies that would enable cost reduction. A few possible scenarios to reduce costs were proposed. No consensus was reached with respect to the best scenario enabling the strongest cost reduction. During the workshop 27 contributions in addition to four personal statements from invited experts were given by industry, research institutes and universities.

The passivation characteristics of thermally grown silicon dioxide (SiO 2 ) and hydrogenated amorphous silicon (a-Si:H) layers are investigated, using a combination of photoluminescence and capacitance-voltage analysis techniques. Key findings are the significant passivation degradation of SiO 2 and a-Si:H layers induced by metallization through electron beam evaporation. The degradation correlates with an increase in silicon dangling bond defect density at the interface with silicon (for both SiO 2 and a-Si:H) or in the passivation layer (a-Si:H). Performing the metallization by thermal evaporation is an effective method to avoid such process-induced damage, as is forming gas annealing at 450°C, which effectively recovers the interface characteristics of SiO 2 layers. Deposition of amorphous silicon on a thermal SiO 2 layer induces bulk and interface defects in the SiO 2 layer-but in this case, a 450°C forming gas anneal is not possible due to the thermal budget limitations of a-Si:H, thereby posing problems for solar cell structures which rely on a combination of PECVD a-Si:H and thermal SiO 2 passivation layers.

We propose a back reflecting scheme in order to enhance the maximum achievable current in one micron thick crystalline silicon solar cells. We perform 3D numerical investigations of the scattering properties of metallic nanostructures located at the back side and optimize them for enhancing absorption in the silicon layer. We validate our numerical results experimentally and also compare the absorption enhancement in the solar cell structure, both with quasi-periodic and random metallic nanostructures. We have looked at the interplay between the metallic nanostructures and an integrated back reflector. We show that the combination of metallic nanoparticles and a metallic reflector results in significant parasitic absorption. We compared this to another implementation based on titanium dioxide nanoparticles, which act as a Lambertian reflector of light. Our simulation and experimental results show that this proposed configuration results in reduced absorption losses and in broadband enhancement of absorption for ultra-thin solar cells, paving the way to an optimal back reflector for thin film photovoltaics.

We report on the fabrication, integration, and simulation, both optical and optoelectrical, of two-dimensional photonic nanostructures for advanced light trapping in thin crystalline silicon (c-Si) solar cells. The photonic nanostructures are fabricated by the combination of various lithography (nanoimprint, laser interference, and hole mask colloidal) and etching (dry plasma and wet chemical) techniques. The nanopatterning possibilities thus range from periodic to random corrugations and from inverted nanopyramids to high aspect ratio profiles. Optically, the nanopatterning results in better performance than the standard pyramid texturing, showing a more robust behavior with respect to light incidence angle. Electrically, wet etching results in higher minority carrier lifetimes compared to dry etching. From the integration of the photonic nanostructures into a micron-thin c-Si solar cell certain factors limiting the efficiencies are identified. More precisely: (a) the parasitic absorption is limiting the short circuit current, (b) the conformality of thin-film coatings on the nanopatterned surface is limiting the fill factor, and (c) the material damage from dry etching is limiting the open circuit voltage. From optical simulations, the optimal pattern parameters are identified. From optoelectrical simulations, cell design considerations are discussed, suggesting to position the junction on the opposite side of the nanopattern.

Future wafer-based silicon solar cells will be fabricated on thin (

The hydrogen plasma passivation of thin film polycrystalline silicon (pc-Si) was investigated in conjunction with plasma texturing process to make efficient heterojunction solar cells. The pc-Si layers were first treated using direct and remote hydrogen plasma technologies. The heterojunction solar cells were then fabricated by subsequent deposition of i/n+ a-Si:H. Hydrogenation at high temperature (610 °C) results in enhanced dissolution and diffusion of hydrogen in pc-Si by a factor of about 3 and 4, respectively, in comparison with those at low temperature (420 °C). The hydrogen atoms in the pc-Si layer mainly bond to the silicon dangling bonds and form complexes with dopant atoms. In addition, platelets defects are generated by the hydrogen plasma in the sub-surface region of pc-Si hydrogenated at 420 °C and cause higher saturation current in the space charge region whilst they form in the region deeper than 1 μm at 610 °C. Removal of the platelets using SF6/N2O plasma post-texturing after low-temperature hydrogenation not only enhances the short circuit current but also improves the open circuit voltage and the fill factor simultaneously. Combining plasma pre-texturing with high-temperature hydrogenation, the best 2 µm-thick pc-Si heterojunction solar cell reaches an efficiency of 8.54%.

A porous silicon-based layer transfer process to produce thin (30-50 μm) kerfless epitaxial foils (epifoils) is a promising approach toward high-efficiency solar cells. For high efficiencies, the epifoil must have high minority carrier lifetimes. The epifoil quality depends on the properties of the porous layer since it is the template for epitaxy. It is shown that by reducing the thickness of this layer and/or its porosity in the near-surface region, the near-surface void size is reduced to

Thin-film polycrystalline silicon (pc-Si) solar cell technology tries to combine the cost benefit of thin-film technology and the quality potential of crystalline Si technology. For this type of solar cells the challenge is to fabricate high quality coarse-grained (grain size of 1–100 µm) layers on non-silicon substrates in combination with superb light management. One possible material fabrication approach is metal induced crystallization (MIC). Many metals lower the crystallization temperature of a-Si but for photovoltaic (PV) solar cell applications aluminum seems to be the most interesting. Approximately a decade after the suggestion of Nast et al. to use aluminum induced layer exchange for thin-film solar cells, this paper will discuss the aluminum induced crystallization process itself as well as the implementation into workable solar cells. The record aluminum induced crystallization (AIC) solar cell today features an energy conversion efficiency of 8.5%, too low to be competitive with other PV technologies. The main problems and limitations as encountered today will be described. We believe that an energy conversion efficiency of 8.5% is not the limit of AIC solar cells. Different possible solutions to improve the AIC process as well as the resulting solar cells will be discussed together with our vision on the direction and future of AIC solar cell research.

In order to relax the mechanical constraints of processing thin crystalline Si wafers into highly efficient solar cells, we propose a process sequence, where a significant part of the process is done on module level. The device structure is an interdigitated-back-contact cell with an amorphous silicon back surface field. The record cell reaches an independently confirmed efficiency of 18.4%. Although the device deserves further optimization, the result shows the compatibility of processing on glass with efficiencies exceeding 18%, which opens the door to a high-efficiency solar cell process where the potentially thin wafer is attached to a foreign carrier during the full processing sequence.

Porous silicon plays an important role in the concept of wafer-equivalent epitaxial thin-film solar cells. Although porous silicon is beneficial in terms of long-wavelength optical confinement and gettering of metals, it could adversely affect the quality of the epitaxial silicon layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the epitaxial layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron-doped (1016/cm3) epitaxial layers grown on reorganised porous silicon as well as on pristine mono-crystalline, Czochralski, p+ silicon. Surprisingly, the bulk lifetime of epitaxial layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of layers on top of bare p+ substrate (32–50 µs). It is believed that proper surface closure prior to epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the epitaxial layer/porous silicon interface was found to be ~250 times more recombinative than an epitaxial layer/p+ substrate interface (S ≅ 103 cm/s). However, the inclusion of an epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.

Epitaxial silicon solar cells (“epicells”) are based on an epitaxial active layer (“epilayer”) grown on top of a low-cost, inactive p+ silicon substrate. A key challenge is to mitigate transition metal out-diffusion from the low-purity substrate into the active layer. An embedded porous silicon (PSi) layer can be used to getter metals within the substrate. This was studied theoretically using density functional theory where large binding energies (∼1.9–2.2 eV) for metal segregation to PSi void surface were calculated for Fe and Cu. Incorporating this in a diffusion model yielded large gettering coefficients of ∼104 even at 1000 °C. To verify this experimentally, a test structure consisting of a 2-µm thick epilayer grown on top of an 8.5 × 8.5 cm2 area of re-organized PSi etched into the middle of an 8″ Cz, p+ wafer was used. These wafers were surface-contaminated with metals (Fe, Ni, Cu) to ∼1014–1015 cm−2 and annealed at high temperatures (950–1000 °C) for up to 15 min. This allowed the metals to distribute throughout the wafer and getter to preferential sites. Direct total reflection X-ray fluorescence mapping of Cu on the front side showed that the embedded PSi reduced the amount of Cu reaching the top surface by ∼103 times, compared to the areas without PSi. Moreover, SIMS depth profiling revealed large metal concentrations (1018–1019 cm−3) in the depth associated with PSi, while the metal concentrations were below detection limits in the surrounding area, suggesting a gettering coefficient of ∼103–104. A slow cooling rate and smaller pore radii were also found to be beneficial for gettering.

We study the effect of metal nanoparticles, showing localised plasmonic resonances, on the spectrally resolved efficiency of thin film crystalline silicon solar cells. We investigate model structures: silver (Ag) nanodiscs on the surface of epitaxial cells grown on highly doped silicon substrates, with a controlled micron-scale thickness. The cells have no back reflector in order to exclusively study the effect of the front surface on their optical properties. The nanodiscs were deposited through hole-mask colloidal lithography, which is a low-cost, bottom-up and extremely versatile technique. As opposed to many other works, we use as benchmarks both bare silicon cells and cells with a dielectric antireflection coating. We optically observe a resonance showing an absorption increase, found to be controllable by the discs parameters. We also see an increase in short-circuit current with respect to bare cells, but we see a decrease in efficiency with respect to cells with a dielectric antireflection coating, due to losses at short wavelengths. As the material properties are not notably affected by the particles deposition, we show that the main loss mechanisms are an important parasitic absorption in the nanoparticles and destructive interferences.

Deep-level transient spectroscopy (DLTS) has been applied to high-temperature annealed n- and p-type Si wafers. The aim is to identify the deep levels responsible for the observed minority carrier lifetime degradation after thin-film transfer to a glass substrate. Anneals have been performed at 1150 °C in H2 or Ar. Care has been taken to avoid radiation defect formation during the fabrication of the Al Schottky barriers used for DLTS. It is shown that besides a change in the carrier doping density and profile, an annealing-induced electron trap at 0.43 eV below the conduction band edge can be found, which is related to a vacancy–impurity complex.

Crystalline Si (c-Si) technology is dominating the photovoltaics market. These modules are nonetheless still relatively expensive, in particular because of the costly silicon wafers, which require large thickness mostly to ease handling. Thin-film technologies, on the other hand, use much less active material, exhibit a much lower production cost per unit area, but achieve an efficiency still limited on module level, which increases the total system costs. A meet-in-the-middle is possible and is the object of this paper. The development of c-Si thin-foil modules is presented: first, the fabrication of the active material on a glass module and then the processing of the Si foils into solar cells, directly on module level. The activity of IMEC in this area is put into perspective with regard to worldwide research results. It appears that great opportunities are offered to this cell concept, although some challenges still need to be tackled before cost-effective and reliable industrial production can be launched. Copyright © 2012 John Wiley & Sons, Ltd.

Monolithic solar modules made from thin-film crystalline-silicon layers of high quality on glass substrates could lower the price of photovoltaic electricity substantially. This paper describes three different approaches that we are currently investigating to address the challenge to form high-quality crystalline-silicon layers on glass substrates. The SLiM-Cut approach is a wafering technique that results in 50-micron thick layers with a minimum of material loss. We show that crack initiation can be used as a means to better control the lift-off process. The epifree approach involves the lift-off of ultra-thin monocrystalline films formed by reorganization of cylindrical macropore arrays in silicon upon annealing. So far, films with a thickness of around 1 μm and very simple cells with an efficiency of up to 4.1% have been achieved. Finally, a seed layer approach is presented based on the epitaxial thickening by thermal CVD of monocrystalline silicon layers bonded on glass-ceramic substrates. Very promising cell efficiencies of 11% and Voc values of up to 610 mV have been achieved using a very simple and non-optimized cell structure.

In the quest for lowering the manufacturing cost of silicon solar cells, imec has been working successfully on two crystalline Si ‘thin-film’ cell concepts. In a first concept, a 20 µm-thin Si solar cell is epitaxially grown on top of a porous Si-based Bragg-type reflector which is electrochemically etched in a low-cost UMG Si substrate. Large area solar cells with efficiencies of 15.2% have been made, using (semi-)industrial processing tools. This clearly demonstrates that this cell concept has almost reached the stage of industrial application. In a second, longer-term approach, a 1–5 µm-thin, stand-alone mono-crystalline film is created based on the controlled annealing of an ordered macroporous silicon layer (the ‘Epi-free’ process). With this very thin Si layer, a simple proof-of-concept solar cell has been made exhibiting an efficiency of 4%. By optimizing the cell process in terms of light trapping and passivation, efficiencies over 15% can be expected from this technology.

This work initiates an investigation of the impact of high-temperature annealings on the material quality of reusable substrates for an "Epifree" solar-cell process, where the substrate itself provides the active layer of the cell. The minority-carrier lifetime of simple bulk wafers is monitored by photoconductance decay and the mechanisms affecting it are explored by deep-level transient spectroscopy. The lifetime is found to drop from the first annealing and then to stabilize to values sufficient for solar-cell application, at a minimum of 101 μs. The amplitude of this drop is strongly related to the wafer type (MCz or Cz) and no major recombination center could be identified as possible cause.

The “Epifree” process involves the lift-off of a high-quality monocrystalline film formed by reorganization upon annealing of cylindrical macropore arrays in silicon, and can thus provide high-quality silicon films without resorting to costly epitaxy. The challenge of this new process lies in etching controlled and regular pores in silicon in a cost-efficient way, and in developing a process compatible with the difficulty of handling a micron-thin material. Proof-of-concept cells have previously been achieved and this paper presents the latest progress, with a first development of thicker films and the inclusion of rear-side passivation. The energy-conversion efficiency of 1-µm-thin Epifree cells was improved from 2.6 to 4.1% by depositing a stack of amorphous silicon (a-Si) layers as rear-side passivation. The increase in Voc was, however, limited and bound to a drop in Jsc. The choice of a-Si was revealed to be unsuitable because of the thinness of the film and the presence of a full aluminum rear contact. The thinness of the film leads to a decrease in rear-side reflectivity by the a-Si absorption, and the aluminum, although not leading to crystallization, partly migrates inside the a-Si stack upon anodic bonding as shown by TEM. These factors indicate that an alternative surface passivation should be developed. In parallel to process developments, the material was thickened by modifying the macropore array dimensions, leading to a 2.4-µm-thick material over 1 cm × 1 cm areas. The efficiency of the next cells is expected to increase with this thicker material. Copyright © 2010 John Wiley & Sons, Ltd.

Solar modules made from thin-film crystalline-silicon layers of high quality on glass substrates could lower the price of photovoltaic electricity substantially. One way to create crystalline-silicon thin films on non-silicon substrates is to use the so-called “seed layer approach”, in which a thin crystalline-silicon seed layer is first created, followed by epitaxial thickening of this seed layer. In this paper, we present the first solar cell results obtained on 10-μm-thick monocrystalline-silicon (mono-Si) layers obtained by a seed layer approach on transparent glass-ceramic substrates. The seed layers were made using implant-induced separation and anodic bonding. These layers were then epitaxially thickened by thermal CVD. Simple solar cell structures without integrated light trapping features showed efficiencies of up to 7.5%. Compared to polycrystalline-silicon layers made by aluminum-induced crystallization of amorphous silicon and thermal CVD, the mono-Si layers have a much higher bulk diffusion lifetime.

Thin layers of silicon for solar cells can be lifted-off from wafers by taking advantage of the property of macropores to reorganise at high temperature and, in specific conditions, to form a high-quality layer on top of an empty space. Those conditions need to be identified and this work focuses in particular on the annealing ambient composition. Its influence was investigated by scanning and transmission electron microscopy and by Fourier-transform infrared spectroscopy. Apart from hydrogen, which has been used in previous studies, argon was found to be also compatible with the reorganisation. This result points out that the presence of oxygen impurities may not be as deleterious as expected, but that those impurities complicate the set of reactions taking place during the high-temperature process.

Thin films of polysilicon are an attractive material to reduce the cost of photovoltaic energy. Among the different polysilicon techniques, fine-grained polysilicon deposited directly onto a foreign substrate is an interesting option, since no extra seed layer or crystallization step is needed. However, the fabrication of efficient fine-grained polysilicon solar cells is a real challenge due to the large number of defects and the small average grain size of only 0.2 µm. This paper reports on our recent progress with fine-grained polysilicon solar cells. Using a diffuse refracting top surface and a more efficient two-step hydrogenation, we obtained an efficiency of 5.0%.