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Electromigration (EM) becomes one of the most challenging reliability issues for current and future ICs in 10-nm technology and below. In this article, a novel method is proposed for the EM hydrostatic stress analysis on 2-D multibranch interconnect trees, which is the foundation of the EM reliability assessment for large-scale on-chip interconnect networks, such as on-chip power grid networks. The proposed method, which is based on an eigenfunction technique, could efficiently calculate the hydrostatic stress evolution for multibranch interconnect trees stressed with different current densities and nonuniformly distributed thermal effects. The proposed method solves the partial differential equations of transient EM stress more efficiently since it does not require any discretization either spatially or temporally, which is in contrast to numerical methods, such as the finite difference method and finite element method. The accuracy of the proposed transient analysis approach is validated against the analytical solution and commercial tools. The convergence of the proposed method is demonstrated by numerical experiments on practical power/ground networks, showing that only a small number of eigenfunction terms are necessary for the accurate solution. Thanks to its analytical nature, the proposed method is also utilized in efficient EM analysis techniques, such as searching for the void nucleation time by a modified bisection algorithm. The numerical results show that the proposed method is 10X–100X faster than the finite difference method and scales better for larger interconnect trees. [ABSTRACT FROM AUTHOR]

Considering temperature gradient or thermomigration (TM) impacts on electromigration (EM) due to Joule heating was less studied in the past. In this article, we propose a new semi-analytical stress transient analysis method to consider both EM and TM effects for general multisegment interconnects. The new method is based on the separation of variables (SOVs) approach to find the analytic solution of coupled EM-TM partial differential equation (PDE). The algorithm consists of several steps. We first develop analytic solutions to compute the steady-state temperature distribution of multisegment wires. Based on this, we derive closed-form solutions for steady-state hydrostatic stress distribution in the context of thermal gradients due to Joule heating for multisegment interconnect wires. With the steady-state stress distribution, the coupled EM-TM PDE can be homogenized and solved by the SOV method. To deal with temperature/position-dependent diffusivity of metal migration process due to nonuniform temperature distribution, we utilize a piecewise linear technique to approximate the position-dependent diffusivity. The numerical results on multisegment interconnects show that the proposed method has negligible error loss compared to commercial finite element analysis software COMSOL but is about an order of magnitude faster than COMSOL with $10\times $ less memory footprint. The numerical results further show that temperature gradient due to Joule heating indeed has significant impacts on the EM failure process. [ABSTRACT FROM AUTHOR]

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this paper, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First, we show that multisegment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: 1) reservoir-enhanced acceleration; 2) sink-enhanced acceleration; and 3) a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this paper since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. The simulation results show that using the proposed method, we can reduce the EM lifetime of a chip from ten years down to a few hours (about ${10^{5}} \times $ acceleration) under the 150 °C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs. [ABSTRACT FROM AUTHOR]

Electromigration (EM) is considered to be one of the most important reliability issues for current and future ICs in 10-nm technology and below. In this article, we propose a fast analytic solution to compute the stress evolution in the confined multisegment interconnect wires. The new method, called the accelerated separation of variables (ASOV) method, aims to find the analytic solutions of the partial differential equations of stress in confined interconnect metals based on the SOV method. It offers several improvements over the existing plain SOV-based method. First, we show that the accuracy of the solution depends on the structure of the interconnects. As a result, the number of required eigenvalues is structure and problem dependent, instead of fixed numbers used by the existing SOV method. Second, for the straight line multisegment and star-structured multiterminal interconnects, analytical expressions are formulated to calculate the eigenvalues directly instead of using numerical methods as in the existing SOV method. Third, we propose a linear Gaussian elimination (GE) algorithm by exploiting the banded structure with the serrated-edge form of the transcendental matrix, which can significantly speed up GE process, and is the key computing step in the SOV-based solution framework. Fourth, instead of using the simple bisection search, we propose to use an enhanced determinant-based secant iterative method to find the eigenvalues of the transcendental matrix. Numerical results show that a good agreement is achieved between analytical and numerical results on two special cases, and the resulting algorithm can lead to 3–5X speedup over the existing plain SOV-based solution on a number of multisegment interconnects benchmarks. [ABSTRACT FROM AUTHOR]

Recently, many physics-based electromigration (EM) models have been proposed to mitigate the over-conservativeness of existing Black–Blech-based EM models. To assess EM failures, one needs to estimate how the void grows after the nucleation phase. As a result, it is important to estimate the saturation volume of a void, which is important for EM mortality check. The existing saturation void volume model only works for a single wire segment. In this paper, we propose a new model for fast estimation of the void’s saturation volume for general multisegment interconnect wires. The new model is based on the fundamental atom conservation at the steady-state condition of void growth phases. The new formula agrees with the existing saturation void volume formula for the single-segment wire case and is a natural extension of the single-segment case to general multisegment wires. In addition, we consider the impacts of the void volume on final stress distributions of the wire to further improve the accuracy of the proposed formula. Based on the new formula, we propose a new EM immortality check flow, which considers both the recently proposed EM immortality in the void nucleation phase and the void saturation volume in the growth phase. The new flow can further reduce the conservativeness of the existing EM failure effect analysis. The numerical results show that the proposed formula agrees well with a published work for two-segment cases, which are supported by experimental data. The formula is also validated by the recently proposed physics-based 3-D finite-element (FEM) analysis tool for general multisegment interconnect wires. We also demonstrate new EM immortality check flow to quickly identify the new type of immortal wires, which are nucleated but with smaller-than-critical voids. [ABSTRACT FROM AUTHOR]

This paper proposes a new power–ground (P/G) network sizing technique based on the recently proposed fast electromigration (EM) immortality check method for general multisegment interconnect wires and a new physics-based EM assessment technique for more accurate time to failure analysis. This paper first shows that the new P/G optimization problem, subject to the voltage IR drop and new EM constraints, can still be formulated as an efficient sequence of linear programing problem, where the optimization is carried out in two linear programing phases in each iteration. The new optimization will ensure that none of the wires fail if all the constraints are satisfied. However, requiring all the wires to be EM immortal can be overconstrained. To mitigate this problem, the first improvement is by means of adding reservoir branches to the mortal wires whose lifetime cannot be made immortal by wire sizing. This is a very effective approach as long as there is a sufficient reservoir area. The second improvement is to consider the aging effects of interconnect wires in the P/G networks. The idea is to allow some short-lifetime wires to fail and optimize the rest of the wires while considering the additional resistance caused by the failed wire segments. In this way, the resulting P/G networks can be optimized, such that the target lifetime of the whole P/G networks can be ensured and will become more robust and aging-aware over the expected lifetime of the chip. Numerical results on a number of IBM and self-generated power supply networks demonstrate that the new method can effectively reduce the area of the networks while ensuring immortality or enforcing target lifetime for all the wires, which is not the case for the existing current-density-constrained optimization methods. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel and fast electromigration (EM) immortality check for general multisegment interconnect wires. Instead of using current density as the key parameter, as in traditional EM analysis methods based on Black’s equation and the Blech limit, the new method estimates the EM-induced steady-state stress in general multisegment copper interconnect wires based on a novel parameter,Critical EM Voltage, ${V_{\mathrm { Crit,EM}}}$. We show that the ${V}_{\mathrm { Crit,EM}}$ is essentially the natural, but important, extension of theBlech limitconcept, which describes the EM immortality condition for a single segment wire, to more general multisegment interconnect wires. The proposed method, called voltage-based EM (VBEM) method, mitigates the problem of current-density-based EM criteria, which can only be applied to a single wire. The new VBEM method can naturally comprehend the impact of the topology of the wire structure on EM-induced stress. As a result, this new VBEM analysis method is very amenable to addressing EM violations, as it brings new optimization capabilities to the physical design flow. The VBEM stress estimation method is based on the fundamental steady-state stress equations. This approach avoids computationally intensive numerical methods and can be implemented in CAD tools very easily, as we demonstrate on real design examples. We also show that the proposed VBEM analysis method agrees with results from the finite difference method in the steady state through one example and also agrees with one published closed-form expression of steady-state stress for a special 3-terminal wire case. Furthermore, we compare VBEM against the COMSOL finite element analysis tool and another published EM numerical simulator XSim, validated by measured results, which shows that VBEM agrees with both of them very well in terms of accuracy and thus further validates the proposed method. We also study the impact of current crowding in practical interconnect wires on the estimated steady-state stress, which are shown to be not significant if the length of the wire is much greater than its width. An extension of the VBEM method to consider the significant current crowding effects is also shown and additionally, we analyze mesh-structured interconnect wires and demonstrate that the proposed VBEM method is correct and accurate on such structures. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel finite-element method-based stress analysis for void growth process after the void is nucleated in the confined copper interconnects. We focus on the postvoiding analysis of void evolution, which remains challenging and less addressed in the past because void growth leads to transient structural changes in the copper interconnects. The new method explicitly considers the stress distribution’s impacts on the void volumes due to atomic conservation in confined wires. We introduce a phase-field equation that results in two coupled dynamic systems to describe the whole postvoiding stress evolution process. A novel regulated void growth velocity is introduced in order to consider the inherent physical interaction between the void volume and stress distribution in a confined interconnect wire. Numerical results show that the computed stress distributions and extracted current exponent values fit the measured results better than a recent postvoiding analysis work. Furthermore, the proposed electromigration analysis method models the Joule heating effect on wire resistance and temperature change, which were well observed in the published experiments. [ABSTRACT FROM AUTHOR]

Abstract Counterfeiting of integrated circuits (ICs) has become an increasingly vital concern for the security of commercial and mission-critical systems. Moreover, they pose an immense economic, security, and safety threat. We propose a comprehensive detection and prevention framework consisting of a multi-functional on-chip aging sensor, and post-fabrication authentication methodology. This framework targets several classes of counterfeit ICs, such as recycled, remarked, out-of-spec, cloned, and over-produced ICs. First, the new sensor consists of both antifuse memory and aging sensors. To reduce reference-circuit related area-overhead, the initial electronic properties of sensor circuits are stored in a global database, accessed by unique chip via challenge-response pairs. Second, this work consists of a two aging-sensor approach, based on IC wear-out effects, using a recently proposed electromigration (EM) aging sensor and a ring oscillator aging sensor. This method can be effective for chip usage estimation of both short and long time periods. Hence, it can serve as a more accurate timer for the chip to meter the long term usage, which can allow for timed services of some functionality of a chip, in addition to detection of the recycled/remark ICs. Third, on top of the new sensor, we propose a new post-fabrication authentication methodology to detect and prevent non-defective counterfeit ICs. All fabricated ICs will be registered in a global database and activated with a unique chip ID, which is written into the antifuse memory. Simulation results show that the combined aging sensors have a high degree of accuracy when compared to traditional on-chip sensors. Highlights • We propose a new on-chip sensor which combines a one-time programmable (OTP) antifuse memory block with existing aging sensors. Unlike existing methods, here, the memory block is not used as a counter but as a storage for a unique chip ID, timestamp of activation, and other important chip assets. The critical information stored in antifuse memory can be encrypted against tampering and be verified by challenge-response pairs. • The proposed on-chip sensor combines two types of aging sensors to detect short-term and long-term aging effects effectively and area-efficiently. The RO-based sensor is effective for short-time usage detection, and the EM-based aging sensor is accurate and area-efficient for long-term usage detection. The EM-based aging sensor exploits the natural aging/failure mechanism of interconnect wires to time the aging of the chip. It can serve as a more accurate timer for the chip to meter the usage of long time periods. This method enables timed service for some functionality of a chip and can also avoid over-usage of the authorized period for a chip or a system under certain security requirements. • In addition to the on-chip aging sensor, we also propose a post-fabrication authentication methodology to detect and prevent non-defective counterfeit ICs. All fabricated ICs are registered and activated with a unique chip ID in a global database. The unique chip ID will be written into the antifuse memory during a registration process and the chip will be activated. This method not only prevents cloned and over-produced ICs, but also mitigates the need for reference circuits in existing aging sensor designs. This significantly reduces area overhead, as the initial electronic properties of the sensor circuits can be stored in the global database. [ABSTRACT FROM AUTHOR]

Electromigration effects are a key failure mechanism for copper-based dual damascene interconnects wires in semiconductor technologies. However, accurately predicting the time-to-failure for a complicated interconnect tree in a VLSI interconnect layout requires detailed knowledge of the stress evolutions over time, and is subject to time-varying currents and temperature. This is a challenging problem as one needs to solve the stress-based partial differential equations (PDEs) in the time domain for confined copper damascene interconnect trees for both void nucleation and void growth phases. To mitigate this problem, we propose a novel Krylov subspace-based method for fast numerical solutions to the stress PDEs. The new approach, which we call FastEM, is based on the finite-difference method which is used to first discretize the PDEs into linear time-invariant ordinary differential equations (ODEs). After discretization, a modified Krylov subspace-based reduction technique is applied in the frequency domain to reduce the size of the original system matrices so that they can be efficiently simulated in the time domain. The FastEM can perform the simulation process for both void nucleation and void growth phases under piecewise constant linear current density inputs and time-varying stressing temperatures. Furthermore, we show that the steady-state response of stress diffusion equations can be obtained from the resulting ODE system in the frequency domain, which agrees with the recently proposed voltage-based EM analysis method for EM immortality checks. Numerical results show that the proposed method can lead to about 1–2 orders of magnitude speed-up over existing finite-difference time-domain-based methods on large interconnect trees for both void nucleation and growth phases with negligible errors. We further show that for most of the interconnect trees tested; we only need a small number of dominant poles for sufficient accuracy. [ABSTRACT FROM AUTHOR]

Electromigration (EM) becomes a major reliability concern in 3-D integrated circuits (3-D ICs). To mitigate this problem, a typical solution is to use through-silicon via (TSV) redundancy in a reactive manner, maintaining the operability of a 3-D chip in the presence of EM failures by detecting and replacing faulty TSVs with spares. In this paper, we explore an alternative, more preferred approach to enhance the EM-related lifetime reliability of TSV grid, in which redundancy is used proactively to allow nonfaulty TSVs to be temporarily deactivated. In this way, EM wear-out can be extended by exploiting its recovery property. The proposed solution is based on two consecutive stages, in which TSV redundancy allocation and TSV repair are finalized at both design-time and runtime, respectively. Applied to 3-D benchmark designs, the recovery-aware proactive repair approach increases EM-related lifetime reliability (measured in mean-time-to-failure) of the entire TSV grid by up to $12\times $ relative to the conventional reactive method, with similar area overhead. In addition, a runtime dynamic recovery approach is proposed to further improve EM-related lifetime reliability to account for stress variation across different chips and over the operational lifetime. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new energy and lifetime optimization techniques for emerging dark silicon manycore microprocessors considering both hard long-term reliability effects (hard errors) and transient soft errors, which have been studied less in the past. We consider a recently proposed physics-based electromigration (EM) reliability model to predict the EM-induced reliability. We employ both dynamic voltage and frequency scaling (DVFS) and dark silicon core state using ON/OFF switching action as the two control knobs. We show that on-chip power consumption has different (even contradicting) impacts on soft and hard reliability effects. This paper also shows that soft error should be mitigated by other techniques if aggressive low power and high long-term reliability are pursued. We focus on two optimization techniques for improving lifetime and reducing energy. To optimize EM-induced lifetime, we first apply the adaptive Q-learning-based method, which is suitable for dynamic runtime operation as it can provide cost-effective yet good solutions. The second lifetime optimization approach is the mixed-integer linear programming (MILP) method, which typically yields better solutions but at higher computational costs. To optimize the energy of a dark silicon chip subject to the both hard and soft reliability effects, power budgets, and performance limits, the Q-learning method has been applied as well. A large class of multithreaded applications is used as our benchmarks to validate and compare the proposed dynamic reliability management methods. Experimental results on a 64-core dark silicon chip show that the proposed DRM algorithm can effectively manage and optimize the lifetime of a dark silicon microprocessor under the given power budget and performance limit. Also, the proposed energy optimization can effectively manage and optimize energy consumption subject to both hard and soft-error rates, power budget, and performance limits as constraints. We also show that the under tightened power and performance constraints, we cannot satisfy both hard and soft errors at the same time as there is no simple tradeoff between performance/power and reliability in this case. Some other soft-error mitigation techniques are required in this case. [ABSTRACT FROM PUBLISHER]

Electromigration (EM) in very large scale integration (VLSI) interconnects has become one of the major reliability issues for current and future VLSI technologies. However, existing EM modeling and analysis techniques are mainly developed for a single wire. For practical VLSI chips, the elemental EM reliability unit called interconnect tree is a multibranch interconnect segment consisting of a continuously connected, highly conductive metal (Cu) lines terminated by diffusion barriers and located within the single level of metallization. The EM effects in those branches are not independent and have to be considered simultaneously. In this paper, we demonstrate, for the first time, a first principle-based analytical solution of this problem. We have derived the analytical expressions describing the hydrostatic stress evolution in several typical interconnect trees: 1) the straight-line three-terminal wires; 2) the T-shaped four-terminal wires; and 3) the cross-shaped five-terminal wires. The new approach solves the stress evolution in a multibranch tree by de-coupling the individual segments through the proper boundary conditions (BCs) accounting the interactions between different branches. By using Laplace transformation technique, analytical solutions are obtained for each type of the interconnect trees. The analytical solutions in terms of a set of auxiliary basis functions using the complementary error function agree well with the numerical analysis results. Our analysis further demonstrates that using the first two dominant basis functions can lead to 0.5% error, which is sufficient for practical EM analysis. [ABSTRACT FROM PUBLISHER]

This article presents a new approach for system-level reliability management for multi/many core microprocessors. In the new approach, the electro-migration (EM) induced time to failure (TTF) at the system level is modeled as a resource, which is abstracted, from a recently proposed physics-based EM model, at the chip level. In this model, a single core can spend the TTF resources at different rates specified by the temperature and the related power consumption. As a result, the new resource-based EM model allows more flexible EM-reliability management for multi/many-core systems. As an application of the new model, we propose a novel task migration method to explicitly balance consumption of EM resources for all the cores. The new method aims at equalizing the probability of failure of each core, which will maximize the lifetime of the whole multi/many core system. To more efficiently regulate the lifetime of the multi/many core system, dynamic voltage and frequency scaling (by using different performance states (p-states), which can represent different operating voltages and frequencies) is further employed to compensate for the excessively consumed lifetime of all the cores when the chip is loaded with heavy tasks for a certain period of time. In this way, the TTF of all the cores could be compensated to meet the lifetime requirement, giving the multi/many core system more flexibility to handle heavy task assignment on demand. Experimental results on a 36-core processor platform show that the proposed task migration scheme could balance the lifetime consumption of all the cores, and maintain even-distributed TTF slacks across different cores, while the existing temperature-based task migration schemes lead to diverged TTF of cores. The results also show that the TTF consumption could be easily compensated for by switching to a low p-state, which could not be achieved if TTF consumption diverged across different cores. [ABSTRACT FROM AUTHOR]

In recent years the concern over Hardware Trojans has come to the forefront of hardware security research as these types of attacks pose a real and dangerous threat to both commercial and mission-critical systems. One interesting threat model utilizes semiconductor physics, specifically aging effects such as Electromigration (EM). However, existing methods for EM-based Trojans rely on empirical Black's models can easily lead to performance degradation and less accuracy in Trojan activation time prediction. In this article, we study the EM-based Trojan attacks based on recently developed physics-based EM models. We propose novel EM attack techniques in which the EM-induced hydrostatic stress increase in a wire is caused by wire structure or layer changes without changing the current density of the wires. The proposed techniques consist of sink/reservoir insertion or sizing and layer switching techniques based on the early and late failure modes of EM wear-out effects. As a result, the proposed techniques can have minimal impact on circuit performance, which is in contrast with existing current-density-based EM attacks. The proposed techniques can serve as a trigger for the EM attack on power/ground networks and signal and clock networks. Furthermore, we also present two potential EM attack mitigation techniques, namely, the split fabrication and burn-in testing. • Utilization of physics based Electromigration models and simulation techniques to create novel reliability based Trojans. • Presents difficult to detect topology and structure based Electromigration Trojans to minimize side channel impact. • Discusses techniques for mitigating the effectiveness of Electromigration based Trojans. [ABSTRACT FROM AUTHOR]

Electromigration (EM) has been considered to be the dominant back end of line (BEOL) reliability issue for current and future VLSI technologies. Current EM reliability analysis is overloaded by over-conservative and simplified EM models. Particularly the transient recovery effect in the EM-induced stress evolution kinetics has never been modeled properly in all the existing analytical EM models. In this article, we propose a new physics-based dynamic compact EM model, which for the first time, can accurately predict the transient hydrostatic stress recovery effect in a confined metal wire. The evolution of preexisted void volume and the corresponding metal line resistance change can be further derived based on the stress evolution. The new dynamic EM model is based on the direct analytical solution of one-dimensional Korhonen's equation with load driven by any unipolar or bipolar current waveforms under varying temperature. We show that the EM recovery effect can be quite significant even under unidirectional current loads. This recovery/healing process is sensitive to temperature, and higher temperatures lead to faster and more complete recovery. Such effect can be further exploited to extend the lifetime of the interconnect wires if the chip current or power can be properly regulated and managed. As a result, the new dynamic EM model can be incorporated with existing dynamic thermal/power/reliability management and optimization approaches, devoted to reliability-aware optimization at multiple system levels (chip/server/rack/data centers). Presented results show that the proposed EM model agrees very well with the numerical analysis results under any time-varying current density and temperature profiles. [ABSTRACT FROM AUTHOR]

With technology scaling, reliability has emerged as a major design constraint for very-large-scale integrated circuits. Many prior works have investigated electromigration (EM) on full-chip power grid interconnects. However, most of the published results were obtained under the assumption of uniformly distributed temperature and/or residual stress across interconnects. In this paper, we demonstrate the implementation of novel methodology and flow for full-chip EM assessment on the multi-layered power grid networks of a 32 nm test-chip and investigate the impacts of the within-die temperature and thermal stress variations on the failure rate. The proposed approach is based on recently developed physics-based EM models and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. The cross-layout temperature distribution caused by power dissipations in devices and by interconnect Joule heating has been characterized and taken into account in the full-chip EM assessment methodology. Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure. Furthermore, the consideration of thermal stress variation results in a retarded EM induced degradation. [ABSTRACT FROM AUTHOR]