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Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method.

Authors :
Cook, Chase
Sun, Zeyu
Demircan, Ertugrul
Shroff, Mehul D.
Tan, Sheldon X.-D.
Source :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; May2018, Vol. 26 Issue 5, p969-980, 12p
Publication Year :
2018

Abstract

Electromigration effects are a key failure mechanism for copper-based dual damascene interconnects wires in semiconductor technologies. However, accurately predicting the time-to-failure for a complicated interconnect tree in a VLSI interconnect layout requires detailed knowledge of the stress evolutions over time, and is subject to time-varying currents and temperature. This is a challenging problem as one needs to solve the stress-based partial differential equations (PDEs) in the time domain for confined copper damascene interconnect trees for both void nucleation and void growth phases. To mitigate this problem, we propose a novel Krylov subspace-based method for fast numerical solutions to the stress PDEs. The new approach, which we call FastEM, is based on the finite-difference method which is used to first discretize the PDEs into linear time-invariant ordinary differential equations (ODEs). After discretization, a modified Krylov subspace-based reduction technique is applied in the frequency domain to reduce the size of the original system matrices so that they can be efficiently simulated in the time domain. The FastEM can perform the simulation process for both void nucleation and void growth phases under piecewise constant linear current density inputs and time-varying stressing temperatures. Furthermore, we show that the steady-state response of stress diffusion equations can be obtained from the resulting ODE system in the frequency domain, which agrees with the recently proposed voltage-based EM analysis method for EM immortality checks. Numerical results show that the proposed method can lead to about 1–2 orders of magnitude speed-up over existing finite-difference time-domain-based methods on large interconnect trees for both void nucleation and growth phases with negligible errors. We further show that for most of the interconnect trees tested; we only need a small number of dominant poles for sufficient accuracy. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
10638210
Volume :
26
Issue :
5
Database :
Complementary Index
Journal :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Publication Type :
Academic Journal
Accession number :
130091797
Full Text :
https://doi.org/10.1109/TVLSI.2018.2800707