Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method.

MLA

Cook, Chase, et al. “Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 5, May 2018, pp. 969–80. EBSCOhost, https://doi.org/10.1109/TVLSI.2018.2800707.

APA

Cook, C., Sun, Z., Demircan, E., Shroff, M. D., & Tan, S. X.-D. (2018). Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(5), 969–980. https://doi.org/10.1109/TVLSI.2018.2800707

Chicago

Cook, Chase, Zeyu Sun, Ertugrul Demircan, Mehul D. Shroff, and Sheldon X.-D. Tan. 2018. “Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (5): 969–80. doi:10.1109/TVLSI.2018.2800707.