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High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance ${R}_{\text {on,sp}}$ of the SJ and the high breakdown voltage ${V}_{\text {B}}$ of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced ${R}_{\text {on,sp}}$ without sacrificing ${V}_{\text {B}}$ . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high ${V}_{\text {B}}$ . The experimental results exhibit a ${R}_{\text {on,sp}}$ of 145 $\text{m}\Omega \cdot $ cm2 with a ${V}_{\text {B}}$ of 977 V. This represents a reduction in ${R}_{\text {on,sp}}$ by 18.1% when compared with the theoretical ${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ “silicon limit”.

3-D edge termination design and analytic model for specific on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}})$ versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters ${L}_{1}$ and ${L}_{2}$ in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at ${L}_{1} = 30~\mu \text{m}$ and ${L}_{2} = 1~\mu \text{m}$ . On the other hand, an analytic model is developed to describe the relation between ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV, which is obtained as ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}} = 5.93 \times 10^{-6} \times 22({T}/298)^{1.7} \times \text {BV}^{2}$ and theoretically verifies that the fabricated device has achieved optimized ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 86.49 $\text{m}\Omega ~\cdot $ cm2 and BV of 805 V, which is leading performance for the 700-V applications in published data.

The global optimization of the balanced symmetric vertical superjunction (VSJ) device is proposed based on the R-well model for the first time to realize the unique minimum specific on-resistance $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {min}}}$ . The R-well model, which is originated from our previous VSJ mode theory, shows the relationship between $R_{{\mathrm{\scriptscriptstyle ON}}}$ and the doping concentration N under the given pillar width W and breakdown voltage $V_{B}$ . The global $R_{{\mathrm{\scriptscriptstyle ON}}}$ optimization is realized to obtain the design formulas of N and the pillar length $L_{d}$ . The calculated results are in good agreement with the simulations. It is demonstrated from the comparisons with the simulations and the existing experiments that the optimization in this paper realizes the unique $R_{{on,\mathrm {min}}}$ with a relationship of $R_{{\mathrm{\scriptscriptstyle ON}}}\propto V_{B}^{1.03}$ . The R-well model is also universal for other $R_{on}$ optimizations.

A 700 V dual-buried-layer n-channel lateral double-diffused MOSFET (DB-nLDMOS) based on substrate termination technology (STT) is presented and experimentally demonstrated in this paper. The termination region is well analyzed and designed to avoid the premature avalanche breakdown caused by the curved junction. The 2-D and 3-D numerical simulations have been performed to optimize the three key parameters of $\Delta L_{1,}\Delta L_{2,}$ and $\Delta L_{3}$ which impact on breakdown voltage (BV) greatly in the termination region. The simulation results show that the electric field peak is reduced and premature avalanche breakdown is avoided at the curved abrupt p-well/n-well junction with the STT. The experimental results demonstrate that low $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}}$ of 105.6 $\text{m}\Omega \cdot {\mathrm{ cm}}^{2}$ based on $L_{d}$ and high BV of 788 V are achieved by the DB-nLDMOS.

A new relationship between the specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON}}$ and breakdown voltage $V_{B}$ for the balanced symmetric superjunction (SJ) device is presented to produce the lowest $R_{\mathrm{\scriptscriptstyle ON}}$ for a given $V_{B}$ . The design formulas, including the doping density NW and the drift length $L_{d}$ , are given for both the nonfull depletion (NFD) and the full depletion SJ devices with an introduction of the normalized $V_{B}$ factor $\eta $ . For the NFD SJ MOSFET, an $R_{\mathrm{\scriptscriptstyle ON}} \propto V_{B}^{1.03}$ relationship is obtained. The analytical results show good agreement with the numerical results.

An ultralow turn-OFF loss ( ${E} _{\mathrm{\scriptscriptstyle OFF}}$ ) silicon-on-insulator lateral insulated-gate bipolar transistor with a p-buried layer (PB SOI LIGBT) is first proposed. A universal ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model during inductive load turn-OFF is set up, which reveals that low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ can be achieved by reducing the total integral current charges, reducing the average anode voltage in the first phase and increasing the charge factor ${k}$ . Due to the large capacitance effect and extra hole extraction path induced by the PB, the three ideas for low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ are demonstrated in the PB SOI LIGBT. Simulation results show that the PB SOI LIGBT can achieve an 85% lower ${E} _{\mathrm{\scriptscriptstyle OFF}}$ compared with the conventional SOI LIGBT based on 6- $\mu \text{m}$ SOI layer. Furthermore, the proposed ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model can be applied to all the IGBTs, and it reveals the mechanism of low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ of the IGBT with a superjunction structure during inductive load switching.

The Backgate (BG) effect on specific ON-resistance ( $R_{{{\mathrm{{\scriptscriptstyle ON}},\rm sp}}})$ and breakdown voltage (BV) for the thin layer Silicon On Insulator (SOI) field p-channel lateral diffusion MOS (pLDMOS) are investigated in this paper. BG-induced dual conduction mode for the thin layer SOI field pLDMOS is revealed, which includes drift and accumulation conduction. Hole accumulation layer induced by BG voltage ( $V_{\rm BG})$ provides extra charges, resulting in a $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ reduction. An expression of equivalent $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ is given to describe the dependence of $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ on $V_{\rm BG}$ . Simultaneously, $V_{\rm BG}$ impacts strongly on BV, inducing three breakdown mechanisms: surface breakdown, bulk breakdown, and punchthrough breakdown. For surface breakdown, a positive linear dependence of BVs on $V_{\rm BG}$ is given with consideration to multiple $_{_{}}$ field plates (MFP). BV of −366 V and $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ of $7.5~\Omega \cdot $ mm $^{2}$ for the thin layer SOI field pLDMOS are achieved experimentally at $V_{\rm BG} = -200$ V.

The reduction of breakdown voltage (BV) influenced by high voltage interconnection (HVI) is a key problem in power integrated circuit, which essentially is that the modulation of electric field distribution at the device surface caused by HVI. In this paper, we review the developments of the methods to shield HVI including thick insulating film technology, field reduction layer technology, field plate technology and self-shielding technology. The four kinds of HVI technologies prevent BV degradation from the introduced adverse charge induced by interconnections in different ways. Thick insulting film technology increases the distance between the HVI and surface of silicon. Field reduction layer technology uses additional doping layers with optimized impurity concentration to enhance the depletion of the drift region under HVI. Field plate technology shields the influence of HVI with various field plate structures. Self-shielding technology makes HVI avoid crossing over high voltage junction terminal (HVJT), thus no additional shielding structure is needed. The divided reduced surface field (RESURF) technology solves the leakage current in the self-shielding structure.

A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (I esd ) path to improve the holding voltage (V h ) and failure current (I t2 ). The relation between V h and base-concentration (N b ) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing V h by changing N b . The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the I ESD distribution and V h . The longer ESD current path improves the V h by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the I t2 . DC and dynamic TLP simulation results show the V h = 5.3 V of proposed SCR is achieved with a higher failure current (I t2 ) of 1.68e-2A/μm.

A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving the isolation performance. According to the simulation results, the surface electric field peak of the proposed DTI LDMOS is reduced by 35 % due to the enhanced depletion effect of P-sink layer. Meanwhile, the concentration of DNW and P-top region are increased, thus the R on, sp is decreased. Furthermore, the isolation region area is reduced significantly so that the chip size will be minimized. The LDMOS with R on, sp of 96.2 mΩ·cm2 and BV of 758 V is experimentally achieved, which breaks the conventional R on, sp -BV silicon limit of double RESURF technology.

This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (R on, sp ) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (R on, sp ) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces R on, sp further and keep higher breakdown. The R on, sp of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BV DSS =27V and R on, sp =7.1 mΩ·mm2; 20V LDMOS has BV DSS =30V and R on, sp =8.8mΩ·mm2; 30V LDMOS has BV DSS =42V and R on, sp =14.5mΩ·mm2; 40V LDMOS has BV DSS =52V and R on, sp =20.5mΩ·mm2.

This paper presents three-dimensional (3-D) edge termination design of a 700-V triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with n-type top (n-top) layer. It is found that breakdown characteristics deterioration related to the electric field crowding and the local charge imbalance in the edge termination. The two crucial parameters L P and L 2 in the layout of the transition region of the edge termination were studied by 3-D numerical simulations and experiments to overcome these issues. As implantation dose of n-top layer (D ntop ) increases from 0.8 × cm−2 to 1.2 × cm−2, progressive performance with Fs from 805 V to 711 V and R on, sp from 86.49 mΩ· cm2 to 80.56 mΩ·cm2 is experimental obtained and the novel LDMOS demonstrates maximum figure of merit (FOM) in the latest existing 700-V LDMOS technologies.

A low turnoff loss (Eoff) silicon-on-insulator lateral insulated gate bipolar transistor with p-buried layer and double gates (DG-PB SOI LIGBT) is proposed. The proposed LIGBT features a p-buried layer (PB) in the n-drift region and an additional trench gate. Due to the large capacitance effect and hole extraction path induced by PB, larger number of the carriers is removed under low anode voltage (VA), which contributes to a fast turnoff and low turnoff loss (Eoff). What's more, the double gates (DG) structure can reduce the overall stored carriers in the on-state, further improving the Eoff ∼ Von tradeoff. Simulation results show that the DG-PB SOI LIGBT can achieve an 83 % lower Eoff compared with the conventional SOI LIGBT at the same Von of 1.05 V.

In this paper, ESD protection devices for power rails in a PDP scan IC are studied. By numerical simulation, current flow distribution of LIGBT under ESD stress is analyzed. The proposed latchup free LIGBT has additional discharge mechanism to optimize the discharge path, and much smaller discharge resistance can be obtained. As demonstrated by TLP test, optimized LIGBT has 33% larger It2 than HV diode, and its Vt2 is only 27 V higher than its breakdown voltage.

NBTI of BOX layer induced degradation for thin layer SOI field p-channel LDMOS is investigated by experiment, modeling and simulation. Decrease in drain current (Id) under high negative BG voltage (VBG) stressing is observed, which is ascribed to the positive fixed oxide charge and interface charge in BOX layer induced by NBTI. The NBTI conduction modulation model is proposed to elevate the positive charge density (ΔQp) generation in the BOX layer. The total on-resistance is enhanced because of hole concentration in the accumulation layer reduced by the positive charges. Simulated Id shift with applying the corresponding ΔQp in the BOX layer shows a good fitting with the measured result. Meanwhile, ΔQp in the BOX layer relaxes the electric field peak at the p-drift/n-well junction on the SOI/BOX interface, which is responsible for breakdown voltage (BV) increasing.

A novel high-voltage (HV) thick layer silicon-on-insulator (SOI) field p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) with single trench isolation is developed for HV switching IC based on 11-µm-thick silicon layer and 1-µm-thick buried oxide layer. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The deep trench is adopted to realize the compatibility between HV pLDMOS and LV CMOS. The device parameters T, Y for the HV SOI field pLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage (BV). The HV SOI field pLDMOS with a BV over 200V is experimentally realized and successfully applied to a 96-bit output driver integrated circuit (IC).

In this paper, the effect of field implantation (FI) on off-and on-state characteristics for thin layer SOI field P-channel LDMOS (FPLDMOS) is investigated. FI effect mechanisms are revealed by modeling, simulating, verifying experimentally. The channel discontinuity gives rise to current step in output curve due to strong electric field and impact ionized generation. Back gate (BG) punch-through breakdown weakens severely block capability. Process parameters for FI technology are optimized to avoid channel discontinuity and BG punch-through breakdown. The rugged thin layer SOI FPLDMOS with channel continuity and punch-through breakdown voltage of −329 V is realized experimentally, and successfully applied in 200-V switching IC.

On the base of appraising synthetically of measuring and testing technique and the monitoring system of thickness, the article analyzed the demand of thickness deviation. It also determined the control core of single chip, and studied on the on-line monitoring system of the wood-based Panel thickness, which is measured by laser sensor and differential transformer sensor and based on the technique of wireless sensors in order to develop monitoring precision and automation standard of blank thickness in wood-based panel industry.

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R on,sp ) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R on,sp and high BV of above 730 V are achieved by the JITR LDMOS. R on,sp of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV 2 /R on,sp ) in comparison to the published SJ LDMOS.

An ultra-low R on,sp 700 V DB-nLDMOS (dual P-buried-layer nLDMOS) which uses 0.35 μm technology and full ion implantation technology is proposed. Experimental results show that with 800 V BV ds, R on,sp is only 10.7 Ω · mm2 which is the lowest value of triple RESURF (REduce SURface Field) LDMOS reported before. This mainly benefits from two aspects. First, thermal budgets of the process are strictly limited after implantation of the Pbury layer. Secondly, device sizes of the neck region are optimised to reduce R on,sp which also suppress the JFET effect of the triple RESURF LDMOS.

An advanced low-cost and low-power high-voltage (HV) startup circuit which uses a 50 V pJFET and a 700 V T-nJFET (triple RESURF nJFET) is proposed. Compared with traditional technology, a mass of module area is saved. This mainly benefits from: first, with increase of V DS, I OFF (leakage current in off-state) can be quickly pinched off to a low value by pJFET without a large layout area which is needed for the traditional resistance method. Secondly, T-nJFET is located at the drain terminal of T-nLDMOS (triple RESURF LDMOS) with common drain electrode which also saves large area than traditional independent nJFET. Moreover, pJFET brings stable and low I OFF which leads to 4 mW P OFF (static power consumption in off-state) due to its low V P (pinch-off voltage) and high BVDS.

A novel ultra-thin partial silicon-on-insulator (PSOI) LDMOS with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conductivity region for majority carriers to significantly improve the self-heating effect. A combination of uniform and linear variable doping (LVD) profile with highly initial concentration is utilised in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (R on,sp) and breakdown voltage (BV), as well as achieving low power dissipation. With a 60-µm n-drift region length, the NBL PSOI LDMOS obtains a high BV of 940 V with a low maximum temperature (T max) of 327 K at a power (P) of 1 mW/μm, which is reduced by around 56 K in comparison to the conventional SOI LDMOS using an LVD profile for the n-drift region (LVD SOI LDMOS). Moreover, R on,sp of the NBL PSOI LDMOS is lower than that of the LVD SOI LDMOS for a wide range of BV from 400 to 900 V.

A novel 300-V high-side thin-layer-SOI field pLDMOS adopting field implant (FI) technology and multiple field plates (MFPs) has been developed. Breakdown mechanisms of back gate (BG) punchthrough and avalanche breakdown for highside thin-layer-SOI field pLDMOS are investigated by setting up an analytic model, simulating, and verifying experimentally. Shallow junction depth of p-field achieved by the proposed FI technology attenuates BG punchthrough effect; premature surface avalanche breakdown can be avoided by using MFPs. High-side field pLDMOS with a breakdown voltage (BV) of 340 V is experimentally realized on a 1.5-μm -thick SOI layer and successfully applied in a 200-V high-voltage switching IC.

An ultralow specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) power lateral MOSFET is proposed. The MOSFET features double trenches: an oxide trench in the drift region and a trench gate extended to the buried oxide (BOX) (SOI DT MOSFET). First, the oxide trench causes multiple-directional depletion, which leads to electric field reshaping and an enhanced reduced surface field effect in the SOI layer. The electric field distributions in the SOI and BOX are thus improved. The oxide trench also increases the electric field strength in the x-direction due to the lower permittivity of oxide than that of Si. Both increase breakdown voltage (BV). Second, the trench makes the drift region folded in the y -direction, resulting in reduced cell pitch and Ron,sp. Third, the trench gate extended to the BOX further reduces Ron,sp by widening the vertical conduction area. The BV of the DT MOSFET increases from 91 V of the conventional SOI LDMOS to 233 V at a half-cell pitch of 6.5 μm, and the Ron,sp decreases from 5.1 to 3.3 mΩ·cm2.

A 700 V self-ISO (isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) without epitaxy is proposed in this paper. By separately implanting deep junction NWELLs, drift region of low doping concentration in neck region is achieved. This alleviates the concentration of the electric field and avoids premature avalanche breakdown around the bird's beak. Furthermore, introduction of triple RESURF (reduce surface field) technology and optimal device sizes benefit for ultra-low R on,sp (specific on-resistance). Finally, this ISO DB-nLDMOS is experimentally integrated in a 700 V BCD process platform. Testing results show that proposed device achieves 780-V BV ds , 10.4-Ω·mm2 R on,sp and 20-V floating voltage of source electrode.

Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 V/mum in the conventional devices on p-SOI layer to 27 V/mum, resulting in enhancement of the BOX electric field EI from 30 to 82 V/mum. Moreover, holes located between the depleted n-islands help to increase EI as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC.

Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.

An ultra-low specific on-resistance (Ron, sp) high voltage trench SOI LDMOS based on the enhanced bulk field (ENBULF) concept is proposed. The key feature of this new device is heavily doped N/P pillars parallel to the trench oxide layer. The bulk electric field of the trench LDMOS is enhanced both in the dielectric and the silicon layer by using the N/P pillars. Firstly, the highly doped N/P pillars introduce two new electric field peaks in the bulk of the drift region, which enhances the bulk electric fields both under the drain and source. Secondly, the additional electric field of the trench oxide layer is produced by N/P pillars, leading to a shrink of the drift area. Thirdly, the enhanced dielectric layer field (ENDIF) effect of the BOX layer occurs self-adaptively with different thicknesses of the BOX layer. Combining the trench and SJ technologies, the cell pitch is reduced and the optimized doping concentration of the drift region is increased. The Ron,sp is therefore reduced efficiently. The 2-D analytical model of the ENBULF LDMOS is developed to guide the design of the novel device. Based on the model and the simulation, the ENBULF LDMOS exhibits a offstate BV of 684 V and a Ron, sp of 48.5 mΩ·cm2. The new device breaks through the silicon limit in a wide applied voltage levels.

Super junction (SJ) concept is attractive for power devices because of its advantage for improving the tradeoff between the breakdown voltage (BV) and the on resistance (R on ). It is an acknowledged wish to apply the SJ concept to LDMOS for the power integrated circuits (PICs). However, the conventional SJ LDMOS is no practical due to the influence of the fabrication process, charge imbalance, and junction termination, etc. This paper introduces the key technologies for the SJ LDMOS based on our researched SJ device named SLOP (Surface Low On-resistance Path) LDMOS, aiming to offer applicable lateral SJ device for the PICs.

Lateral Double Diffusion MOSFET is widely used due to its excellent properties. However, the contradictory between on-resistance and breakdown voltage (BV) is proved to be the technical bottleneck of optimizing power devices. On one hand, technologies such as REduce SURface Filed (RESURF), Field Plate and Variation of Lateral Doping are applied to enhance the breakdown characteristics of power devices. On the other hand, due to the limits of silicon material, to reach a higher breakdown voltage, the on-resistance must be set higher. The proposed structure, comparing with conventional structure, exhibits a higher breakdown voltage property while keeping the on-resistance invariant.

We investigated the impact of field plate of PLDMOS in thick film SOI with due consideration to gate field which is connected to gate electrode. SOI PLDMOS is employed in the level shifters and multi-output stage in scan driver for PDP. We have simulated the current capability, the saturate current of gate field plate(GFP) structure has obtained about 30% larger than source field plate(SFP), and has better thermal effects. GFP structure in our fabricated IC is experimentally realized with the device width of 1200μm, the current drivability can reach 400mA in output stage.

A 300 V thin layer SOI nLDMOS based on reduced surface electric field (RESURF) and multiple field plates (MFP) is proposed in this paper. RESURF principle and MFP technology are adopted to modulate the electric field distribution and improve the breakdown voltage (BV). Device structure parameters are discussed to achieve a trade-off between breakdown voltage and on-resistance. Compared with conventional structures, the achieved 300 V nLDMOS not only owns high BV, but also possesses a simple manufacturing process and a low cost.

Based on the optimization idea of the electric field from the surface to the bulk, this paper summarizes the basic theory and the two types of analytical optimization methods of the super junction (SJ) device. The essential difference between the SJ and the conventional power MOS structure is: the former is the junction-type voltage sustaining layer with the periodic N/P dopings and the later is the resistance-type voltage sustaining layer with the single conductive type. The positive and negative charges satisfying the charge balance are introduced into the SJ voltage sustaining layer, which causes the two-dimensional electric field to realize the optimization from the surface to the bulk. The paper gives the concepts of the charge and potential electric fields, analyzes the non-full depletion and full depletion modes, introduces the mechanism of the transient process and forward biased safe operating area, discusses the equivalent substrate model and the optimized substrate conditions. Finally, the minimum specific on-resistance R on,min optimization methodology is proposed to give the R on,min for a given breakdown voltage V B. R on of the SJ is decreased significantly compared to that of the conventional power MOS with the same V B. The R on -V B relationship changes from the R on∝ V B2.5 to V B1.32 even V B1.03, leading to the SJ as the “milestone in high voltage power MOS device”

A novel HV thin layer SOI technology based on 1.5-µm-thick silicon layer for negative HV power supply has been first proposed. HV field nLDMOS with thick gate oxide, HV pLDMOS with thin gate oxide and LV CMOS are compatible with shallow trench isolation. Gate and source field plates are adopted to improve the breakdown characteristics of HV field nLDMOS since it doesn't meet SOI RESURF criterion. N-field with shallow junction depth is introduced to eliminate channel discontinuity around the “beak” region at the source side of HV field nLDMOS and avoid punch-through breakdown induced by BG effect of HV field nLDMOS. The influences of key parameters on breakdown mechanism are discussed and optimal parameters are obtained to achieve well characteristics of HV field nLDMOS for negative HV power supply. A negative HV switching IC using the proposed thin layer SOI technology shows that both the rise and fall times of the output stages are less than 50 ns under the negative supply voltage of −100 V and the load capacitance of 5000 pF.

A novel partial silicon-on-insulator (PSOI) high-voltage LDMOS is proposed and its breakdown mechanism is investigated numerically and experimentally. The PSOI LDMOS features double-sided charge trenches on the top and bottom interfaces of the buried oxide (BOX) (DTPSOI). In high-voltage blocking state, the charges located in the trenches enhance the electric field strength in the BOX, and a Si window makes the substrate share the vertical voltage drop and modulates the lateral field in the SOI layer. Both increase the blocking voltage (BV). A BV>700V DTPSOI LDMOS is realized on a 8μm-thick SOI layer over the 1.2μm BOX and 1.5μm-deep trench. Moreover, the Si window alleviates the self-heating effect.

Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N+&P+ and a deep P+ are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.

A novel substrate-assisted (SA) RESURF technology aiming at improving off-state breakdown voltage (BV) of PN junction with small curvature radius is proposed and experimentally demonstrated in this paper. The SA RESURF technology not only realizes small curvature radius in the fingertip region, but also reduces electric field concentration in the curved metallurgical junction. Low-doped P-substrate, which increases depletion of the small curvature radius junction and reduces electric field concentration in the curved metallurgical junction, is adopted in the source fingertip region. Owing to the existence of low-doped P-substrate, the abrupt PN junction with small curvature radius is adjusted to low-doped PN junction with large curvature radius. The SA RESURF technology can be widely applied to lateral high voltage devices with small curved junction, especially to lateral super junction devices. A CBSLOP-LDMOS with the proposed SA RESURF technology has been developed. The experimental results show that the CBSLOP-LDMOS exhibits off-state BV of 700 V and specific on-resistance (R on, sp ) of 142 mΩ·cm2.

A SA-LIGBT with N+ diffusion and N-buffer layer in the anode has been described and analyzed. The onset voltage, on-resistance and turn-off speed of the device can be optimized by adjusting the width of P+ diffusion paralleled with N+ diffusion in the anode. A robust SA-LIGBT is optimized and fabricated successfully in a p-type single crystal without epitaxial layer or buried layer. The experimental SA-LIGBT has a breakdown voltage of 787 V, specific on-resistance of 53 mohm·cm2, turn-off time of 310 ns and onset voltage of 1 V. These qualities make it possible to apply the proposed SA-LIGBT in power integrated circuit.

This paper reports a novel Super Junction pLDMOS (SJ-pLDMOS) with charge-balanced SJ region at the surface of Variation Lateral Doping (VLD) drift region. SJ region provides a low on-resistance path in the ON-state and keeps charge balance approximately when the doping concentration of p pillars is slightly higher than that of the n pillars during the OFF-state. A significant reduction of the specific on-resistance for a given Breakdown Voltage (BV) can be achieved by using a high aspect ratio of the SJ pillars. Simulation results show that the SJ-pLDMOS with L d of 35µm exhibits BV of 582V and R on,SP of 210mΩ.cm2, yielding to a power Figure Of Merit (FOM) of 1.6 MW/cm2. These excellent device performances make the proposed SJ-pLDMOS a promising candidate for level shift circuit.

Device simulations are applied to find out the effects of floating island thickness (d F ) and doping concentration (N p+ ) in power floating island MOSFET (FLIMOS). The simulation results show that the specific on-resistance (R on·sp ) increases by enlarging d F while N p+ produce little influence on R on·sp ; When N p+ is low, the breakdown voltage (V br ) improves by enlarging d F ; When N p+ is high, the breakdown voltage (V br ) degrades by enlarging d F .

Reduced Bulk Field (REBULF) technology is used in the design of lateral power devices to improve breakdown voltage. Since this technology was firstly presented in 2006, this technology has gained widespread attention amongst researchers and has shown to offer good performance in a variety of application domains, especially in bulk silicon and SOI. This paper aims to offer a compendious and timely review of the technology and some work of our lab on the application of this technology in bulk silicon and SOI.

A novel high-voltage thin layer SOI technology based on 1-mum-thick silicon layer and 2-mum-thick buried oxide layer for driving color plasma display panels (PDP) has been developed. High-voltage pLDMOS with thick gate oxide, high- voltage nLDMOS, and low-voltage CMOS are compatible with LOCOS isolation. The proposed technology includes two aspects: first, an implantation after field oxide (IFO) technology is developed for achieving shallow junction depth of p-field region to avoid punch-through breakdown induced by back-gate (BG) effect of pLDMOS; second, conforming technology of isolation and oxidation is adopted for forming thick gate oxide of high-voltage pLDMOS, field oxide isolation of low-voltage CMOS, and full dielectric isolation between high-voltage and low-voltage CMOS simultaneously without additional mask and process. Compared with conventional technology of junction or trench isolation, the new high-voltage thin layer SOI technology achieves better process compatibility with lower process complexity and lower parasitic capacitance. A PDP data driver IC using the developed technology shows that the rise and fall times of the output stages are about 230 ns and 160 ns respectively under the supply voltage of 80 V and load capacitance of 50 pF.

The two structures of over 650V MR & MR SLMFFP double RESURF LDMOSs with HVI are experimentally realized using SPSM BCD process for high side gate drive IC. The experimental results, coincident with the three-dimensional simulations, show that the breakdown voltage of LDMOS will increase by reducing the width of HVI metal line. The breakdown voltages of the MR double RESURF LDMOS are 670V, 760V, 990V when the widths of HVI metal lines are 20 mum, 5 mum, 0 mum, respectively. The breakdown voltages of the MR SLMFFP double RESURF LDMOS are 700V, 920V when the widths of HVI metal lines are 15 mum, 0 mum, respectively. An experimental half bridge gate drive IC is also successfully implemented, using the MR double RESURF LDMOS with HVI. As a result, the two proposed high voltage structures can be used in level shifting and HVJT for AC260V, without thick oxide and additional conductive layer

A novel high concentration linear variable doping interface thin silicon layer (TSL) silicon-on-insulator (SOI) super junction (SJ) LDMOS is proposed. The design of the linear variable doping can deplete the high drift concentration. The proposed structure uses a TSL to achieve charge balance and eliminate substrate-assisted depletion effect. The dielectric electric field (EI) and the breakdown voltage (BV) of the TSL SOI SJ are 530 V/μm and 552 V with 30 µm length drift region and 1 µm-thick dielectric layer, respectively, and the specific on-resistance (Ron, sp) is 0.03403 Ω·cm2 and FOM (FOM=BV2/Ron,sp) is 8.95 MW/cm2, when gate voltage is 5 V.

A low turnoff loss snapback-free reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with a novel collector structure is demonstrated. The n-collector is partially enclosed by a floating p-layer (p-float) which acts as a barrier for electrons at low current in the forward conduction state and contributes to the snapback-free forward conduction characteristics. The p-float makes the proposed device feature double n-p-n electron extraction paths, the n-drift/p- float/n-collector (n-p-nl, n-drift is emitter) and the n-buffer/p-float/ n-collector (n-p-n2, n-buffer is emitter), both of which can be activated during turnoff. As numerical simulations show, the two n-p-n extraction paths, especially n-p-n2 which is more effective than n-p-nl, are favourable to the ultra-low turnoff loss.

A novel concept of SOI BG REBULF (back-gate reduced bulk field), which breaks through the limitation of vertical breakdown voltage of lateral high-voltage SOI transistors, is proposed. The mechanism of the improved breakdown behaviour is the reduction of bulk electric field in silicon due to field-modulated effect of the interface charges induced by the back-gate voltage. The impact of the back-gate bias on the breakdown behaviour of over 600 V SOI LDMOS transistors is discussed. When the back-gate bias is 330 V,the breakdown voltage of the BG REBULF SOI LDMOS is 1020 V, which is 47.8% greater than that of the conventional SOI LDMOS.

A novel deep trench SOI LIGBT with enhanced safe operating area has been proposed. Deep trench gate electrode, reaching buried oxide layer, has been directly introduced for achieving low on-resistance. Heavily doped p+ region at the emitter side, which sandwiches between the n-drift region and n+ emitter region, is provided as holes bypassing path for ensuring enhanced forward biased safe operating area. Some of holes will flow from the n-drift to the p+ emitter without flowing through the pwell layer directly. On the other hand, the portion of the n-drift region which underlies the pwell is fully depleted at a relatively low voltage, thus preventing the voltage across the trench gate oxide from becoming too high and causing less reliable and stable problems. This JFET pinch-off effect keeps any hot-carrier injection (HCI) away from the sensitive gate oxide, providing HCI performance far superior to conventional LIGBT devices.

A compact current-mode boost converter for battery-operated portable devices is presented in this paper. With the help of depletion-mode MOSFET, the chip's volume reduces and input voltage extends from 2.5V to 10V. Using a 0.5µm BCD process, the maximum efficiency of this converter can reach 90% at fixed frequency 1.4MHz. In addition, a single input error amplifier and dead-time control circuit for this design are proposed in the paper. The simulation results and measures verify the function of the proposed structure.

A novel NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V half bridge gate drive IC with the NFFP HVI structure is experimentally realized by using a thin epitaxial high voltage BCD process. Compared with the conventional MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The experimental high side offset voltage of the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.