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A novel odd-even column-level passive sample and column-shared active readout structure is proposed to realise a high speed, low power and low noise readout integrated circuit (ROIC). This structure reduces the number of operational amplifiers (OPAs) in each column and decreases the power consumption of the column capacitive transimpedance amplifier (CTIA) and output buffer. Compared to the traditional design for medium-scale array ROIC, power consumption of a single column is reduced by 80%. A 320 × 320 array ROIC has been designed for indium antimonide (InSb) cooled infrared detector using the novel structure. The chip is fabricated in the 0.35 μm CMOS process. The total power consumption is

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35µm CMOS technology. It occupies an area of 2.113i?0.81mm2. Measurement results show that the proposed channel can process up to 1MHz counting rate and provide a conversion gain of about 170mV/fC at a power dissipation of 330µW with a 3.3V power supply. Ac-coupled to a silicon PIN detector, it successfully detects s-rays.

A two-stage charge sensitive amplifier architecture suitable for semiconductor radiation detector with large capacitance is proposed. The integration capacitor of the first stage can be made large to reduce gain sensibility to detector capacitance without any stability problem. Each stage uses a self-biased MOS transistor to discharge the integration capacitor. The self-bias circuit tracks process, temperature and supply voltage variations to make a relatively constant feedback resistor. This improves the gain linearity of the charge sensitive amplifier and the uniformity of multi-channel front-end electronics. The feasibility of the proposed circuit is verified by comparing the simulation results with the conventional one-stage charge sensitive amplifier and a two-stage structure with fixed-gate-voltage reset transistor. A prototype of 16-channel front-end circuit for electron collection designed in a 0.35μm CMOS technology has been measured. The area is 2.5×1.54mm2 with 42 pads and the power dissipation is 60mW with power supplies of 2V and 5V.

A 14-bit Column-level ADC for Infrared Focal Plane Array (IRFPA) is proposed in this paper. Correlated switch structure is designed, which helps to cancel the offset generated by injected charge and then achieves accurate sampling and holding. Odd-even structure is realized to make longer converting time after sampling. Comparators with two-stage pre amplifiers use low power supply voltages, which ensures low power operation, as well as low noise. Conversion accuracy of the ADC circuit can reach 14-bit. The structure is used for a 640×512 array.

A programmable readout circuit for capacitive accelerometer is presented. The inequality of initial capacitance of sensor's differential capacitor pair is properly compensated. The gain of CSA and the cut-off frequency of LPF are both adjustable. To lower noises, amplifier of CSA is carefully designed. Its equivalent input noise density is 12.7nV/ √ Hz. A rail-to-rail buffer is chosen to enlarge the measurement range. EEPROM instead of pads is exploited, which saves about 33 percent of the layout area.

A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5 ?m CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5 mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900 e. The power dissipation without the output buffer is about 2.6 mW.

A 12-bit 20 MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5 ?m CMOS technology, the ADC dissipates 65 mw from a 5 V supply, and achieves a peak SNDR of 70.1 dB with a 1 MHz full-scale sine input at 20 MS/s.

A 10-bit 80 MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5 um technology, the ADC dissipates 210 mw of power from a 5 v supply, and achieves a peak SNDR of 56 dB at 80 Ms/s.

This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.

A full parasitic capacitance model of diode-class ESD structures is presented in this paper, including not only the reversed-bias capacitance model in the circuit normal operation but the forward-bias capacitance model under the ESD stress. This model successfully calculates the ESD-induced capacitances which degrade the high-speed mix-signal and RF IC performances, and also deals with the puzzle why diode-class structures have a low discharge level with a small turn-on resistance. And a novel parameter CESDV, which is named as the parasitic capacitance unit kV ESD level for the ESD device, is also proposed. The experimental results imply that the MOS-bounded diode has a CESDV about 15fF/kV, far smaller than the normal diode about 30fF/kV. It is shown that the MOS-bounded diode is an appropriate choice for the high-speed mix-signal and RF ICs ESD protection.

A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.

In this paper, instead of the traditional experience-based trial-and-error ESD design approach, a novel ESD protection design methodology is proposed, which resolves the costly and time-consuming problems of high-performance ESD protection development in deep-submicron CMOS technology. And this novel design method is conducted and verified in a 0.5-mum CMOS technology to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be great than 4.5kV. To effectively improve latchup free capability, latchup prevention design is also discussed

A new structure of low-noise CMOS differential amplifier has been presented in this paper. The structure is mainly based on a load of common-gate MOSFETs with resistances in series at sources (CG-R load), which does not increase complication of the circuit. This structure decreases 1/f noise of the load by a (1 + g/sub m2/R) /sup 2/ coefficient, while keeps the voltage gain high. The simulation result for the given example reveals an average reduction of 90% for load noise at low frequencies, compared with current-mirror load (CM load).

A design model is proposed to exactly simulate operating principles of gate-coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor C/sub n/ and coupling resistor R/sub n/ can be calculated to improve the efficiency of GCNMOS ESD protection circuit.

An op-amp with a push-pull output stage for infrared focal plane array (IRFPA) readout integrated circuit (ROIC) is described in this paper. It works in the class AB mode with little die area. The op-amp is simulated by the SMIC 0.35-/spl mu/m CMOS process. The circuit is designed to operate from a single 5 V power and drive a capacitive load of 15 pF. The unity gain-bandwidth (GBW) is 30 MHz. the rising slew rate (SR) 34 V/s. and the falling slew rate (SR-) 39 V/s. The common-mode input and the output swing are almost 5 V.

Design of CMOS high-speed self-regulating voltage-controlled oscillator (HSSR VCO) using negative skewed delay scheme is presented in this paper. With a SMIC standard logic 0.18-/spl mu/ 1.8V CMOS process, the simulation results show that the HSSR VCO can work at 2.2 GHz with good linearity in frequency-voltage space as over an acceptable tuning range as well as a built-in compensation for the delay variation caused by supply fluctuation.

This paper presents a precise compensated bandgap reference without resistors. This bandgap reference uses an improved voltage-transfer unit instead of resistors. A current proportional to T/sup /spl alpha// (/spl alpha/ is a constant) is produced to compensate for the higher order of the V/sub EB/. This bandgap reference is based on 0.5/spl mu/m n-well CMOS technology. The supply voltage is 5V, working from -10/spl deg/C to 90/spl deg/C, the effective temperature coefficient of the output voltage is only 7 ppm//spl deg/C, and the maximum power dissipation is 0.76mW.

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.

An improved low power CMOS snapshot readout structure called OESCA (Odd-Even Snapshot Charge Amplifier) for focal plane array (FPA) is presented in this paper. Using two low power charge amplifiers as column readout circuit (one is for the odd-row readout and the other is for the even-row), this structure not only can eliminate the influence of column bus parasitic capacitance, but also can save 15% power dissipation of the column readout stage. The pixel circuit includes only three NMOSFETs. Thus, it is very suitable for large-format small-pixel lower-power readout circuit. An experimental 64/spl times/64 OESCA chip has been fabricated with 1.2-/spl mu/m Double-Poly Double-Metal (DPDM) n-well CMOS technology. The charge handling capacity is 10.37 pC with pixel size 50/spl times/50 /spl mu/m/sup 2/. A description of the readout circuit structure, pixel circuit, operation principle is given in detail. Both excellent simulation results and experimental results of the fabricated OESCA readout chip are presented.