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Desire to integrate electronic devices more closely into the everyday life of the consumer led to the emergence of flexible devices, which can conform to any shape surface. These flexible devices are lighter, thinner, and more resilient than their rigid counterparts. Since consumers these days are heavily concerned about the visual look of any product along with its technological features, the flexible devices also pave the way for innovation and creativity from the aesthetic point of view. As more and more electronics including wearable devices and displays are shifting towards the flexible regime, their basic components like sensors and integrated circuits are also required to be flexible and conformal. This paper reviews the development and evolution of several types of flexible MEMS sensors, accelerometers, and energy harvesters from the design, fabrication, and performance perspective.

We investigated the effect of channel hot carrier (CHC) stressing on the creation of gate oxide defect centers causing random telegraph signals (RTSs) in pMOSFETs. To identify these stress-induced hole traps in the oxide and fully characterize their trapping properties, variable temperature RTS measurements were performed from room temperature down to 215 K and repeated after each stressing interval, up to 1200 s. The trapping properties of the stress-induced defect sites and those present before stress are quantified, including the hole capture and emission activation energies, structural relaxation in the oxide network due to trapping/detrapping, and entropy change as well as the energy level and position of the trap in the oxide. Based on this information, disassociated III-Si and hydrogen bridge defects are identified as the hole trapping centers in SiO2. Difference was observed between the process- and stress-induced traps in the entropy change upon hole emission from the oxide trap to Si channel (electron capture from the Si valence band), implying the possibility of stress-induced structural defects being different than the native ones.

Although it is the worst degradation mechanism, the effect of channel hot carrier (CHC) stressing on random telegraph signals (RTS) has not been given enough attention in pMOSFETs. We report on the effect of CHC stressing on different RTS trap parameters namely screened scattering coefficient which controls the amount of charge carrier mobility fluctuations due to remote Coulomb scattering by the trap, RTS fluctuation amplitude, average capture time and capture cross-section. The generation of positive fixed oxide charge with stressing influences the screened Coulomb scattering of the channel carriers and therefore their mobility, in addition to the commonly accepted self-screening of the channel carriers. The two-dimensional mobility fluctuations model is adopted for analyzing the CHC effect on pMOSFETs. The comparison between theoretically and experimentally obtained screened scattering coefficients points toward the impact of the newly generated positive fixed oxide charge due to stressing. The decrease of the screened scattering coefficient results in increased RTS amplitude and decreased contribution of mobility fluctuations to RTS amplitude. Capture time and capture cross-section also change as the capture cross-section pre-factor has been impacted by the reduction of relaxation energy with stressing.

In recent years, material printing on flexible and disposable substrates has received substantial interest for realizing low cost electronic and sensing systems on large-areas. As a result, new methods such as printing and additive manufacturing, etc. have received significant attention to develop a wide range of easily deployable systems such as displays, sensors, and RFID smart tags. The technologies developed for silicon-based planar electronics and solid-state sensors is also being repurposed to meet the demands in the emerging field of flexible and printed sensors. This trend will continue as all market indicators point towards significant growth in this area. The exponential growth in flexible, printed and disposable sensor technology, the development of novel printable and solution processable nanomaterials, and the development of novel printing techniques have brought about a new wave of novel printed sensor technologies and applications. Considering this growth, it became necessary to provide a forum to discuss latest developments in the field and to bring together academia and industry to lay the future roadmap. The IEEE International Conference on Flexible and Printable Sensors and Systems (IEEE FLEPS) aims to be such a forum. The 2019 conference was the first edition, started by IEEE Sensors Council, with an aim to be a premier conference in the world. The high standards of the conference will be ensured by the steering committee and the track chairs formed by world-leading experts in the field.

We report on the investigation of random telegraph signals (RTSs) in pMOSFETs at variable temperatures to identify and characterize the hole traps residing at the oxide–semiconductor interface. Attractive center defects as well as a repulsive center defect are identified with trap location, capture cross section, remote Coulomb scattering coefficient, capture barrier energy, trap binding enthalpy, relaxation energy, and change in entropy with hole emission. The attractive centers responsible for RTS were a pair of dissociated three-coordinated silicon (D-III-Si) defects while the repulsive center was identified as a puckered/back-projected oxygen vacancy defect, [a pair of under-coordinated silicon (III-Si) and over-coordinated oxygen (III-O) defects]. Both contain ${E}\gamma ^{\prime }$ centers. This is the first time when such detailed analysis is reported on the hole traps in SiO2 which are responsible for RTS.

A complete investigation of the effect of Li doping on the physical, material, electromechanical and piezoelectric properties of ZnO nanowires (NWs) is presented. Low temperature hydrothermal growth technique is used to grow vertically aligned crystalline ZnO NWs doped with different concentrations of Li. Characterization techniques reveal considerable physical, material and electromechanical property modifications of the ZnO NWs due to the incorporation of Li dopants. Atomic Force Microscope is utilized to apply controlled amount of force on the fabricated NWs to assess their piezoelectric response. More than twenty two-fold improvement is observed in sensitivity due to the combined effect of modifications in NW geometry and piezoelectric properties with the addition of Li. Finite element method simulations were performed to decouple the individual effect of Li doping on the NW size and on the piezoelectric coefficient and to see how much each effect plays a role in the sensitivity improvement. It is estimated that the changes in the material and electromechanical properties alone are responsible for more than seven-fold improvement in the sensitivity. The impact of ‘kick-out’ diffusion mechanism of Li in ZnO is one of the major factors responsible behind this sensitivity improvement. It is also observed that there is an optimum level of Li doping concentration which can lead to the best piezoelectric performance by the ZnO NWs. The novelty of this work lies on the detailed analyses to illustrate the physics and impact of Li dopants in ZnO NW structures from a piezoelectric point of view towards improving their application as a nano-sensing and nano-energy harvesting element.

This paper presents a wafer-level vacuum-packaged z-axis capacitive micro accelerometer fabricated on a flexible polyimide substrate and encapsulated by another polyimide superstrate enabling the flexibility, bendability, and portability of both the device and the package. The novel low-cost and low-temperature encapsulation procedure requires a fewer fabrication steps than the processes, where a thin epitaxial Si layer or a full Si wafer with cavity is used as a superstrate. It also provides a better pliability. The fabricated micro accelerometers demonstrated excellent integrity when bowed down to 2-cm radius of curvature with the sensitivity varying between 139 and 174 fF/g, depending on the design, under the application of ±4 g of acceleration. The resonant frequencies varied from 800 Hz for the largest device to 1050 Hz for the smallest device. The results reported here represent the best performing, wafer-level-packaged flexible micro accelerometers to date.

Surface micro-machined z-axis capacitive accelerometers were designed and fabricated on a flexible polyimide substrate, conformal down to 2 cm radius of curvature with the stresses sustained by all layers well below the yield strength for each material. A novel UV-LIGA fabrication technique was developed to realize a thicker proof-mass (8 μm) compared to the spring (3 μm), thus decoupling the two important parameters: the stiffness and the proof-mass to achieve higher sensitivity. Devices with three different sizes were fabricated with the capability of sustaining under distinct amount of acceleration and tuned to frequencies ranging from 600 Hz to 1100 Hz. The largest device, having the area of 960 μm × 960 μm, showed a sensitivity of 187 fF/g with a SNR (Signal to Noise Ratio) of at least 100 when characterized at its resonance frequency of 800 Hz. The applied acceleration was ±4 g in addition to gravitation.

The design, fabrication, performance simulation and characterization of a piezoelectric zinc oxide (ZnO) nanowire (NW) micro-energy harvester integrated with a microelectromechanical proof-mass/spring system are presented. Low temperature hydrothermal growth of vertically aligned nanowires together with MEMS surface micromachining and UV-LIGA (Lithographie, Galvanoformung, Abformung) processes were utilized to achieve efficient coupling of environmental vibrations to the nano energy harvester. The NWs were connected in series through the membrane/proof-mass structure to achieve higher output voltage. A novel polyimide fill-in and etch-back technique was employed to embed the NW tips into the membrane, such that the NWs were compressed and stretched by the membrane/proof-mass structure in response to the external vibrations. Peak power of 70 pW was observed across an optimal 7 MΩ load when the nano energy harvester was excited with an acceleration of 1.4 g at 40 Hz, corresponding to 22 mW/cm 3 volume-normalized power output. The measured voltage between the top and the bottom electrode was 21.4 mV for this case. The output frequency spectral density with 40 Hz excitation and output voltage with varying excitation frequency are also discussed.

Investigating random telegraph signals (RTS) observed in MOS devices is important for studying the gate-oxide defect characteristics and developing simulation and modeling tools in highly scaled devices. In this paper, we are presenting a comprehensive, variable-temperature, single-to-multitrap scalable RTS model and a simulation tool (RTSSIM) based on the first principles, and supported by experimental data. The physical and electrical characteristics of the actual oxide defects are considered, such as trapping barrier energy, capture cross section, trap-binding enthalpy, entropy change with emission, Coulombic scattering effect, and the trap location. Experimentally obtained time-domain switching data and RTS traces reconstructed by the developed simulation tool are compared for assessing the accuracy of the modeling. In this paper, we identified the trap species responsible for the RTS as an unrelaxed neutral oxygen deficiency center ( $V^{0}$ ODC II) with measured and theoretically verified relaxation energy of 1.11, 1.25, and 0.60 eV. RTSSIM is a tool used to mimic or reproduce a given noise measurement on a particular device. The simulation tool shows over 92% accuracy in replicating the RTS and trap characteristics. The model also represents the first realistic simulation of multilevel RTS.

A novel triboelectric energy harvesting (TEH) and sensing system scaled down to microelectromechanical systems (MEMS) size is presented. The design is structurally optimized for harvesting the highest average power and power density while ensuring the structural robustness. Unlike traditional triboelectric energy harvesters, this design results in a high operating frequency with a wide bandwidth. Adoption of MEMS fabrication techniques including the use of spin-coated Teflon AF rather than a Teflon sheet, adaptation of UV-LIGA (Ultra-Violet Lithographie, Galvanoformung, Abformung) with modifications and implementation of a thick polyimide sacrificial layer make the fabrication process unique. If excited by ±9.33 g external vibration with a frequency of 1.15 kHz, the TEH can generate 0.179 μW average power and 0.597 μW peak power at an optimum resistive load of 256 kΩ. The peak surface power density, volumetric power density and acceleration-normalized volumetric power density reach 3.98 μWcm−2, 2.64 mWcm-3 and 30.3 μWcm-3/g2, respectively. While the surface power density of the presented TEH is moderate, the volumetric power density and acceleration-normalized volumetric power density are quite competitive among the state-of-the-art designs. The TEH also demonstrates a wide operating frequency bandwidth of 920 Hz. If operated as an accelerometer, the device shows a linear sensitivity of 43 mV/g. Although the simulation predicts the optimum operating frequency and load resistance of the system to be at 800 Hz and 10 MΩ, respectively, the experimental results demonstrate these values to be at 1150 Hz and 256 KΩ. A few fabrication anomalies, most notably the notching in the Teflon layer and bowing of the proof-mass, are responsible for this deviation. In addition, a distortion is observed in the simulated output voltage profile which is not present in the experimental output voltage profile due to the presence of the parasitic capacitance in the experimental circuit. The aforementioned triboelectric energy harvester can have specific applications in the sensor and actuator systems in the aircraft industry as well as in the automobile industry, micro-robotic systems, prosthetic systems, and sensor nodes in the internet of things (IoT) due to its operating frequency and bandwidth range.

The effect of channel hot carrier stress has been investigated in pMOSFETs with respect to channel hole trapping by the gate oxide traps and the resultant Random Telegraph Signals (RTS) observed at the output. Process- and stress- induced oxide traps have been identified through RTS measurements. These traps are believed to be E′ centers, acting as hole-attractive or repulsive centers, causing RTS through correlated carrier number and mobility fluctuations. Generation of E′ centers as well as activation of the passivated oxide defects as a result of stress are thought to be the reasons behind observing the stress-induced RTS. Two of the observed defects: one process-induced and one stress-induced trap have disappeared and reappeared randomly with stress. We report the reaction of the defects with hydrogen to be responsible for the volatile nature of the traps. Hydrogen is either bound to the Si/SiO2 interface or trapped at the oxide defects. Applying the stress releases these hydrogen species, which then drift towards the gate through the oxide layer and react with the oxide defects to passivate them. Reaction with another hydrogen de-passivates the defect releasing H2. This is the first article that reports hydrogen to deactivate and reactivate oxide traps responsible for RTS.

The fabrication and characterization of micromachined piezoresistive absolute pressure sensors in a flexible substrate is presented. A suspended aluminum oxide diaphragm containing nichrome (Ni-80%/Cr-20%) piezoresistive sensors backed by a vacuum cavity was utilized to form the sensor. The piezoresistors were placed in a half-Wheatstone bridge geometry to provide a linear response and thermal stability. The average value of the gauge factor of nichrome was measured to be 1.95. The average normalized Hooge coefficient $\text{K}_{1/f}$ was found to be $4.64\times 10^{-11}$ for the nichrome piezoresistors. The pressure sensors displayed an average sensitivity of 1.25 nV/Pa and average value of noise equivalent pressure (NEPr) of 7.44 kPa in the bandwidth of 1–10 Hz in the 1/ $f$ -noise limited regime. In the Johnson noise-limited regime, the NEPr was found to be 10 Pa in a 1-Hz bandwidth. [2014-0028]

The physical origin of majority charge carrier fluctuations in the SiO2 interface of Si at accumulation has been investigated and analyzed for differently processed and voltage-rated reduced surface field (RESURF), lateral-double-diffused MOS (LDMOS) transistors. Surface carrier mobility fluctuation due to remote Coulomb scattering by the trapped charge in the gate oxide is identified as the dominant physical mechanism for LDMOS 1/f noise irrespective of process technologies. A significant contribution to the measured noise has been noted from the surface majority carrier mobility fluctuation due to trapped charge at the accumulation region of the extended drain region, dominant over other sources including the surface minority charge carrier fluctuations in the channel. Active oxide trap density was characterized spatially and for the first time up to ∼0.4 eV above the conduction band-edge of Si. The interface trap density in the unstressed devices (∼8 × 106 cm−2) increased more than an order of magnitude (∼1 × 108 cm−2) after the devices were stressed for 10,000 sec at their individual worst drain current and on-resistance degradation conditions. The extracted Si/SiO2 interface trap density above the silicon conduction band edge was found to be several orders of magnitude lower than that reported for silicon mid-gap energies, even after stressing. Since the traps near the quasi-Fermi level for electrons are active in trapping–detrapping, and the Fermi level is energetically positioned above the conduction band edge of Si in the investigated devices as compared to the previously reported observations, the lower trap density obtained here is an indication for reversal of the well-known exponential trap energy distribution beyond the conduction band-edge of Si. These findings shift the focus from the channel to the gate overlap section of the extended drain and the quality of the Si/SiO2 interface in that region.

Flexible, bendable tactile pressure sensors are developed with crystalline ZnO nanorods as a robotic skin or as part of a multimodal sensing garment. The sensors are arranged in addressable arrays for detection of spatial tactile pressure variation with a resolution of 1 mm or better. The sensors are fully conformable to nonplanar surfaces. A low-temperature hydrothermal process in conjunction with thermal nanoimprint lithography is demonstrated to achieve ordered growth of ZnO nanorods placed vertically on the flexible substrate. The nanorods are fully packaged in inert polyimide for protection against dust, moisture, and mechanical shock. The sensor response to applied pressure is observed to be nearly linear and with negligible hysteresis. A peak sensitivity of 21.2 μV/kPa has been observed for tactile pressure in the 10-200 kPa range.

A nanoelectromechanical vibrational energy harvester is reported based on a ZnO nanorod array coupled to a microelectromechanical mass-spring system. A carpet of vertically aligned crystalline zinc oxide nanorods grown using a low temperature process was characterized to determine their piezoelectric response to mechanical excitation. An atomic force microscope was operated in the force spectroscopy mode to probe ZnO nanorods applying a force in the µN range. In contrast to previously published reports using lateral tip motion (C-AFM), the motion of the AFM tip in our experiment was perpendicular to the plane of the nanorods, which closely mimics the operation of the bulk-micromachined NEMS energy harvester. Voltage pulses with amplitudes ranging from hundreds of µV to few mV were observed. The novelty of this work lies in the integration of the ZnO NEMS and Si-MEMS structures, the use of nanoimprint lithography to achieve periodic, vertical placement of the ZnO nanorods, and the demonstration of piezoelectric voltage generation through low-temperature processed ZnO nanorod carpet.

MEMS force sensors embedded in flexible polyimide substrates are reported, motivated by the need to monitor force and pressure on nonplanar surfaces for structural health monitoring. Details of the fabrication, measured preliminary results, and figures of merit are described. The sensors showed an average piezoresistive gauge factor of 1.75. The average value of normalized Hooge noise coefficient K1/f was found to be 1.89×10-10. The sensitivity was measured to the range from 0.266 to 2.248 V/N with an average sensitivity of 1.25 V/N. The noise equivalent force was calculated to the range from 8.83 to 46.56 μN with an average value of 20.47 μN for the force sensors in a noise frequency bandwidth from 1 to 8 Hz.

Piezoresistive NiCr tactile sensors have been developed on surface micromachined aluminum oxide membranes, embedded between two polyimide layers, i.e., one serving as a substrate, another as a superstrate. A novel method to bond a flexible superstrate polyimide layer onto a microelectromechanical system tactile sensor array is presented. The piezoresistors were connected in a half-Wheatstone bridge configuration to minimize the effects of thermal drift. Three different types of sensor designs were fabricated and characterized to obtain the nichrome thin-film gauge factor. The experimental results were compared with those simulated for the same conditions of membrane deflection. The gauge factors range between 2.2 and 7.9 for sensors with a superstrate and between 1.5 and 3.2 without a superstrate.

A physics-based model has been implemented to describe the low-frequency noise behavior in differently processed reduced-surface-field lateral double-diffused MOS devices. The developed model is based upon the correlated carrier number and the mobility fluctuation theory known as the unified model but has been modified to account for the fluctuations in the extended drain and the channel. Unlike the unified 1/f noise model, nonuniform trap distribution has been taken into account with respect to position in the gate oxide and band-gap energy. The effect of stress on dc and noise characteristics has been investigated. Individual resistance and noise components in the channel and in the extended drain regions under the gate and field oxides are evaluated as a function of stress duration. The model is experimentally verified to identify the physical mechanisms for degradation due to stressing.

This paper presents the fabrication and measured performance of temperature sensors embedded in flexible polyimide substrates. The sensing material used for the temperature sensor was undoped amorphous silicon which was fabricated on a 35-m-thick layer of polyimide that serves as the flexible substrate. Another flexible polyimide superstrate layer of 35-40 m was spin-coated on top of the sensors to make sure the temperature sensors lie on a zero stress plane. The temperature coefficient of resistance was measured over the temperature range of 200- 360 K. The maximum temperature coefficient of resistance at 30 C was measured to be 0.0288 K-1. The effect of the flicker noise and voltage dependence of the voltage noise power spectral density exhibited by the sensor was evaluated. The normalized flicker noise coefficient was found to be 1.2 × 10-11.

Capacitive accelerometers were designed, fabricated and characterized on Si and flexible polyimide substrates with sensitivities ranging between 8.9-23 fF/g and 2.5-9.2 fF/g for z-axis and lateral axes, respectively. UV-LIGA process in conjunction with Ni electroplating was utilized to form the proof mass. Measured sensitivities on the flexible accelerometers were higher than the predictions of the simulations, ranging between 22-27 fF/g in the z axis and 12-18 fF/g in the lateral axes, respectively.

Nanocrystalline piezoresistive polysilicon films were obtained at low temperatures by aluminum-induced crystallization (AIC). The films exhibited granular structure with good polycrystalline properties. A piezoresistive pressure sensor was fabricated on a polyimide substrate, in a Wheatstone bridge configuration comprising two passive resistors and two active piezoresistors made of polysilicon films obtained by AIC. The resistors showed linear I-V characteristics with typical resistance values between 15 and 30 kΩ . Atomic force microscopy was used in contact mode to study the response of the pressure sensor with applied pressure in the 2-19 kPa range. For the higher range of 450 kPa-2 MPa, a load-cell with a nanopositioner was utilized. The pressure-sensor sensitivity was measured to be 41.12 and 5.02 mV/MPa, respectively, for these ranges, when the Wheatstone bridge was bias at 1 V.

For specific RF applications, where the use of MEMS is highly attractive, cost-effective reliable packaging is one of the primary barriers to commercialization. Many RF MEMS devices require a hermetic or vacuum operation environment. This paper presents a post-CMOS-compatible method for vacuum packaging of RF MEMS devices by growing an encapsulation layer during the device fabrication. The resulting MEMS devices are surrounded by a vacuum cavity and can then be placed in a conventional low-cost circuit package. This is a low-temperature area-efficient device-level encapsulation for MEMS devices. RF MEMS resonators in a fixed-fixed configuration were used as the test bed since their quality factor can be used as a measure of the package quality. The encapsulation process is based on a double-sacrificial-layer surface micromachining technique, which is used to create a cavity under and above the resonator. Polyimide was used as the sacrificial layer, followed by the deposition of a packaging layer with trench cuts, which facilitate the sacrificial layer removal. The trench cuts were then sealed at a low pressure, forming a cavity around the device at the sealant layer deposition pressure. Extensive RF characterization and reliability tests were performed on the packaged resonators.

Understanding and minimization of low-frequency noise (LFN) originating from high- k (HK) gate dielectrics in new generation MOSFETs are of critical importance to applications in RF, analog, and digital circuits. To understand the effect of stress conditions on noise, nMOSFETs were subjected to accelerated hot-carrier stress (HCS) and positive constant-voltage stress (CVS). The additional LFN introduced through stressing was evaluated on nMOSFETs with TiN metal gate and HfSiON gate dielectric. Nitridation of HfSiO gate-dielectric MOSFETs was achieved by either a high-temperature NH3 anneal or a lower temperature plasma anneal. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties, and LFN was studied. Worst degradation conditions, i.e., Vg = Vd, were used for HCS, whereas for CVS, the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Plasma-nitrided devices showed less increase in their noise in the linear operation region than the thermally nitrided devices. This difference in noise behavior is attributed to the nitrogen profile across the HK/Si interface and in the bulk of the HK oxide caused by different nitridation techniques. The dielectric defect profile resultant from different annealing techniques was consistent with the spectral form of the observed drain-voltage LFN.

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high- k ), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high- k /interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high- k /interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C–V measurements were performed in the 78–350 K temperature range on TaSiN/HfO 2 n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO 2 by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO 2 resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high- k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1–100 Hz frequency range at temperatures of 78–350 K for both gate stacks.

A physics-based low frequency noise model has been developed for MOSFET devices with nitrided high- κ gate dielectric materials. The new model is built upon the correlated carrier number and surface mobility fluctuations theory, where the original Unified Model was modified to take into account the multilayered structure of the high- κ gate dielectrics, and the resultant charge carrier tunneling process in terms of a two-step cascaded barrier instead of a single step barrier. The new model eliminates the discrepancies previously reported for the dielectric trap density values extracted from noise data using the original Unified Model for flicker noise. The dielectric trap density, typically taken as an average or spatially uniform in the dielectric and constant with respect to energy, is replaced here with an exponential expression dependent on the band-gap energy along with a spatial distribution of the traps in the high- κ layer. Thus, due to the energy dependence of the trap density, bending of the energy bands induces an additional non-uniformity in the spatial trap distribution. Implementation of this expression also provides the much needed flexibility in simulating realistic trap profiles in high- κ materials. Here, MOSFETs with nitrided dielectrics were considered for the noise experiments, as nitridation presents many advantages for the electrical and thermal characteristics of the gate insulator. Variable temperature low frequency noise and mobility measurements have been performed on MOSFETs with nitrided high- κ dielectric. Phonon scattering was found to have a profound effect on the mobility behavior, but no consequence on the low frequency noise characteristics. The low frequency noise data obtained on devices with different interfacial layer thicknesses and different regions of transistor operation was successfully compared with the predictions of the newly developed Multi Stack Unified Noise (MSUN) Model over a temperature range of 172–300 K.

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO2 gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO2 devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high-k stacks but higher than that for the poly-Si SiO2 system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.

This paper reports on the design, fabrication, and characterization of device-level vacuum-packaged microbolometers on rigid Si wafers and flexible polyimide substrates. Semiconducting yttrium barium copper oxide (commonly, referred to as YBCO) serves as the bolometric material. Operating micromachined bolometers in vacuum reduces the thermal conductance G(th) from the detector to the substrate. If flexibility of the substrate is not to be sacrificed, then the vacuum packaging needs to be done at the device level. Here, the microbolometers are fabricated on a silicon nitride support membrane, isolated from the substrate using surface micromachining. Suitable materials as well as various dimensions in the vacuum cavity are determined using finite-element method (FEM)-based CoventorWARE. A vacuum cavity made of Al2O3 has been designed. The thermal conductance G(th) of bolometers with the geometry implemented in this work is the same for devices on rigid and flexible substrates. The theoretical value of G(th) was calculated to be 4.0 x 10(-6) W/K for devices operating in vacuum and 1.4 x 10(-4) W/K for devices operating at atmospheric pressure. Device-level vacuum-packaged microbolometers on both rigid Si and flexible polyimide substrates have been fabricated and characterized for optical and electrical properties. A low thermal conductance of 1.1 x 10(-6) W/K has been measured six months after fabrication, which implies an intact vacuum cavity.

This paper presents design, fabrication and measured performance parameters of micromachined infrared detectors on polyimide substrates. The detectors are of bolometer type made of semiconducting yttrium–barium–copper oxide (YBCO) as the thermometer material and are built on a 40–50m-thick layer of polyimide (PI5878G) that serves as a flexible substrate. A thin film of Si3N4 supports the detectors. Surface micromachining is used to isolate the detectors and the supporting nitride layer from the substrate. Despite being supported by a layer of Si3N4, an average thermal conductivity of 5.61 × 10 −7 W/K, comparable to self-supporting devices on flexible substrates has been measured. This opens the possibility of placing such flexible sensors on micromachined membranes, integrated with other functions such as pressure sensing to build “Smart Skin.” Roomtemperature responsivity of 7.4 × 10 3 V/W and detectivity of 6.6 × 10 5 cm Hz 1/2 /W were demonstrated on 40m × 40m microbolometers. The effect of substrate heating was also investigated and was found not to cause cross talk between the pixels. If these sensors are to be used as part of multi-functional, flexible sensor systems, device-level vacuum packaging is necessary. This was investigated using computer simulations for structural analysis and found to be feasible. © 2006 Elsevier B.V. All rights reserved.

This paper presents the design, modeling and simulation of micromachined, integrated pressure–thermal sensors on flexible polyimide substrates. Finite element simulations were performed with polycrystalline silicon as the piezoresistor material on a suspended Si3N4 layer. These piezoresistors are connected to each other in a half-bridge Wheatstone configuration using flexible aluminum interconnects. Several different designs of integrated thermal–pressure sensors as well as pressure-only sensors were simulated to compute the sensor figures of merit such as the percentage change in piezoresistance in response to normal pressure, piezoresistor Wheatstone-bridge output voltage for varying skin curvature, bolometric response to broadband infrared radiation, thermal time constant and thermal conductance of the micromachined structures hosting the sensors to the substrate. For a perpendicular uniform pressure application of 50 kPa, a maximum Wheatstone-bridge output of 7.59 mV was computed for 1 V bias, corresponding to a piezoresistance change of 1.52%. When the skin is bent to a curvature of 2.2 mm, a maximum Wheatstone-bridge output voltage of 70 mV was calculated for the case when the sensors are aligned along the axis of bending. Thermal and optical calculations performed on the integrated thermal–pressure sensors showed a thermal time constant as low as 12.8 µs for a 1.9 µm thick silicon nitride membrane layer, with a responsivity of 270 V W−1 to a broad-band infrared radiation. This would be appropriate for applications requiring fast response but not high sensitivity. Integrated sensors on a thinner silicon nitride membrane layer of 0.5 µm, on the other hand, exhibited responsivity as high as 2000 V W−1, with a response time of 626 µs.

In this paper, the effects of different transistor design aspects on the noise behavior of SiGe heterojunction bipolar transistors have been investigated. Selectively implanted collector, although retards the base push-out, does not deteriorate the noise characteristics. Moreover, a higher dopant implant in the extrinsic base region intended for a smaller base resistance does not deteriorate the noise characteristics. While the interface between the SiGe epitaxial and polycrystalline layers does not have any detrimental impact, the emitter-poly overlap significantly influences both the DC and the noise characteristics. Smaller emitter-poly overlap results in an increased non-ideal base current at lower bias voltages and produces appreciable generation–recombination noise. For all the transistors, except for the ones with smaller emitter-poly overlap, the base current noise power spectral density shows a near quadratic dependence on the base current, where the noise is believed to originate mostly from the superposition of the generation–recombination noise in the intrinsic emitter–base junction. The base current noise power spectral density for the transistors with a smaller emitter-poly overlap shows a near linear dependence on the base current, which results from an increased contribution from the trap-assisted tunneling fluctuations of the minority carriers at the surface of the emitter–base junction.

Low-frequency noise measurements and analysis were performed on n-channel MOSFETs with HfSiON as the gate-dielectric material. The role of SiON interfacial-layer thickness was investigated. It was observed that these fluctuations can be described by the unified flicker-noise model that attributes noise to correlated carrier-number/mobility fluctuations due to trapping states in the gate dielectric. The model was modified to include the effect of different gate stack layers on the observed noise. The carrier-number fluctuations were found to dominate over the correlated mobility fluctuations in the measured bias range and more so at the lower gate overdrives. The noise magnitude showed a decrease with increasing SiON interfacial-layer thickness. Furthermore, an inverse-proportionality relationship was revealed between the effective oxide trap density and SiON thickness.

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.

Micromachined infrared sensor arrays have been fabricated on flexible polyimide substrates using a silicon wafer carrier during the fabrication process. These flexible polyimide substrates containing the micromachined infrared sensors were removed from the silicon wafer at the end of fabrication. The fabrication technique utilized surface micromachining of a bridge structure to form the thermal infrared (IR) sensors on flexible substrates. Semiconducting yttrium barium copper oxide YBCO was used as the radiation sensitive material. 1 × 10 sensor arrays of microbolometers were micromachined using a photo-definable polyimide sacrificial layer and characterized before and after removal of the substrate from the Si wafer carrier. The flexible infrared microsensors showed similar performance to microbolometers fabricated on rigid silicon substrates. The YBCO thermistors exhibited a temperature coefficient of resistance (TCR) of ∼−3.4% K−1 near room temperature. Responsivity and detectivity values as high as 6.1 × 104 V/W and 1.2 × 108 cm Hz1/2/W, respectively, were measured in vacuum for a 40 μm × 40 μm microbolometer with 1 μA bias. The lowest observed noise equivalent power was 4.1 × 10−11 W/Hz1/2 while the lowest thermal time constant was 5.7 ms.

This special issue focuses on the sensors and sensing systems having features like flexibility, bendability, conformability, stretchability, and presence over large areas and 3D surfaces. Like conventional sensors, flexible sensors are also used to measure parameters and agents like pH, temperature, humidity, force, gasses, velocity, flow etc. In addition, they possess the ability to bend. This requires special front-end processing techniques compatible with the flexible materials that these sensors are made of. In response to the call for papers for this special issue, 114 manuscripts were received. Of those, 39 were found not to fit to the scope of the special issue and were separated to be handled by the permanent editors of the Journal. The peer review process resulted in 29 innovative manuscripts to be published here submitted from over 45 institutions, with a few trailing manuscripts to be published at a later issue due to time constraints. Of the work presented here, nine papers describe sensors for health and medical applications. Five papers detail sensors for the general fields of environmental and structural health monitoring. Four are on robotic applications. Although majority of the manuscripts focus on a single sensing function such as fluidic flow, force, pH, temperature or presence of a specific gas, four papers present multifunctional flexible sensors.

The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (R/sub S/) were used to investigate the relative contribution of each individual noise source from the base current (S/sub IB/), the collector current (S/sub IC/) and, the internal emitter and base series resistances (S/sub Vr/). When the voltage noise power spectral densities S/sub VC/ and S/sub VB/ were measured across resistances in series with the collector and base, respectively, using a relatively large R/sub S/ (/spl sim/1 M/spl Omega/), S/sub IB/ was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities S/sub VC/ and S/sub VE/ were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low R/sub S/ value, S/sub Vr/ was found to have the dominant noise contribution at higher bias currents. IFO was found to increase S/sub IB/, S/sub IC/, and S/sub Vr/. S/sub IB/ was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas S/sub IC/ was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. S/sub Vr/ was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO.

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.

Uncooled semiconducting YBaCuO infrared microbolometers have been fabricated on a flexible polyimide substrate formed by spin-coating a silicon wafer with a release layer. The wafer was used as a carrier for the flexible substrate during fabrication. The finished microbolometers on the flexible substrate showed a temperature coefficient of resistance (TCR) TCR =(1/R)(dR/dT) of -3.03% K/sup -1/, at room temperature, which is comparable to the TCR values observed for semiconducting YBaCuO microbolometers fabricated directly on Si. In order to provide protection and better mechanical integrity, some of the devices were encapsulated. The microbolometers attained a responsivity and detectivity as high as 3.5/spl times/10/sup 3/ V/W and 1/spl times/10/sup 7/ cm/spl middot/Hz/sup 1/2//W, respectively, at 2.88 /spl mu/A of current bias. The responsivity and detectivity of the encapsulated microbolometers, on the other hand, were 1.6/spl times/10/sup 3/ V/W and 4.9/spl times/10/sup 6/ cm/spl middot/Hz/sup 1/2//W, respectively at 1 /spl mu/A of current bias. Spin-coated liquid polyimide solved two major problems previously encountered with the solid polyimide sheets when used as a flexible substrate. First, flatness of the flexible substrate was maintained with no air bubbles. Second, the thermal expansion of the flexible substrate during the fabrication process due to thermal cycling was minimal. All measurements reported in this paper, were taken prior to releasing the flexible substrate from the Si wafer containing the finished microbolometers.

1/f noise was measured on lateral bipolar PNP transistors over a temperature range of 220

Random telegraph signals (RTS) are two or more level switching events observed at the drain current or voltage of a MOSFET, which originate from the traps at the Si/SiO2 interface through the process of capture and emission of charge carriers. Even though there are several available models for low-frequency noise in MOSFETs today, none of them provide modeling tools for RTS. A model has been developed for RTS at the drain of sub-micron scale MOSFETs. The RTS power spectral density is given in terms of three parameters, which fully characterize the RTS, namely capture time, emission time and RTS amplitude. These three parameters are expressed in the terms of the device physical parameters, biasing conditions and temperature, through seven independent modeling parameters: the trap position, xT and yT, trap energy, ET−ECox, capture cross-section, σ0, trap binding energy, ΔEB, and empirical fitting constants for the screened scattering coefficient, K1 and K2. The model was tested through RTS data obtained on sub-micron LDD n-MOSFETs. Results were compared with the model and fitting parameters were extracted. The trap position xT was found to be 13 A, close to the Si–SiO2 interface compared to the oxide thickness of 50 A. yT is 0.12 μm, indicating the trap is located close to the drain side. The σ0 obtained from the fittings was 7 × 10−20 cm2 at VGS=1.2 V and increased with gate voltage. ΔEB was 0.3 eV. The K1 and K2 values were evaluated to be 3 × 10−13 and −2.5 × 10−16 V s, respectively. The extracted parameters are comparable to the reported values measured on similar devices.

Low-frequency noise in double reduced-surface-field lateral-double-diffused-MOS devices has been measured, and the effect of dc stressing is analyzed. The noise components contributing from the extended drain regions under the gate and field oxides were differentiated from the channel noise by a series of experimental and analytical techniques. The effect of voltage stressing on each noise component was investigated. Trapped-charge carrier fluctuations due to Si/SiO2 interface traps in the overlap region in the extended drain as well as in the channel were found to be the dominant source of noise. The bulk resistance fluctuations in the extended drain region under the field oxide were found to be insignificant. High-voltage stressing caused an increase in the interface traps, thus increasing both the extended drain overlap resistance and the noise.

1/f noise was measured on polysilicon-emitter bipolar n-p-n and p-n-p transistors over a temperature range of 173K

A new generation of microbolometers were designed, fabricated and tested for the NASA CERES (Clouds and the Earth's Radiant Energy System) instrument to measure the radiation flux at the Earth's surface and the radiant energy now within the atmosphere. These detectors are designed to measure the earth radiances in three spectral channels consisting of a short wave channel of 0.3 to 5 /spl mu/m, a wide-band channel of 0.3 to 100 /spl mu/m and a window channel from 8 to 12 /spl mu/m each housing a 1.5 mm x 1.5 mm microbolometers or alternatively 400 /spl mu/m x 400 mm microbolometers in a 1 /spl times/ 4 array of detectors in each of the three wavelength bands, thus yielding a total of 12 channels. The microbolometers were fabricated by radio frequency (RF) magnetron sputtering at ambient temperature, using polyimide sacrificial layers and standard micromachining techniques. A semiconducting YBaCuO thermometer was employed. A double micromirror structure with multiple resonance cavities was designed to achieve a relatively uniform absorption from 0.3 to 100 /spl mu/m wavelength. Surface micromachining techniques in conjunction with a polyimide sacrificial layer were utilized to create a gap underneath the detector and the Si/sub 3/N/sub 4/ bridge layer. The temperature coefficient of resistance was measured to be -2.8%/K. The voltage responsivities were over 10/sup 3/ V/W, detectivities above 10/sup 8/ cm Hz/sup 1/2//W, noise equivalent power less than 4 /spl times/ 10/sup -10/W/Hz/sup 1/2/ and thermal time constant less than 15 ms.

Microbolometer infrared detectors based on semiconducting yttrium-barium-copper-oxide (YBCO) have been fabricated on a 125-/spl mu/m-thick flexible polyimide substrate, Kapton(R). During the fabrication process, the highest temperature reached was 270/spl deg/C, used to cure a polyimide insulation layer. The 60 /spl mu/m/spl times/60 /spl mu/m microbolometers displayed a temperature coefficient of resistance of -3.07%/K at room temperature. The thermal conductivity of the structure was measured to be 4.18/spl times/10/sup -5/ W/K. The bolometer response showed a linear dependence on bias current with a responsivity of 2/spl times/10/sup 3/ V/W and detectivity of 3/spl times/10/sup 7/ cm Hz/sup 1/2//W at 1.13 Hz and 1 /spl mu/A bias.

The author reviews the recent results obtained on the low-frequency noise characteristics of deep-submicron metal-oxide-semiconductor field-effect transistors (MOSFETs). The manuscript covers measurements, analysis and modelling of 1/f noise as well as random telegraph signals (RTS). In addition, techniques are presented where RTS and 1/f noise measurements can be utilised to characterise the oxide traps responsible for these fluctuations, namely the position of the trap in the oxide and along the conduction channel, the trap energy, and the associated screened scattering coefficient. Most of the analysis is based on the classical three-dimensional treatment of charge carrier calculation, although a section is reserved for charge quantisation and its effect on RTS. For noise modelling, an improved physics-based 1/f noise model is presented where the Berkeley short channel IGFET model (BSIM3) has been modified to include the threshold variation along the channel. This model merges into the classical BSIM3 for supermicron devices. The noise models presented in the manuscript are based on data that were obtained on many submicron channel length n- and p-MOSFETs made by different leading manufacturers using different technologies. It is expected that the developed models will be valid for all advanced MOSFETs.

A new micromachined microbolometer array structure is presented that utilizes a self-supporting semiconducting yttrium barium copper oxide (Y-Ba-Cu-O) thin film thermometer. The Y-Ba-Cu-O thermometer is held above the substrate only by the electrode arms without the need of any underlying supporting membrane. This represents a significant improvement in the state-of-the-art for microbolometers by eliminating the thermal mass associated with the supporting membrane. The reduced thermal mass permits lowering the thermal conductance to the substrate to obtain increased responsivity or having a shorter thermal time constant to allow for higher frame rate camera. The simple structure does not suffer from warping problems associated with stress imbalances in multilayer microbolometer structures that utilize a supporting membrane such as Si/sub 3/N/sub 4/. Devices were fabricated by growing Y-Ba-Cu-O films on a conventional polyimide sacrificial layer mesa. Subsequent etching of the sacrificial layer provides the air gap that thermally isolates the microbolometer. Y-Ba-Cu-O possesses a relatively high temperature coefficient of resistance of 3.1%/K at room temperature. The 400-nm-thick Y-Ba-Cu-O film exhibited absorptivity of about 30%. The responsivity and detectivity approached 10/sup 4/ V/W and 10/sup 8/ cm Hz/sup 1/2//W to filtered blackbody infrared (IR) radiation covering the 2.5 to 13.5 /spl mu/m band. This extrapolates to noise equivalent temperature difference (NETD) less than 100 mK. The micromachining techniques employed are post-complementary metal-oxide-semiconductor (CMOS) compatible, allowing for the fabrication of focal plane arrays for IR cameras.

Random telegraph signals (RTS) have been investigated in the drain to source voltage of Weff×Leff=1.37×0.17 μm2 medium-doped drain (MDD) n-type MOSFETs. The emission (τe) and capture (τc) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τe and τc including the influence of bulk bias (VSB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO2 interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔVDS/VDS) shows a positive dependence on VSB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.

Random telegraph signals (RTS) have been used to characterize oxide traps of W×L=0.97×0.15 μm 2 medium-doped drain n-MOSFETs. RTS have been measured in the linear and saturation regions of operation, both in forward and reverse modes where the drain and source are reversed. The contribution of mobility fluctuations as well as number fluctuations to the amplitude of RTS has been investigated. The scattering coefficient due to screened Coulomb scattering effect is computed from the measured data as a function of channel carrier density. The depth of the position of the trap in the oxide from Si–SiO2 interface is calculated utilizing the dependence of the emission and capture times on the gate voltage. In addition, the position of the trap along the channel with respect to the source is obtained using the difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes. Knowing the location of the trap in the oxide and along the channel, the energy associated with the trap can be extracted accurately from the data. This technique allows one to evaluate the trap energy at the point where the trap is located without any assumptions about the location of the trap or the need for variable temperature measurements. The probed trap was found to be an acceptor type center (repulsive for an n-MOSFET) located at about 27 A deep the oxide, half-way between drain and source with an energy of ECox−ET=3.04 eV, slightly above the conduction band edge.

Medium doped drain n-MOSFET with W eff × L eff = 0.29 × 0.20 μm 2 have been used to investigate complex random telegraph signals (RTS) in the drain to source voltage. Four-level switching events were observed, from which three discrete traps were distinguished. Their behavior was observed in the range of gate-to-source and drain-to-source voltages of 0.5–1.8 V, all in strong inversion. The capture and emission times of each trap were investigated as a function of gate bias as well as drain voltage. Using the mark-space ratio of the switching events, the position of the traps from the Si–SiO 2 interface was calculated to be about 0.43, 0.55 and 0.74 nm. These evaluations were used successfully to determine the trap energy level with respect to oxide conduction band edge. Comparative evaluation of the mobility fluctuations with respect to number fluctuations was done using RTS amplitude. The screened scattering coefficient due to the Coulomb scattering effect was examined with respect to the variation of carrier density in the channel as well as in the drain voltage for all three traps. An influence of one trap on another was observed and found that there is a change of the energy level of 0.06 eV due to this effect.