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This paper proposes a digital logic circuit in the source driver for OLEDoS micro display which uses a novel data signal tree structure with clock gating logic to reduce power consumption. The proposed structure for 4096×4096 (4K) 144 Hz micro displays was verified using a CMOS 110 nm process. The power consumption was reduced by 69.6 % compared to the conventional data signal tree structure, enabling a low‐power design. [ABSTRACT FROM AUTHOR]

The object of this study is models of low-power digital logic circuits. The problem being solved is the effectiveness of the technique for simplifying Boolean functions to obtain optimal structures of logic circuits. A new theorem of a non-standard system of simplification of Boolean functions has been formulated, according to which in order to obtain a minimal function it will suffice to perform all non-redundant operations of simple and/or super-gluing of variables, which ultimately provides a minimal function in the main basis without using an implicant table. Thus, the problem of simplifying Boolean functions to the simplest normal equivalent is solved in one step. The interpretation of the result is that the properties of 2-(n, b)-design combinatorial systems make it possible to reproduce the definition of logical operations of super-gluing variables, to represent logical operations in a different way, and vice versa. This, in turn, ensures the establishment of the locations of equivalent transformations on the binary structure of the truth table and the implication of a systematic procedure for simplifying Boolean functions by an analytical method. Special feature of the results is that unambiguous identification of the locations of equivalent transformations is possible even when different intervals of the Boolean space containing the 2-(n, b)-design systems have common modules. It has been experimentally confirmed that the non-standard system improves the efficiency of simplifying Boolean functions, including partially defined ones, by 200–300 % compared to analogs. In terms of application, a non-standard system for simplifying Boolean functions will ensure the transfer of innovations to material production: from conducting fundamental research, expanding the capabilities of digital component design technology to organizing serial or mass production of novelties. [ABSTRACT FROM AUTHOR]

The exponential growth of the power of modern digital computers is based upon the miniaturization of vast nanoscale arrays of electronic switches, but this will be eventually constrained by fabrication limits and power dissipation. Chemical processes have the potential to scale beyond these limits by performing computations through chemical reactions, yet the lack of well-defined programmability limits their scalability and performance. Here, we present a hybrid digitally programmable chemical array as a probabilistic computational machine that uses chemical oscillators using Belousov-Zhabotinsky reaction partitioned in interconnected cells as a computational substrate. This hybrid architecture performs efficient computation by distributing information between chemical and digital domains together with inbuilt error correction logic. The efficiency is gained by combining digital logic with probabilistic chemical logic based on nearest neighbour interactions and hysteresis effects. We demonstrated the computational capabilities of our hybrid processor by implementing one- and two-dimensional Chemical Cellular Automata demonstrating emergent dynamics of life-like entities called Chemits. Additionally, we demonstrate hybrid probabilistic logic as a viable logic for solving combinatorial optimization problems. Computing platforms based on chemical processes can be an alternative to digital computers in some scenarios but have limited programmability. Here the authors demonstrate a hybrid computing platform combining digital electronics and an oscillatory chemical reaction and demonstrate its computational capabilities. [ABSTRACT FROM AUTHOR]

A parity generator as a combinational logic circuit in digital circuits can generate the parity bit in the transmitter. It is very applicable in digital networking and communications. Also, rather than diodes and transistors, quantum dots will be used in the next-generation circuits. Quantum-dot Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits' functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively. Quantum dot-Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits' functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively. [ABSTRACT FROM AUTHOR]

As an emerging nanodevice, Quantum-dot cellular automata (QCA) is a hopeful candidate for conventional complementary metal oxide semiconductor devices. XOR, one of the most vital gates, occupies a significant positon in digital logic circuits. In order to improve the property performance of XOR, a novel five-input majority gate is put forward first. Then, an efficient XOR employing a NAND-NOR-Inverter (NNI) and the proposed five-input majority voter is realized in the paper. Compared with previous counterparts based on gates, the proposed design requires fewer cells, occupies less area, and consumes less average energy consumption. Specifically, it improves by 11.11% in cell count, 2.11% in area, and 9.51% (1.5Ek) in energy consumption when compared to the state-of-the-art design. The clock delay of the XOR in the article keeps the same with the minimum of them. Additionally, the proposed design has the lowest QCA cost, including area-delay cost, QCA-specific cost, and energy-delay cost. Moreover, the design is coplanar, without any crossing types. All these make it an outstanding design. To demonstrate its practicality, n-bit parity generators using the proposed XOR are implemented. The novel 4-bit parity generator excels in cell count, area, and average energy dissipation, achieving optimization of up to 10.6%, 6.0%, and 38.6% (0.5Ek), respectively, compared to previous optimum values. The significance of these optimization results becomes more pronounced as the bit of parity generators increases, indicating a promising future for constructing complex circuits. [ABSTRACT FROM AUTHOR]

A set of laboratory exercises are presented, which use the video game Minecraft as the environment for teaching combinational digital logic in an introductory electronics lab. Several advantages are noted when students use the virtual Minecraft environment prior to building any real digital circuits. Editor's Note: Looking for new ways to connect with your students or to get your students to connect with each other? If so, Minecraft may be for you! In this paper you'll learn how to use the best-selling video game in history to develop digital electronics activities that teach concepts as simple as basic logic gates or as complicated as the emulation of a whole working computer. [ABSTRACT FROM AUTHOR]

This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme. [ABSTRACT FROM AUTHOR]

There are presented several two and three variable gates of molecular electronics digital computers. Maximal length of these molecular electronics digital logic gates are no more than four nanometers and maximal width 2.5 nm. The results of light induced internal molecular motions in azo-dyes molecules [1-3] have been used for the design of light driven logically controlled (OR, AND, NOR, NAND) molecular machines composed from organic photoactive electron donor dithieno[3,2-b:2',3'-d]- thiophene, tetrathiofulvalene (TTF) or ferrocene molecules and electron accepting 4,5-dinitro-9-(dicyanomethylidene)-fluorene (DN9(CN)2F), tetracyano-indane, and moving azo-benzene fragment. Density functional theory (DFT) B3PW91/6-311G model calculations were performed for the geometry optimization of these molecular electronics logical gates. Applied DFT time dependent (DFT-TD/B3PW91) method and our visualization program give absorption spectra of designed molecular gates and show from which fragments electrons are hopping in various excited states. There are designed set of single supermolecule fluorescencing devices containing OR and AND logic functions. [ABSTRACT FROM AUTHOR]

In today's time more than 70% of the world's population suffer from eye disnormalities leading to the usage of eyewear or spectacles. Integrating profound technologies with daily utilities could serve some of the issues improving and optimizing our lifestyle to the most. One such way is to infuse nanosized chip in eyewear i.e., powered spectacles or shades to detect the location of the spectacles whenever it is necessary. The nanosized chip proposed has features including self-designed Bluetooth operating digital circuit, timer logic, clock generation using astable multivibrator circuit, emergency button, beep alarm and impact sensor. The values of resistance and capacitace is calculated to be 18 K ohm and 47 uF to obtain 1 Hz frequency. An optimal pin placement arrangement is analyzed, and the timing waveform is simulated using Verilog as proof of logical working of the chip. 13 D flipflops have been calculated to refrain from eye related strains. This paper suggests a bottom-up approach and develops the architectural framework of the chip, its working flow, system on chip top-view, digital logic description of each block and its implementation using Verilog hardware description language (HDL). The complexity and computational cost of the designed chip is minimal thus being commercially viable. [ABSTRACT FROM AUTHOR]

[Display omitted] There is an unceasing quest to create novel forms of intelligent active matter that exhibits sensing, energy harvesting, actuating, computing, and communication functionalities. Realizing such capabilities can provide new road maps to autonomous and electronic materials with numerous applications in robotics, human–machine interfacing, micro/nano-electromechanical systems, and flexible electronics. Here, we introduce "mechanical metamaterial electronics (meta-mechanotronics)" as a platform for designing intelligent matter that can sense external stimuli, self-power and process the information to create an integrated closed-loop control system. We achieve these advanced functionalities by fusing mechanical metamaterials, digital electronics and triboelectric nano energy harvesting technologies. Meta-mechanotronic systems use only their constituent components and integrated nanogenerator mechanisms to perform self-powered mechanical–electrical-logic and information storage operations. Thus, they establish a direct interaction mechanism between the external environment and electronics, which is a radically different approach from conventional electrically-controlled units. We demonstrate digital unit cells as building blocks for meta-mechanotronics to perform various self-powered computation functionalities. Analytical models, numerical simulations and experimental studies are performed to design a suite of electronic mechanical metamaterials capable of synthesizing discrete mechanical configurations, performing binary/ternary computations, and realizing digital logic gates, i.e., AND, OR, XOR, NAND, NOR, and XNOR. We demonstrate the capability of the framework by creating self-powered mechanically-responsive data storage devices that can store various ASCII codes. Further discussion is provided on how meta-mechanotronics and the associated circuitry can lead to developing future mechanical metamaterial computers, complementing traditional electronics with electronics made of mechanical metamaterials. [ABSTRACT FROM AUTHOR]

In this paper, a novel design of an all-optical half-adder (HA) based on two two-ring resonators in a two-dimensional square-lattice photonic crystal (PC) structure without nonlinear materials is proposed. The all-optical HA comprises AND and XOR gates where each gate is composed of cross-shaped waveguides and two-ring resonators in a 2D square-lattice PC that are filled with silicon (Si) rods in silica (SiO2). The AND and XOR gates are analyzed and simulated using plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methods. Simulation results show that light guiding inside the device functions as AND and XOR gates. Thus, the proposed device has the potential for use in optical arithmetic logic units for digital computing circuits. The structure comprises an optical AND gate and an optical XOR gate that were designed to work at the C-band spectrum. Results show that there is a clear distinction between logic states 1 and 0 with a narrow power range that leads to a better robust decision on the receiver side for minimized logic errors in the photonic decision circuit. Thus, the proposed HA can be a key component for designing a photonic arithmetic logic unit. [ABSTRACT FROM AUTHOR]

Logisim is a digital logic circuit design and simulation software that is an open source, free of charge, secondary development, installation-free, easy to use and intuitive. This paper examines how Logisim can be used to design the data path and combine it with Verilog for FPGA design of single cycle CPUs. [ABSTRACT FROM AUTHOR]

A number of arithmetic operations and applications use digital logic circuits as their primary building blocks, to operate with high reliability and precision. The multiplier is the core part of most arithmetic designs. The trend of imprecise multiplier has gained visibility in recent years, especially for image processing applications. Most of the multiplier designs use a compressor in the dot product reduction. In recent years, researchers have focused on designing imprecise, or approximate compressor to reduce design complexity while maintaining a low error rate. For higher bit multiplication, the design of a higher-order compressor is required. Using Karnaugh map (K-map) and truth table for approximation is a challenging task for the higher-order compressor. To address this issue, a scalable compressor with reasonable approximation using counter-based comparison methods is designed in this paper. The simulation results used with scalable compressors are compared with the existing 8 × 8 and 16 × 16 multipliers. These approximate circuits show significant improvement in the efficiency of multimedia signal processing, leading to better efficiency in terms of 30% area, 25% power, 20% delay, mean error distance (MED), error distance (ED), and normalized error distance (NED). The proposed method is applied in image multiplications for image contrast enhancement application. The peak signal-to-noise ratio (PSNR) is then determined and compared to other existing work. [ABSTRACT FROM AUTHOR]

Graphene is considered a promising material because of the novel functionalities associated with its outstanding charge transport properties. However, because graphene has no bandgap, its electrical conductivity cannot be controlled as in semiconductors, at present. Although many attempts have been made to achieve a bandgap opening in graphene, a meaningful bandgap opening for p -type field-effect-transistors (FETs) still remains a challenge. In this study, boron-doping in transfer-free monolayer graphene was successfully demonstrated for digital logic devices. Our approach is highly versatile, as it allows the fabrication of p -type single-crystal graphene FETs having a mobility of ∼290 cm2V−1s−1, an on/off ratio of 1.9 × 105, and a subthreshold swing of 70 mVdec−1. The scalability and versatility of this transfer-free approach for the fabrication of p -type graphene FETs pave the way for high-performance p -type graphene-based digital logic circuits. A scalable direct-growth approach to the fabrication of p- type graphene FETs, which manifest cutting-edge performance is demonstrated for the large-scale complementary integration of p -type graphene-based circuit for digital logic device applications. [Display omitted] [ABSTRACT FROM AUTHOR]

A study of GaN for high temperature (HT, up to 500 °C) digital circuits was conducted. A HT-robust GaN-on-Si technology based on enhancement-mode p-GaN-gate AlGaN/GaN high electron mobility transistors (HEMTs) and depletion-mode AlGaN/GaN HEMTs was proposed and used to implement different digital circuit configurations, namely E/D-mode and E/E-mode (E: enhancement, D: depletion). The E/D-mode inverter was found to offer significantly better performance in terms of voltage swing, noise margin, and gain, across temperature and ${V}_{\textit {DD}}$ scaling. As calculated from E/D-mode ring oscillators (ROs) with ${L}_{G}=2\,\,\mu \text{m}$ , a RO exhibited a propagation delay (${t}_{p}$) of < 1.48 ns/stage at 500 °C. The best RO achieved ${t}_{p} < 0.18$ ns/stage at 25 °C. To the best of the authors’ knowledge, the proposed technology sets a new boundary of ${t}_{p}$ vs. ${L}_{G}$ in wide band gap digital logic, and is operational at the highest reported temperature (500 °C) of a GaN digital circuit. The results reflect the promising potential of the proposed technology for emerging HT applications at 500 °C and beyond. [ABSTRACT FROM AUTHOR]

Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and higher device density. One of the most important and widely used circuits in digital logic calculations is the full adder (FA) circuit, which actually creates the problem of finding its optimal design and increasing performance. In this paper, we designed and implemented two new FA circuits in QCA technology and then implemented ripple carry adder (RCA) circuits. The proposed FAs and RCAs showed excellent performance in terms of QCA evaluation parameters, especially in cost and cost function, compared to the other reported designs. The proposed adders' approach was 46.43% more efficient than the best-known design, and the reason for this superiority was due to the coplanar form, without crossovers and inverter gates in the designs. [ABSTRACT FROM AUTHOR]

As the semiconductor industry strives for downsizing and high speed, it is confronted with increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and low-power consumption. We introduced an optimal design of content addressable memory (CAM) memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the first time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts. [ABSTRACT FROM AUTHOR]

This paper describes the fabrication of digital logic circuits comprising resistors and diodes made from protein complexes and wired together using printed liquid metal electrodes. These resistors and diodes exhibit temperature-independent charge-transport over a distance of approximately 10 nm and require no encapsulation or special handling. The function of the protein complexes is determined entirely by self-assembly. When induced to self-assembly into anisotropic monolayers, the collective action of the aligned dipole moments increases the electrical conductivity of the ensemble in one direction and decreases it in the other. When induced to self-assemble into isotropic monolayers, the dipole moments are randomized and the electrical conductivity is approximately equal in both directions. We demonstrate the robustness and utility of these all-protein logic circuits by constructing pulse modulators based on AND and OR logic gates that function nearly identically to simulated circuits. These results show that digital circuits with useful functionality can be derived from readily obtainable biomolecules using simple, straightforward fabrication techniques that exploit molecular self-assembly, realizing one of the primary goals of molecular electronics. Proteins are promising molecular materials for next-generation electronic devices. Here, the authors fabricated printable digital logic circuits comprising resistors and diodes from self-assembled photosystem I complexes that enable pulse modulation. [ABSTRACT FROM AUTHOR]

In the field of low power VLSI, the charge recovery property of adiabatic logic has been liked by the VLSI researchers. And this stimulates the research of various charge recovery techniques for low power computation. The applications of adiabatic logic in digital circuits are well understood, whereas mixed signals and analog circuits are yet to be explored. In this work, the author presents a wave shaping diode-based adiabatic logic (WSDAL) driven strong ARM comparator. The proposed ARM comparator consumes a power of 0.46 µW as compared to 14.41 µW and 8.77 µW as that of traditional strong ARM and adiabatic driven strong ARM, respectively. The reduction in power dissipation is achieved by three ways, (1) the proposed design consists of WSDAL based invertor for SR latch inputs that reduces the power dissipation up to a great extent by charge recycling through PCb (power clock bar). (2) The magnitude of PCb is half as that of PC (power clock), which reduces the node voltage difference and ultimately reduces the power dissipation, (3) the leakage and short circuit components of current get reduced utilizing PC as a sinusoidal supply. The proposed design also shows better thermal stability with varying temperature conditions. [ABSTRACT FROM AUTHOR]

Memristor has been widely explored in digital logic circuits where most of the works are focused on basic gate circuits, such as OR and AND logic gates or full adders while few involve flip‐flops. In fact, flip‐flops are also basic logic units with memory function for various digital systems. In this paper, we present circuit designs for Delay (D) and Jump‐Key (JK) flip‐flops based on memristor ratioed logic (MRL). The proposed circuit for D flip‐flop only needs five memristors and one NMOS transistor, and circuit for JK flip‐flop needs seven memristors and two NMOS transistors. Furthermore, the proposed circuits have been mapped into a hybrid memristor‐CMOS crossbar array. Compared with previous approaches, the quantity of MOSFET for each proposed circuit has been greatly reduced. Thus, the proposed designs have achieved simpler structure, smaller area, and lower power consumption benefiting from the memristor's nanoscale size and low power consumption. The circuit verification based on PSpice simulation is also provided. [ABSTRACT FROM AUTHOR]

We investigate the circuit performance of the junctionless nanowire transistor. We have demonstrated pass transistor-based logic gates using the junctionless transistor. Pass transistor-based basic logic gates: AND, OR, XOR are designed using only the n-type junctionless nanowire transistor with HfO2 gate dielectric. Simulations of these circuits have been studied and analyzed under a mixed-mode environment. Outcomes of the analysis show that 3D dual gate junctionless nanowire transistor with 20 nm gate length well performed for pass transistor logic. In addition, a junctionless nanowire transistor-made multiplexer has also been studied and found to perform well. A high-k gate dielectric was used for all junctionless transistors as the higher k value improves the device characteristics and circuit performances. Our study also shows that the junctionless nanowire transistor-based pass transistor logics for digital circuit perform well. [ABSTRACT FROM AUTHOR]

Quantum dot-cellular automata (QCA) technology has recently emerged as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents and implements two 1-bit QCA-based comparator designs. The proposed QCA implementations are compact, require only a single layer and are less complex compared to recently reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvements compared to their existing counterparts in terms of the number of QCA cells and occupational area requirements in addition to cost and efficient complexity values. Furthermore, all of the proposed structures are dissipating extremely low energy values. Thus, the proposed QCA-based comparators can be viewed as viable options for low power digital applications. [ABSTRACT FROM AUTHOR]

This paper presents a general modeling method for threshold-type multivalued memristors. Through this memristor modeling method, it is very simple to establish threshold-type memristor behavior models with different numbers of memristance elements, and these models are verified by numerical MATLAB simulations. A corresponding circuit-level SPICE model of the ternary memristor behavior model is developed and simulated in LTspice, shown to be consistent with the MATLAB results. Finally, the SPICE model is used to design the AND gate, OR gate, and three NOT gates of ternary state-based logic, and the effectiveness of the circuit is proved by LTSpice simulation. [ABSTRACT FROM AUTHOR]

For the development of the market of modern microelectronics, methods are required that allow continuously increasing the productivity and energy efficiency of semiconductor products and, at the same time, reducing the required minimum area of the crystal while maintaining its functionality. Therefore, the integration of nonvolatile elements (memristors) and CMOS technologies, as well as the creation of methods for synthesizing digital circuits with smmristor functional units—memristor logic (MeMOS logic)—are urgent problems. The paper proposes a block method for the synthesis of hybrid MeMOS circuits, using minterm maps, which makes it possible to simultaneously synthesize a MeMOS circuit and optimize it. Examples of the synthesis of combinational (Exclusive OR) and sequential (RS-trigger) schemes. The existing and new variants of solutions to problems of the synthesis of combinational and sequential integrated circuits with memristors are considered. It is shown that the average power dissipated RS-trigger is 7.7 μW for the standard logic and 2.2 μW for the memristor logic. The power consumption of the XOR circuit is 13 μW for the standard logic and 9.2 μW for the memristor logic. [ABSTRACT FROM AUTHOR]

The latest efforts in digital fluidic circuits' research aim at being electronics‐free, light‐weight, and compliant controllers for soft robots; however, challenges arise to adjust the fluidic circuit's digital logic operations. Currently there is no other way to modulate the amplitude or frequency but to structurally redesign the entire fluidic circuitry. This is mainly because there is currently no method to create an analog circuit‐like behavior in the digital fluidic circuits using conventional digitized fluidic gates. In this work, a new approach is presented to designing a circuit with digitized fluidic gates that is comparable to an analog circuit capable of actively tuning the circuit's fluidic characteristics, such as pressure gain, amplitude of output, and time response. For the first time, a pressure‐controlled oscillator is modeled, designed, and prototyped that not only controls the fluidic oscillation, but also modulates its frequency using only a single, quasi‐static pressure input. It can also demonstrate the circuit's performance for the control of a soft robotic system by actively modulating the motion of a soft earthworm robot up to twice of crawling speeds. This work has distinct contributions to designing and building intelligent pneumatic controllers toward truly comprehensive soft robotic systems. [ABSTRACT FROM AUTHOR]

In the present day, optical communication technology is proving to be one of the potential replacements to the current electronic-based systems due to its much higher data transmission rate with low loss and electromagnetic interference. This paper designed and simulated our proposed circuit of a digital photonic even parity bit error detection system that is widely employed for the long-range digital signal transmission. Silicon photonic micro-ring resonators are used as their core component. Each of the rings is configured to operate as a digital logic XOR mode by taking advantage of the silicon waveguide's resonance shifting properties. Dynamic response characterization was carried out by simulating the proposed circuits at the data rate of 1-Gbps, with the data sampling rate of 1.6-THz. A clear timing waveform was generated to confirm that the proposed circuit operates as the parity bit error detection system. [ABSTRACT FROM AUTHOR]

Electronic devices based on 2D materials have exhibited outstanding figures of merit. However, the fabrication of 2D diodes still relies on manual or semi‐automated handling processing. To unleash their commercial potential, the integration of 2D materials into a fully‐automated fabrication line is a critical step. Here, the focused ion‐beam writing as an automated approach to construct lateral diodes on a 2D heterostructure (MoSe2/G) consisting of graphene and MoSe2 is elucidated. Se‐defects generated by focused ion writing endow the 2D heterostructure with unique electronic properties, which allows for the construction of the barrier at the boundary of the writing and non‐writing region. Benefiting from this feature, the ion‐beam‐written heterostructure is used to realize rectifying and current regulating diodes. Exhibiting comparable performance to traditional diodes, the rectifying diode has a rectification ratio of ≈104, while the current regulative diode has a dynamic resistance larger than 4.5 MΩ. Furthermore, to illustrate practical applications of these diodes in digital logic electronics, AND and OR logic gates are directly inscribed on the heterostructure by ion beams. This work demonstrates focused ion‐beam writing as an additional strategy for direct‐writing of 2D diodes on graphene‐based heterostructures. [ABSTRACT FROM AUTHOR]

This article advances a new theory of the digital democratic affordance, a concept first introduced by Lincoln Dahlberg to devise a taxonomy of the democratic capacities of digital media applications. Whereas Dahlberg classifies digital media affordances on the basis of preexisting democratic positions, the article argues that the primary affordance of digital media is to abate the costs of political participation. This cost-reducing logic of digital media has diverging effects on political participation. On an institutional level, digital democracy applications allow elected representatives to monitor and consult their constituents, closing some gaps in the circuits of representation. On a societal level, digital media allow constituents to organize and represent their own interests directly. In the former case, digital affordances work instrumentally in the service of representative democracy; in the latter, digital democratic affordances provide a mobilized public with emerging tools that put pressure on the autonomy of representatives. [ABSTRACT FROM AUTHOR]

In this paper, a behavioral SPICE memristor model for digital logic implementation is presented and demonstrated in LTSpice. We show binarized state switching and voltage thresholding in the model, which are both important features in practical digital systems. The use of this SPICE model is straightforward and intuitive because almost all parameters in the model can be changed according to the application, including the threshold voltage and the memristance. The LTSpice circuit simulation shows the same characteristics as the original MATLAB numerical implementation, which means that the circuit-level SPICE model can be integrated with other designs. Three types of memristor digital logic circuits are simulated with the LTSpice model with positive results, which proves that the behavioral memristor model has potential application in digital system design. [ABSTRACT FROM AUTHOR]

The proposal of compute-in-memory (CIM) is a breakthrough for the traditional von Neumann architecture to achieve efficient computing research. This architecture has unique advantages in the computing field thanks to supporting multi-line computing and without data transmission between processor and memory. In this paper, an in-memory computing structure based on 9T SRAM unit is proposed, which can both operate on memory and computing mode. Compared with the previous works, thanks to the redundant units, the computational structure can directly complete XNOR operations and storage of the whole SRAM array in only one cycle, without the need of extra digital logic circuits (such as AND, OR circuits), which can significantly improve the parallelism of the computation. Meanwhile, the architecture can map the XNOR logical operation into the binary multiplication, and then add up the one-bit multiplication results through the addition tree, thus realizing the binary convolution calculation. A 64-bit × 64-bit (4 Kb) SRAM array with the proposed scheme is designed and simulated in 55 nm CMOS technology. Simulation results show excellent stability and write yields in SRAM memory mode at an operating frequency of 200 MHz. In computing mode, the SRAM array power consumption for logical operation is 52.68 fJ/bit at 1.2 V supply voltage. At a minimum supply voltage of 0.8 V, the power consumption is only 5.58 fJ/bit, with an energy efficiency 179.21 TOPS/W. [ABSTRACT FROM AUTHOR]

Teaching second year undergraduate digital electronics is a serious business, designed to impart individual technical mastery. In this paper we attempt to embed several key digital logic concepts within an escape room game. We report results of iteratively piloting our game with academic engineering staff and then used them with students showing promise for using escape rooms to support undergraduate engineering education. [ABSTRACT FROM AUTHOR]

Micro-electro-mechanical relays with multiple gate electrodes (i.e., multiple input voltage signals), operated with a tunable body bias voltage, are investigated for more compact and energy-efficient implementation of digital logic circuits. Specifically, a relay design with three gate electrodes of equal area is demonstrated to be capable of performing different digital logic functions for the same input operating voltage (${V} _{\textbf {DD}}$), by adjusting the body bias voltage. Since the lower limit for ${V} _{\textbf {DD}}$ is equal to the switching hysteresis voltage (${V} _{\textbf {H}}$), the magnitude of ${V} _{\textbf {H}}$ is investigated for different combinations of transitioning input voltage signals. It is found that ${V} _{\textbf {H}}$ is larger for fewer transitioning input voltage signals, i.e., reduced effective actuation area of the switching input voltage signal. This can set a practical upper limit for the number of independent gates in a single relay. [ABSTRACT FROM AUTHOR]

The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under:Algorithmic Development > Structure DiscoveryTechnologies > Machine LearningTechnologies > Prediction [ABSTRACT FROM AUTHOR]

A new design of quaternary inverter (QNOT gate) is proposed by means of finite-element simulation. Traditionally, increasing the number of data levels in digital logic circuits was achieved by increasing the number of transistors. Our QNOT gate consists of only two transistors, resembling the binary complementary metal-oxide-semiconductor (CMOS) inverter, yet the two additional levels are generated by controlling the charge-injection barrier and electrode overlap. Furthermore, these two transistors are stacked vertically, meaning that the entire footprint only consumes the area of one single transistor. We explore several key geometrical and material parameters in a series of simulations to show how to systematically modulate and optimize the quaternary logic behaviors. [ABSTRACT FROM AUTHOR]

High-frequency firing activity can be induced either naturally in a healthy brain as a result of the processing of sensory stimuli or as an uncontrolled synchronous activity characterizing epileptic seizures. As part of this work, we investigate how logic circuits that are engineered in neurons can be used to design spike filters, attenuating high-frequency activity in a neuronal network that can be used to minimize the effects of neurodegenerative disorders such as epilepsy. We propose a reconfigurable filter design built from small neuronal networks that behave as digital logic circuits. We developed a mathematical framework to obtain a transfer function derived from a linearization process of the Hodgkin-Huxley model. Our results suggest that individual gates working as the output of the logic circuits can be used as a reconfigurable filtering technique. Also, as part of the analysis, the analytical model showed similar levels of attenuation in the frequency domain when compared to computational simulations by fine-tuning the synaptic weight. The proposed approach can potentially lead to precise and tunable treatments for neurological conditions that are inspired by communication theory. [ABSTRACT FROM AUTHOR]

1D memristors with nonvolatile memristive characteristics have large potential in brain‐like neuromorphic computation and digital logic circuits. Herein, a novel memristive device based on wrinkled MoS2 wrapped GaN nanowires (NWs) with a spray‐coated Ag NWs network top electrode is described. The memristive device shows good stability/durability and retention characteristics for 798 cycles and 3.4 × 103 s, respectively, together with low switching voltages. A memristive model based on filament formation/rupture in the wrinkled surface of the NWs is proposed by analyzing the conductive characteristics and surface structure. Bipolar resistive switching is governed by the electric field associated with the wrinkled structure giving rise to migration of oxygen ions along the wrinkled surface of the NWs. The results enrich the knowledge pertaining to the design and optimization of memristors composed of NWs and also provide insights into the memristive behavior of memristors composed of 1D materials. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) have shown great promise in a variety of applications ranging from digital logic circuits to biosensors and artificial synapses for neuromorphic computing. The working mechanism of OECTs relies on the mixed transport of ionic and electronic charge carriers, extending throughout the bulk of the organic channel. This attribute renders OECTs fundamentally different from conventional field effect transistors and endows them with unique features, including large gate-to-channel capacitance, low operating voltage, and high transconductance. Owing to the complexity of the mixed ion-electron coupling and transport processes, the OECT device physics is sophisticated and yet to be fully unraveled. Here, we give an account of the one- and two-dimensional drift-diffusion models that have been developed to describe the mixed transport of ions and electrons by finite-element methods and identify key device parameters to be tuned for the next developments in the field. [ABSTRACT FROM AUTHOR]

In digital system design, digital logic circuit diagrams are built using interconnects and symbolic representations of the basic logic gates. Constructing such diagrams using free sketches is the first step in the design process. After that the circuit schematic or code has to be generated before being able to simulate the design. While most of the mentioned steps are automated using design automation tools, drafting the schematic circuit and then converting it into a valid format that can be simulated are still done manually due to the lack of robust tools that can recognize the free sketches and incorporate them into end user simulators. Hence, the goal of this paper is to construct and deploy computer simulation tools capable of understanding free sketches and incorporate them into useful simulation tools. Such a tool will be useful at both the educational and the industrial levels. Moreover, while this tool is designed to deal with sketched logic circuits, it can be generalized and applied to many other fields to convert the sketched design into a digital format. To implement this tool, we relied on the emerging machine learning and image processing concepts to make sure that the designed system is robust and accurate. Our results show that our system is able to recognize all the gates in the digital circuit with more than 95% accuracy. [ABSTRACT FROM AUTHOR]

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart. [ABSTRACT FROM AUTHOR]

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Digital circuits are often prone to suffer from uncertain timing, inadequate sensor feedback, limited controllability of past states or inability of initializing memory-banks, and erroneous behavior of analog-to-digital converters, which may produce an unknown (${X}$) logic value at various circuit nodes. Additionally, many design bugs that are identified during the post-silicon validation phase manifest themselves as ${X}$ -values. The presence of such ${X}$ -sources on certain primary or secondary inputs of a logic circuit may cause loss of fault-coverage of a test set, which, in turn, may impact its reliability and robustness. In this paper, we provide a mechanism for predicting the sensitivity of ${X}$ -sources in terms of loss of fault-coverage, on the basis of learning only a few structural features of the circuit that are easy to extract from the netlist. We show that the ${X}$ -sources can be graded satisfactorily according to their sensitivity using support vector regression, thereby obviating the need for costly explicit simulation. Experimental results on several benchmark circuits demonstrate the efficacy, speed, and accuracy of prediction. [ABSTRACT FROM AUTHOR]

The occupied area, power consumption, and delay are the most crucial and critical factors in constructing integrated circuits. Due to the reduced occupied area, highly low power consumption, and extremely high speed of quantum-dot cellular automata (QCA) technology, it is one of the finest alternatives to complementary metal–oxide–semiconductor (CMOS) technology for nanoscale construction of circuits. On the other hand, fault tolerance becomes crucial in QCA due to the inherent sensitivity of quantum dots to various sources of errors and faults. These errors can arise from environmental disturbances, manufacturing imperfections, thermal fluctuations, and other factors. The presence of defects or faults can significantly impact the functionality and accuracy of QCA systems, leading to incorrect computation or signal corruption. To address these challenges, fault-tolerant structures are designed in QCA systems. These structures are specifically engineered to detect, tolerate, and mitigate the effects of faults, thereby enhancing the reliability and robustness of QCA-based computation. Fault-tolerant designs aim to ensure that the system can continue to operate correctly even in the presence of defects or faults. In QCA, proposed a fault-tolerant majority gate is necessary to ensure reliable computation in the presence of defects or faults. The fault-tolerant majority gate is a fundamental component in digital logic circuits, and it plays a crucial role in performing computations. It takes multiple input signals and produces an output based on the majority of those inputs. In classical computing, the majority gates are typically implemented using transistors. Therefore, t his paper introduces a new and efficient fault-tolerant 3-input majority voter (FT MV3) using 11 simple and rotated cells in the QCA technology, which is 100% and 90.47% tolerant against single-cell and double-cell omission defects. The recommended FT MV3 gate verification is confirmed using some physical proofs. Afterward, to illustrate the performance of the introduced gate, three fault-tolerant computational circuits, including multiplexer, adder and ALU, are presented using the introduced FT MV3 gate. The comparison of the proposed fault tolerant ALU to the best coplanar design shows a 28.80% and 34.01% reduction of cell count and occupied area, respectively. All circuits are simulated using QCADesigner 2.0.3 software. [ABSTRACT FROM AUTHOR]

Digitalization of handwritten documents has created a greater need for accurate online recognition of hand-drawn sketches. However, the online recognition of hand-drawn diagrams is an enduring challenge in human-computer interaction due to the complexity in extracting and recognizing the visual objects reliably from a continuous stroke stream. This paper focuses on the design and development of a new, efficient stroke-based online hand-drawn sketch recognition scheme named SKETRACK for hand-drawn arrow diagrams and digital logic circuit diagrams. The fundamental parts of this model are text separation, symbol segmentation, feature extraction, classification, and structural analysis. The proposed scheme utilizes the concepts of normalization and segmentation to isolate the text from the sketches. Then, the features are extracted to model different structural variations of the strokes that are categorized into the arrows/lines and the symbols for effective processing. The strokes are clustered using the spectral clustering algorithm based on p-distance and Euclidean distance to compute the similarity between the features and minimize the feature dimensionality by grouping similar features. Then, the symbol recognition is performed using modified support vector machine (MSVM) classifier in which a hybrid kernel function with a lion optimized tuning parameter of SVM is utilized. Structural analysis is performed with lion-based task optimization for recognizing the symbol candidates to form the final diagram representations. This proposed recognition model is suitable for simpler structures such as flowcharts, finite automata, and the logic circuit diagrams. Through the experiments, the performance of the proposed SKETRACK scheme is evaluated on three domains of databases and the results are compared with the state-of-the-art methods to validate its superior efficiency. [ABSTRACT FROM AUTHOR]

In recent years, the development of biological computers is becoming faster and faster, in order to make the logical operation algorithms of biological computers more mature and stable, a new idea for the code lock logic circuit is proposed based on DNA strand displacement by using the dual-rail method. The code lock is designed by four input signals and one conversion input signal. Only when the four input codes are correct and the conversion signal code is turned on, the password lock will be in open state, otherwise the password lock will produce an alarm signal, stopping outside invasion timely. The information of key is processed to obtain the correct password; finally, the experimental simulation results are obtained by Visual DSD software. The results analysis show that the designed code lock circuit is effective, which may provide a good technical support and a good theoretical basis in biological computers development. In this study, the digital logic circuit of five inputs code luck based on DNA strand displacement technology was first designed. Then the digital circuit was converted into a dual-rail logic circuit with the new dual-rail idea. Subsequently a molecular circuit has been generated. Finally, the validity of this design was verified through DSD software. This design of the bio-molecular logic circuit may promote the development of bio-computing. [ABSTRACT FROM AUTHOR]

In view of the current curriculum time gradually reduced and the teaching requirements continue to improve, summarized and analyzed the basic contents and teaching objectives of the digital circuit curriculum. A digital circuit teaching experimental platform was designed and developed in the absence of additional course hours and enriching the experimental content, improve the efficiency of course hours, at the same time actively carry out the curriculum design.In order to reduce the device loss, a conventional chip verification and demonstration module was developed. In order to improve the understanding of digital signal, a 8-bit binary digital signal unit was designed. Some other features include: tri-state logic pen unit, FPGA programmable unit, single pulse generating unit, DAC, ADC unit, liquid crystal display unit etc. The design of the platform is improved from the already used platform, which has provided a convenient and basic value for the basic course teaching. [ABSTRACT FROM AUTHOR]

A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ($\Delta {V}_{\text {T}}$) and by both $\Delta {V}_{\text {T}}$ and subthreshold slope shift ($\Delta $ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring $\Delta $ SS on OFF current and static power (${P}_{\text {static}}$) is estimated. [ABSTRACT FROM AUTHOR]

• Universal logic gate based on CMOS-memdiode technology. • Full adder circuit based on CMOS-memdiode technology. • Memristor-based digital logic circuits. • ULG and Full adder circuit in LT-SPICE. • Memristor-based universal logic gate calibrated with experimental data. The study of memristor-based digital logic circuits is a new approach in non-conventional computation frameworks because of the memristor's properties, especially the ability to store data and perform logic operations. Using memristors, in this work, we have analyzed in terms of variability basic AND/OR Universal Logic Gates (ULG) and a Full adder implementation at the circuit-level in LT-spice. We first implement and calibrate a memristor's model with data obtained from IV curves of HfO2-based ReRAM to do it. The data demonstrate that although buffers are used to restore the signal, memristors variability affects the output voltage and the circuit's performance. [ABSTRACT FROM AUTHOR]

A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T XOR-XNOR gates combined with a feedback loop. The performance of this new cell is compared with some reported ones and then, using this new cell and two other modules, a novel full adder circuit is proposed and evaluated in TSMC 0.18 μm CMOS process technology. Post-layout simulations using Cadence Virtuoso tool showed 33%–74% and 35%–81% improvement in terms of power consumption and power-delay product (PDP), respectively, compared with some well-known counterparts in the literature. Furthermore, high-performance claim of our proposed full adder cell is verified through the process, voltage and temperature (PVT) variations' simulation of the adders. Finally, implementation of different full adders in 4-bit ripple carry adders (RCAs) proved our new design has high performance in the aspects of power dissipation and PDP. [ABSTRACT FROM AUTHOR]

A new family of two-dimensional optical hybrid code which employs zero cross-correlation (ZCC) codes, constructed by the balanced incomplete block design BIBD, as both time-spreading and wavelength hopping patterns are used in this paper. The obtained codes have both off-peak autocorrelation and cross-correlation values respectively equal to zero and unity. The work in this paper is a computer experiment performed using Optisystem 9.0 software program as a simulator to determine the wavelength hopping/time spreading (WH/TS) OCDMA system performances limitations. Five system parameters were considered in this work: the optical fiber length (transmission distance), the bitrate, the chip spacing and the transmitted power. This paper shows for what sufficient system performance parameters (BER≤10−9, Q≥6) the system can stand for. [ABSTRACT FROM AUTHOR]