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High-performance architectures are over-provisioned with resources to extract the maximum achievable performance out of applications. Two sources of avoidable power dissipation are the leakage power from underutilized resources, along with clock power from the clock hierarchy that feeds these resources. Most reconfiguration mechanisms either focus solely on power gating execution resources alone or in addition, simply turn off the immediate clock tree segment which supplied the clock to those resources. These proposals neither attempt to gate further up the clock hierarchy nor do they involve the clock hierarchy in influencing the reconfiguration decisions. The primary contribution of CHARSTAR is optimizing reconfiguration mechanisms to become clock hierarchy aware. Resource gating decisions are cognizant of the power consumed by each node in the clock hierarchy and additionally, entire branches of the clock tree are greedily shut down whenever possible. The CHARSTAR design is further optimized for balanced spatio-temporal reconfiguration and also enables efficient joint control of resource and frequency scaling. The proposal is implemented by leveraging the inherent advantages of spatial architectures, utilizing a control mechanism driven by a lightweight offline trained neural predictor. CHARSTAR, when deployed on the CRIB tiled microarchitecture, improves processor energy efficiency by 20-25%, with efficiency improvements of roughly 2x in comparison to a naive power gating mechanism. Alternatively, it improves performance by 10-20% under varying power and energy constraints.

This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV’s large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates’ insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV’s placement. Compared with previous 3D clock tree synthesis techniques, our K-means clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance. New circuit approaches for current-mode (CM) clocking save significant clock power, but have been limited to only symmetric networks, while most application specific integrated circuits have asymmetric clock distributions. In this paper, we propose the first CM clock synthesis (CMCS) methodology to reduce the overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. We validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks using an extracted SPICE model distributed in 1.4–275.6-mm2 area and consists of 81–2249 sinks. This methodology saves 39%–84% average power with similar skew on the benchmarks using 45-nm CMOS technology simulation of clock frequencies range from 1–3 GHz. In addition, the CMCS methodology takes $2.4-9.1\times $ less running time and consumes 20%–26% less transistor area compared with synthesized, buffered VM clock distributions.

Clock trees, which deliver the clock signal to every clock sink in the whole system, switch actively at high frequency, which makes them one of the most dominant sources of noise. While many clock polarity assignment (PA) techniques were proposed to mitigate the clock noise, no attention has been paid to the PA under useful skew constraints. In this work, we show that the clock PA problem under useful skew constraints is intractable and propose a comprehensive and scalable clique search based algorithm to solve the problem effectively. In addition, we demonstrate the applicability of our solution by extending it for PA under delay variation environment. Through experiments with ISPD'10 benchmark circuits, we show that our proposed clock PA algorithm is able to reduce the peak noise by 10.9% further over that of the conventional global skew bound constrained PA. Finally, we compare our PA technique against decoupling capacitor embedding technique which is a commonly used method for noise reduction. HighlightsWe propose a clock buffer polarity assignment algorithm under useful clock skew constraints that enables the consideration of individual setup and hold time constraints for the reduction of power and ground noise emitted by the clock trees.We prove that the polarity assignment under useful clock skews is intractable.A heuristic framework that is able to trade-off between the quality of solution and run-time is proposed.

A simple circuit for duty-cycle correction is proposed in this paper. The configuration is flexible consisting of only three CMOS inverters in a feedback loop. It does not require any reference signal and, therefore, it can be used as a standalone circuit, while it can be applied on a single-ended clock path without breaking the clock line. Simulation results in a 65 nm CMOS technology and 1 V supply voltage give a duty-cycle error less than 1% for a duty-cycle input clock variation between 30 and 70% with a frequency range from 2.4 to 2.9 GHz.

Clocking of electrical circuit is a crucial issue since clock signal is used to establish the flow-of-time inside electronic world. Before, during and after the "Moore's law", flow-of-time is an eternal issue. Alongside processor, memory/storage and analog/ RF technologies, IC clocking could be regarded as the 4th major IC design technology. In the past several decades, clock is mostly used in the form of fixed-frequency with high frequency stability. For future system, however, this type of clock signal is not sufficient because its usage environment is not expected to be stationary but dynamic. To meet this challenge, innovation in IC clocking is required. This paper first discusses the difficulties in creating flow-of-time; then the two long-lasting problems in clock generation are identified, and then new challenges in the design of future system are summarized. Afterwards, the Time-Average-Frequency based flexible clock generator is introduced and its potential to confront these challenges is addressed. Several major issues in modern design are discussed. The paper concludes with a vision that, for electronic system to improve its information processing efficiency to next level, clock technology is the next frontier to be explored.

Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that constructs useful skew clock trees with large safety margins that are tailored to the tree topology. Sequential elements are clustered early in the topology, if it is impossible provide adequate robustness to variations using only safety margins. Compared to earlier studies, the proposed framework performs the clock scheduling one to two orders of magnitude faster and improves yield and capacitive cost on several synthesized circuits.

The work solves a new problem of optimizing the boundary of buffered clock trees, which has not been addressed in the design automation as yet. Precisely, we want to show that the clock cells that directly drive flip-flops should not necessarily be buffers. By taking into account the internal structure of flip-flops, we can have a freedom of choosing either buffers or inverters for the cell implementation from library. This in fact leads to cancel out the two inverters, one in the driving buffer and another in each flip-flop, thereby reducing the power consumption on the clock tree, including flip-flops. We generalize this idea to look into the possibility of co-optimizing the driving buffers and flip-flops together to reduce the clock power at the boundary of clock trees, and propose an effective four-step synthesis algorithm of clock tree boundary for low power. By applying our proposed technique to benchmark circuits, it is observed that the clock power is able to be reduced by 4.45 % ~ 6.33 % further on average without timing violation.

This paper suggests a simple method to solve the clock skew problem generated on two or several separate chips when voltage difference, or gradient, occurs between/among the chips. Generation and distribution of clock signals with minimum skews becomes a critical factor in overall system performance in today’s GHz operation speed. With a few connection lines, similar to Data Bus, between two chips, named CBL (Clock Bus Line), a multi-chip synchronization method is newly proposed and proved through simulations and TTL chip measurements. With 2% of supplied voltage differences in different chips, within 3% of the period clock skew is guaranteed in this new scheme. A feasible way of implementation of this CBL method in today’s integrated circuits is also described along with CMOS layout.

The present invention discloses a method for synchronizing a clock signal which designs a ring oscillator with a stable fractal structure. The method for synchronizing a clock signal comprises the following steps of: receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal; oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip; and outputting the first clock signal and the second clock signal as the clock signal having the same frequency and the same phase. The clock line connects three ends of the first chip and the second chip having the same fractal structure.

A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: 1) a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and 2) a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCAS’89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies.

EtherCAT has been widely applied in the motion control domain due to its advantages of the fast response speed, low CPU usage and good synchronization performance. Although the built-in distributed clock (DC) synchronization mechanism exhibits strong performance between slaves, the method of clock synchronization between the master and the reference clock is left open for selection by users and there are very few studies in this area. This paper introduces three synchronization modes for EtherCAT and analyzes the reasons for packet loss in free run mode and DC mode. This paper presents a novel method to realize the master clock synchronization with the reference clock. The proposed method can eliminate the settling time which is unusual in other synchronization mechanisms. The method is implemented on Windows with real-time extension and experimental results prove its feasibility.

dissipation is major drawback in the digital sequential circuit design of low power electronic devices. Clock signal is one input which is common for all the sequential circuits. The clock signal has major power dissipation at high frequencies. The clock gating technique can be implemented at architectural level to reduce the power dissipation at dynamic and clock power level. Aim of this paper is to analyze, implement and comparison between various clock gating techniques for a 8-bit ALU on a artix7,45 nm technology with xc7a100t-3csg324 , xc6slx41-1Ltqg144 spartan6 with 40nm FPGA board. The two clock gating techniques are proposed and used in the design are namely: T-flip flop and use of latch. This technique is implemented by using Xilinx 14.1. T flip flop is best for this design as it requires less number of gate counts and also less area. Operation using11 instructions are performed in the proposed design. This technique is designed through T Flip-Flop based on gated clock ALU at RTL level. At different operating frequencies of 100MHZ, 200MHZ, 300MHZ, 400MHZ & 500MHZ, the dissipated power is 5mw, 9mw, 14mw, 19mw,24mw respectively. Keywordscircuit, T-FF, Clock- Gating, Implementation

The clock distribution network primarily comprises of the clock tree and the flip-flops. The resonant clocking, which drives a clock tree possesses a large potential for a sweeping power minimisation in the clock network. In addition, the clocked flip-flops, being the crucial timing elements, have become a major contributor to the total power dissipation. Thus, this study proposes a novel `self-gated resonant (SGR) clocked flip-flop' to address these concerns. The proposed flip-flop achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. Second, this study investigates the use of the resonant clock in a hierarchical clock tree distribution network operating 1024 flip-flops at its leaf nodes. The advantages of the SGR clocked flip-flop are validated through exhaustive simulations and comparisons, with the flip-flop structures available in the literature. Furthermore, the post-layout simulations of a typical H-clock tree driving the 1024 flip-flops at the leaf cells have been carried out. Cadence ® EDA tools and the 45 nm process technology files have been used to substantiate the merits of the proposed design.

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of ip-ops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate exible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period (Tclk) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today’s CMOS process scaling, enables the receiver to achieve low power and area consumption. The ADCDR can enter into open loop after lock-in to save power and avoid clock dithering phenomenon. Moreover, to compensate the open loop, a phase tracking procedure is proposed to enable the ADCDR to track the phase drift due to the voltage and temperature variations. Furthermore, the all-digital delay-locked loop circuit integrated in the ADCDR can generate accurate multiphase clocks with the proposed calibrated locking algorithm in the presence of process variations. The precise multiphase clocks are essential for the half-rate sampling and Alexander-type phase detecting. Measurement results show that the receiver can operate at a data rate of 6.4 Gbits/s with a bit error rate $ , consuming 7.5-mW per lane (1.2 pJ/bit) under a 0.85 V power supply. With ADCDR’s phase tracking, the receiver performs better in jitter tolerance and achieves a 500-kHz bandwidth, which is high enough to track the phase drift. The receiver core occupies an area of 0.02 mm $^{2}$ per lane.

Two types of clock networks including clock mesh and a buffered clock tree in a daisy-chain style were utilized to synchronize 5 DFF chains and fabricated in a 28 nm bulk CMOS technology. Alpha and proton particles did not trigger any errors indicating the significant single event tolerance of these clock networks. Heavy ion results for the data input pattern of checkerboard (alternate 1 and 0) are presented showing few occurrences of burst errors induced by single event transients (SETs) in the buffered clock tree at relatively high LET values. The same phenomena were observed in laser tests. Clock mesh is therefore proven to be less sensitive to SETs, if pre-mesh drivers do not generate transients. Otherwise, clock mesh possesses lower tolerance, as demonstrated in previous work. Moreover, these burst errors occurred (1) simultaneously in a DFF chain and its subsequent chains, or (2) in a single chain with subsequent chains unaffected. The distinct mechanisms of these burst errors were found to be the electrical masking effect of the daisy-chain clock buffers.

The portion of clock power in system is rapidly increasing with the continuous increasing of clock frequency and clock resources. Last two decades, a great research attention has been paid to minimizing the clock power. Recently, it is shown that the structure of resonant clock networks is very effective in saving power since it can store electric energy to the inserted inductors rather than dissipate. On the other side, it has been known that dynamic voltage-frequency scaling (DVFS) is one of the most effectively and widely used power reduction techniques. However, so far no works have addressed the design methodology problem of synthesizing resonant clock networks that are able to operate under the designs with DVFS capability even though the problem is potentially very important to maximize the synergy effect on saving power. In this context, this paper proposes a comprehensive solution to the problem. Precisely, we propose a two-phase synthesis algorithm: 1) formulating the problem of inductor allocation, placement, and adjustable-sizing to support DVFS into a weighted set cover problem with the objective of minimizing total area of inductors and 2) followed by performing the task of resizing of adjustable driving buffers to support the switch of driving strength according to the clock frequencies by DVFS. Through experiments with benchmark circuits, it is shown that for designs with DVFS using 1 and 3 GHz, our algorithm synthesizes resonant clock networks with 25.9% less power on the execution of the clock frequency, which is not supported by resonant clocking in the previous no-DVFS aware resonant clock synthesis algorithm.

Nowadays, power is a primary concern in digital circuits and clock distribution networks are particularly a significant power consumer. Therefore, clock gating is an effective technique in saving dynamic power by reducing the switching activities. In this paper, we propose a centralized and fine-grained microarchitecture-level clock gating for low power hardware accelerators which are automatically designed by high-level synthesis (HLS) tool. The basic principium of our idea is not to use any extra computation for generating clock enabled signals and exploit exiting signals of finite state machine for controlling the datapath clock network. After determining the current state in finite state machine, clock sub-tree of current state is enabled and the other sub-trees are disabled with a slight increase in circuit area. Our approach is implemented within an HLS design flow for automatic low power hardware accelerator generation in application specific integrated circuit design. Experimental results are obtained on a set of representative benchmark programs. Depending on the circuit size and number of registers, it is shown that 47%–86% reduction in power dissipation is observed.

A high precision multi-node clock network for multiple users was built following the precise frequency transmission and time synchronization of 120 km fiber. The network topology adopts a simple star-shaped network structure. The clock signal of a hydrogen maser (synchronized with UTC) was recovered from a 120 km telecommunication fiber link and then was distributed to 4 sub-stations. The fractional frequency instability of all substations is in the level of 10-15 in a second and the clock offset instability is in sub-ps in root-mean-square average.

For a multi-die IC, the chip-level clock synchronization problem that aims to establish a global clock signal across multiple functional dies is harder to achieve than its single-die counterpart. In this work, we investigate a process resilient solution for this problem by incorporating Delay-Locked Loops (DLLs). The basic idea is to insert a DLL (which can be generated by a DLL compiler) in each functional die so that the clock latency (from a clock source to the clock ports of a number of FFs) in different dies can be dynamically tuned and equalized. This method has a benefit that the clock network of each die can be designed independently, while the clock skew of the entire chip can still be minimized at run-time, in response to its operating environment. In a preliminary study, experimental results on a pseudo 4-die design demonstrates how the clock skew as high as 233ps initially can be reduced to 34ps after the application of the proposed method.

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.

This paper describes the development of an embedded SNTP clock which applies NTP Protocol to embedded clock to realize the high accuracy and precision SNTP client clock. It consists of three parts which are the communication part to communicate between NTP Server and SNTP client clock, the data processing part to process data packet, and maintain accuracy, precision of time, and the result displaying part to show time together with the reliability status of the clock. This article explains the concept of applying and analyzing NTP packet, process of maintaining accuracy and precision of time and displaying the result, and hardware, software designs. This paper will provide the introduction of NTP, the development of NTP on the embedded clock, the simulation, and results of the experiment.

A clock skew-compensation and duty-cycle correction circuit (CSADC) is used as the second-level clock distributing circuit to align a system global clock while maintaining a 50% duty cycle. A power-efficient, range-unlimited, and accuracy-enhanced CSADC, designed mainly with a new delay-interleaving and -recycling technique that mitigates operating frequency limitations while keeping overhead costs low, is proposed in this paper. Our preliminary research results prove the feasibility of the proposed technique and show that the operating frequency ranges from 110 MHz to 1.75 GHz, with the corrected duty cycle varying from 51.2% to 48.9% based on 0.18- $\mu $ m CMOS technology. Meanwhile, the lock-in time, static phase error, and power consumption are, respectively, 26 clock cycles, 4.2 ps, and 5.58 mW at 1.75 GHz.

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

Summary This paper proposes a new open-loop and low complexity (small size) fast-lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open-loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase-locked loops or delay-locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non-return-to-zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal-oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35-data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright © 2015 John Wiley & Sons, Ltd.

We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks.

Clock trees are commonly used to deliver clock signals to sequential elements in circuits. However, by construction, tree structures are inherently prone to failure caused by variations. The robustness of a clock tree can be improved by inserting redundancy in the form of cross links or multilevel fusion trees. Such near-tree structures can provide robustness at low cost. In this paper, we establish that the locations of the inserted redundancy are crucial in providing cost-effective robustness. We present two methods to systematically insert redundancy. The redundancy is realized by either inserting cross links or performing local merges. Moreover, we present a vertex reduction method that reduces the amount of redundancy that needs to be inserted in our near-tree structures. Empirical results show that our structures are more robust to variations and have lower power consumption compared to the state-of-the-art clock networks. Furthermore, our near-tree structures provide smooth trade-offs between cost and robustness, reducing clock skews by 11%–39% at an expense of 3%–68% higher power consumption.

Small delay defects are posing a serious challenge to the quality and reliability of modern fabricated chips. A promising way for screening the timing-related defects in nanometer technology designs is faster-than-at-speed delay testing. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip frequency-programmable test clock generation method which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. With a reconfigurable launch-and-capture clock generator (LCCG) embedded on-chip, the required test clock, with a reconfigurable frequency and a high resolution, can be achieved by specifying the control information in the test patterns, which is then used to configure the LCCG. Similarly, the control information regarding test framework and clock signal selection can also be embedded in the test patterns. Experimental results are presented to validate the proposed method. A launch and capture clock generator (LCCG) is proposed for generating faster-than-at-speed test clock with programmable frequencies, which can be used to detect SDDs effectively by reducing the slacks of paths under test.The frequencies of faster-than-at-speed test clocks can be easily programmed by embedding the control information into the test patterns. Moreover, the frequencies of the generated test clocks have a high resolution and can achieve a large dynamic range.Both LOC and LOS test frameworks can be supported by the proposed method. The control information for selecting various test frameworks can also be embedded in the test patterns. The reason of not considering the ES test framework in this paper is that the enhanced scan delay testing approach is rarely used in industry for the unacceptable hardware overhead.With a programmable clock selection signal from the LCCG, a clock signal selector is designed to effectively support the application mode such as scan mode, functional operation mode, and test mode by selecting the required clock signal.Frequency variation of the generated test clock in the presence of process variations is analyzed. A method for preventing yield loss caused by frequency variation is presented, so that the test clock period can be programmed to leave a sufficient margin to avoid yield loss.The hardware overhead of the proposed LCCG and clock signal selector is very low, which isapproximately equal to that of 40 standard muxed-D scan cells and can be ignored by modern designs.

The digital clock is a clock designed by digital circuit. Now, there are some limitations in the use and regulation of the digital clock in the large square. In this paper, the infrared remote-controlled digital clock based on FPGA can solve this problem well. This digital clock is composed of three parts: infrared remote control module, main circuit of the digital clock and function modules. And it is designed by the VHDL hardware description language, in the Quartus II software development environment.In addition, the digital clock has many extended functions, such as the hour timekeeping, alarm clock and temperature measuring. Besides, it has many advantages, including stable system , simple structure, short development cycle, fast speed and the strong usability.

Achieving same notion of time remains an important task for most distributed systems. Time synchronization requires a unique combination of high accuracy ($$\upmu $$μs level) and energy efficiency. Several application layer protocols have been developed to meet these requirements. This article proposes that the physical layer clock recovery process can provide application layer clock drift estimate, and the application layer clock can be corrected with the help of this estimate. This eliminates the need of application layer time synchronization protocol i.e. the cross-layer approach reduces the number of message exchanges required by application layer for time synchronization that leads to energy conservation. It argues that such a cross-layer approach can provide a more accurate frequency offset estimation, or can achieve greater energy savings, for a given accuracy, by reducing the message exchanges. Analysis of the proposed method provides concrete bounds on achieved improvement. Experimental evaluation showed that physical layer clock drift can be used to correct application layer clock drift as they are identical.

Traditional die-to-die (DTD) clock skew compensation topologies prerequisite matched delay lines or equal through-silicon via (TSV) delays. Unlike previous techniques, the proposed mismatch-insensitive skew compensation architecture can maintain a synchronous clock signal between two dies, while completely eliminating any skew arising from code-dependent mismatch in delay lines or unequal TSV delays. The performance of our design is verified in theory and simulation in light of mismatch/finite resolution of delay lines, clock jitter, phase detector dead zone, TSV delay, and buffer mismatch. Postsynthesis timing verification of this cell-based design was done in a 65-nm CMOS process. Under similar worse case mismatch conditions, the residual skew in the proposed architecture was delimited to 32 ps at 1 GHz, compared with 116 ps for a recent DTD topology, while consuming only 2.1 mW.

An analog-digital clock delay locked loop (DLL) control circuit is proposed to detect and adjust the analog-digital clock phase difference in real time in a 14-bit 2GSPS digital-to-analog converter (DAC). To achieve a reasonable analog-digital clock phase difference, a digitally controlled delay line (DCDL) should be able to provide a total clock delay up to 1024ps. Such fine control is realized by a control block tracking and maintaining the precise phase relationship between analog and digital clock domains. The control circuit is realized by designing a digital finite state machine (FSM) carefully. The proposed circuit is implemented in 0.18μm CMOS technology. Simulation results show that the proposed circuit performs well in various conditions in high speed data transmission applications.

Measuring power consumption for side channel analysis typically uses an oscilloscope, which measures the data relative to an internal sample clock. By synchronizing the sampling clock to the clock of the target device, the sample rate requirements are considerably relaxed; the attack will succeed with a much lower sample rate. This work characterizes the performance of a synchronous sampling system attacking a modern microcontroller running a software AES implementation. This attack is characterized under four conditions: with a stable crystal oscillator-based clock, with a clock that is randomly varied between 3.9 and 13 MHz, with an internal oscillator that is randomly varied between 7.2 and 8.1 MHz, and with an internal oscillator that has slight random variation due to natural ‘drift’ in the oscillator. Traces captured with the synchronous sampling technique can be processed with a standard Differential Power Analysis style attack in all four cases, whereas when an oscilloscope is used only the stable oscillator setup is successful. This work also develops the hardware to recover the internal clock of a device which does not have an externally available clock. It is possible to implement this scheme in software only, allowing it to work with existing oscilloscope-based test environments. Performing the recovery in hardware allows the use of fault injection with excellent temporal stability relative to a sensitive event. This is demonstrated with a power glitch inserted into a microcontroller, where the glitch is triggered based on a signature in the measured power consumption.

High performance chip design is always a hot topic in integrated circuit (IC) field. Clock design plays a critical role in improving chip performance and affecting power consumption. The regular clock layout has always been the ideal way to improve the timing of results. In this paper, we propose a symmetrical clock tree synthesis algorithm for top-level design, including tree architecture planning, matching, merging and embedding. We also integrate buffer insertion and obstacle processing into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by average 17.2% while using less than average 24.5% capacitance resource compared with other symmetrical clock trees.

The elastic clock scheme is a robust design methodology to ensure timing closure under PVT variation using locally generated clocks and handshaking protocol. However, it still has a chance of timing errors due to delay mismatch between the data-path and delay replica. In this paper, we propose a low design overhead timing error correction scheme tailored to elastic clock. In the proposed scheme, a timing error can be corrected within a cycle using clock stretching. The proposed scheme shows 40.3× and 4.6× reduction in timing margin with 9.1% and 9.0% area overhead over the synchronous baseline and elastic clock design, respectively.

In the conventional ASIC design flow, slew constraints are imposed on clock sinks and clock buffers uniformly. The slew constraint has a significant affect not only on the timing but also on power in high performance designs. This paper investigates relaxing tight slew constraints for the reduction of low-impact buffers in clock trees. This is motivated by the observation that buffers in a clock tree that directly drive clock sinks have a high impact on meeting timing constraints. Buffers that drive other buffers in the clock tree do not directly impact the sink timing within some bound. These buffers can be considered low-impact, but still consume significant power. In order to reduce this power, the slew design constraint can be relaxed for low-impact buffers. Benchmarks from the ISPD2010 benchmark suite are synthesized to demonstrate the impact of a "slew-down" at the non-sink clock buffers of a clock tree with power and timing results from HSPICE. Results using a 20nm PTM FinFET technology at 4GHz shows that power savings of up to 50% (~10% on average) can be achieved compared to the minimum slew constraint while satisfying the same global slew constraint by a methodical slew-down process.

A clock generation system for a 1GS/s 8-bit subranging time-interleaved analog-to-digital converter (ADC) is introduced. General timing considerations for time-interleaved ADCs are reviewed prior to describing the design methodology for a prototype ADC. This hybrid ADC architecture contains four time-interleaved combined sample-and-hold and capacitive digital-to-analog converter (SHDAC) circuits as front-end sample-and-hold for a flash stage and for a time-interleaved successive approximation stage, which minimizes the errors due to sampling time mismatches between the two stages. The associated clock signal generation techniques that enable this hybrid ADC design approach are presented in this paper, which range from particular non-overlapping clocks and extensive buffering to synchronous resetting for adjusting the order of the clock signals in each time-interleaved channel. The transistor-level and layout-level clock generation circuits were designed and simulated in 130nm CMOS technology, and consume 3.88mW from a 1.2V supply. The standard deviation of the timing skews between time-interleaved channels is less than 1ps based on Monte Carlo simulations. To evaluate the feasibility of the clock generation approach, post-layout simulations were conducted with the interconnected ADC core layout and routed clock generation circuits. The hybrid ADC achieved an effective number of bits (ENOB) of 7.39 with a sampling frequency of 1GHz and an input frequency close to the Nyquist rate.

Usage of a precise and accurate clock synchronization solution is unavoidable in modern distributed systems. In industrial usage IEEE 1588:2008 standard is becoming ubiquitous as it provides in-band, cost-effective and reasonably accurate distributed clocks to implement. The reliability is mostly discussed in a cybersecurity perspective, as maintaining the integrity of the clock synchronization messages is crucial to protect the consistency of the clock synchronization network. The current (NTP) and proposed (IEEE 1588v3) clock synchronization standards contain mitigation methods to counter these issues. The PTP protocol uses tens of variables to calculate the hierarchy of the synchronization tree, and update the state variables/clock servos of the synchronizing nodes. The temporal properties of these variable may induce sensitivity to transient memory errors. For example bit errors in static (or rarely recalculated) variables may introduce reconfigurations in the clock sync network which may lead to undesired consequences. This paper examines the robustness and reliability of the IEEE 1588:2008 implementations from a different point of view. The implementation of operational memories, caches, register files used in runtime hardware employ several competing volatile memory technologies. All of them are more or less sensitive to perturbations induced by their environment or to aging. This paper analyses the causes and effects of potential problems related to operation memory corruption and offers solutions so the possible breakdowns could be mitigated or at least detected.

Clock gating is a useful technique to reduce power consumption of a synchronous sequential circuit. Conventionally, we use activity patterns, which are derived from a scheduled data flow graph and a module binding solution, to represent enable logics for clock gating. Based on activity patterns of modules, previous works utilize AND gates to construct activity-driven clock trees. In this paper, we demonstrate that, if we utilize OR gates at the bottom level, the power consumption at higher levels can be greatly reduced. From this observation, we propose a novel activity-driven clock tree design methodology, including a new tree structure and a corresponding design flow. Benchmark data show that our methodology can reduce 7.1% clock power consumption.

One of the challenging stages in Very Large Scale Integration (VLSI) design is clock network synthesis that plays an important role in the circuit performance. Digital Integrated Circuits (IC) include synchronous components and timing criteria are the most important performance constraints in the VLSI designs. This paper describes an efficient optimal method to solve the clock network buffer sizing non-convex optimization problem. We use a geometric programming format with two competing objectives, power consumption and clock network skew considering slew and technology constraints to find the global optimal solution. The proposed formulation is applied on the latest clock network benchmarks from the 2009 and 2010 ISPD clock network contests and results show up to 86% reduction in power consumption and up to 183 ps skew reduction. We also show our proposed formulation can be solved efficiently in a relatively short runtime compared to other existing algorithms in the literature.

In this paper, we introduce Pulsar, a wireless time transfer platform that can achieve clock synchronization to better than five nanosecond between indoor or GPS-denied devices. Nanosecond-level clock synchronization is a missing capability for many real-time applications like next-generation wireless systems that leverage spatial multiplexing to improve channel capacity and provide services like time-of-flight localization. With finegrained synchronization, both clock stability and propagation delays introduce significant sources of error. Pulsar leverages a stable clock source derived from a Chip-Scale Atomic Clock (CSAC) along with an Ultra-WideBand (UWB) radio able to perform sub-nanosecond packet timestamping to estimate and correct for clock offsets. We design and evaluate a proof-ofconcept network-wide synchronization protocol for Pulsar that selects low-jitter links to both estimate the location of nodes and reduce cumulative synchronization error across multiple hops. The Pulsar platform and protocol together provide a phase synchronized one pulse per second (1PPS) signal and 10 MHz reference clock that can be easily integrated with typical enduser applications like software-defined radios and communication systems. We experimentally evaluate the Pulsar platform in terms of clock synchronization accuracy, Allan deviation between pairwise clocks and ranging accuracy to show a clock synchronization of better than five nanoseconds per hop with an average of 2.12 ns and a standard deviation of 0.84 ns. The platform is able to identify and avoid clock error in cases where there is heavy multi-path or non-Line-of-Sight signals.

Background/Objective: Energy recovery is one of the most promising methods for low power design methodologies. The main idea behind the energy recovery circuits is the use of a slowly rising and slowly falling AC power supply i.e., sinusoidal or trapezoidal clock signal. Hence, it is essential to design low power clocking schemes for such energy recovery circuits. This paper presents an efficient clocking scheme for the energy recovery circuits. Methods/Statistical Analysis: The single phase sinusoidal clock signal which is used to operate the energy recovery circuits is generated from the 2N2P resonant clock generator. The sinusoidal clock signal is routed to the energy recovery circuits through the H-tree clock distribution network. Findings: Single phase energy recovery circuit, namely, the Glitch free and Cascadable Adiabatic Logic (GFCAL) is used to validate the clock network design. 16 inverters are cascaded and connected to the output nodes of the clock tree, and the cascaded chain is driven by the clock signal. Conclusion/Improvement: The simulation results show that the 16-bit adiabatic inverter chain operated at 2GHz incur a power consumption of 184.1 μWatts and the conventional CMOS inverter chain of 16-bit operated at the same frequency incurs power dissipation of 190.2μWatts. All the simulations have been carried out using the industry standard Cadence® Virtuoso tool using 180nm technology library files.

Adaptive clock generation to track critical path delay enables lowering supply voltage with improved timing slack under supply noise. This paper presents how to synthesize clock tree in adaptive clocking to fully exploit the clock data compensation (CDC) effect in digital circuits. The paper first provides analytical proof of ideal CDC effect for ring oscillator based clock generation. Second, the paper analyzes non-ideal CDC effect in a gate dominated critical path and wire dominated clock tree design. The paper shows the delay sensitivity mismatch between clock tree and critical path can degrade CDC effect by analyzing timing slack under power supply noise (PSN). Finally, the paper proposes simple but efficient clock tree synthesis (CTS) technique to maximize timing slack under PSN in digital circuits with adaptive clock generation.