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This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full adder allows the production of sum and carry outputs based on the adder inputs regardless of the carry input when the spacer is supplied. When utilized in a ripple carry adder (RCA) architecture, the proposed full adder achieves significant reductions in design metrics, such as cycle time, area, and power, compared to existing IOM asynchronous full adders. For a 32-bit RCA implementation using a 28 nm CMOS technology, the proposed full adder outperforms an existing state-of-the-art high-speed asynchronous full adder by reducing the cycle time by 10.4% and the area by 15.8% for RtZ handshaking and reduces the cycle time by 9.8% and the area by 15.8% for RtO handshaking without incurring any power penalty. Further, in terms of the power-cycle time product, which serves as a representative measure of energy, the proposed full adder yields an 11.8% reduction for RtZ handshaking and an 11.2% reduction for RtO handshaking. [ABSTRACT FROM AUTHOR]

Inaccurate computing is found to be a high-speed, low-power and energy-efficient alternative to accurate computing for error-tolerant applications. In this context, this paper analyzes the usefulness of inaccurate computing for a digital image processing application, viz. digital image blending, which has been less explored. We analyze the use of inaccurate addition for image blending used in applications such as photo editing and computer graphics. For experimentation, we considered blending two digital images using accurate and inaccurate addition separately. We considered many inaccurate addition architectures which are suitable for implementation in both FPGA and ASIC design environments to perform a comparative analysis. We found that an inaccurate addition with an optimum inaccuracy produces a similar quality of blended image as obtained using accurate addition. The quality of blended images is quantified using standard metrics such as the peak signal-to-noise ratio and the structural similarity index measure. In particular, an inaccurate adder, M-HERLOA, was found to be preferable for image blending from the combined perspectives of quality of blended image, error metrics and design metrics. We implemented the accurate and inaccurate adders corresponding to an optimum inaccuracy in FPGA and ASIC design environments. We considered a Xilinx Artix-7 FPGA for an FPGA-based implementation and a 32/28 nm CMOS standard digital cell library for an ASIC type standard cell-based implementation. The results show that, for an FPGA-based implementation, M-HERLOA enables a reduction in delay by 13%, requires 50% fewer LUTs and 49% fewer registers and consumes 24.3% less on-chip power compared to the accurate high-speed FPGA adder while yielding a blended image of good quality. For an ASIC type standard cell-based implementation, M-HERLOA enables a reduction in delay by 64.6% (24.4%), requires 43% (82.4%), less area and dissipates 63% (67.8%) less power than the accurate carry ripple adder (carry look-ahead adder). [ABSTRACT FROM AUTHOR]

Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology. [ABSTRACT FROM AUTHOR]

Low power is an essential requirement for suitable multimedia devices, image compression techniques utilizing several signal processing architectures and algorithms. In numerous multimedia applications, human beings are able to congregate practical information from somewhat erroneous outputs. Therefore, exact outputs are not necessary to produce. In digital signal processing system, adders play a vital role as an arithmetic module in fixing the power and area utilization of the system. The trade-off parameters such as area, time and power utilization and also the fault tolerance environment of few applications have been employed as a base for the adverse development and use of approximate adders. In this paper, various types of existing adders and approximate adders are analyzed based on the area, delay and power consumption. Also, an approximate, high speed and power efficient adder is proposed, which yields better performance than that of the existing adders. It can be used in various image processing applications and data mining, where the accurate outputs are not needed. The existing and proposed approximate adders are simulated by using Xilinx ISE for time and area utilization. Power simulation has been done by using Microwind Software. [ABSTRACT FROM AUTHOR]

A $V$ -band low-dc-power wide-locking-range divide-by-6 injection-locked frequency divider (ILFD) using a 90-nm CMOS process is proposed in this letter. The proposed innovative topology is composed of current-reused oscillation cores with transformer coupling. Moreover, the dc bias of the injectors can be properly applied to widen the locking range (LR). With a core dc power of 5.6 mW and an input power of −5 dBm, the measured maximum locking is 5.6 GHz (9.8%) from 54.5 to 60.1 GHz. When compared to the previously reported $V$ -band ILFDs, this work features a high division ratio, low dc power, wide LR, and good sensitivity. [ABSTRACT FROM AUTHOR]

A 50-Gb/s four-level pulse-amplitude modulation (PAM4) silicon photonic transmitter is presented, which is composed of a 40-nm bulk CMOS driver hybrid integrated with a 180-nm silicon-on-insulator (SOI) CMOS Mach–Zehnder modulator (MZM). To recover and demodulate 50-Gb/s PAM4 data into dual-25-Gb/s nonreturn to zero (NRZ) streams for the co-designed MZM digital-analog converter (DAC), a reference-less clock and data recovery (CDR) is integrated, and to achieve high swing and high speed, the driver is made in a distributed amplifier (DA), employing push–pull cells that are grouped in three segments. A digital-assisted distributed driver (DADD) that replaces the input T-line by segmented 2:1 multiplexers and buffers is, thus, proposed. Precise time gating in each segment allows for velocity match in both the DA and optical DAC, as well as the in-segment pre-emphasis without power-hungry analog delay stages. Measurement results show that the driver and CDR achieve 4-VPP differential swing, 1.19-ps rms jitter, and 1.34-W power consumption at 50 Gb/s. An optical transmitter is demonstrated by wire-bonding the driver to the MZM DAC, achieving 50-Gb/s PAM4 output with 6.35-ps rms jitter and improved linearity. [ABSTRACT FROM AUTHOR]

To meet the demand for low-voltage/low-power and high speed analog-to-digital convertors, a new fully differential double-tail dynamic comparator is proposed. To reduce the power dissipation and speed up the comparison process, charge sharing technique has been used in the latch stage of the proposed dynamic comparator. In addition, differential pair and double-tail dynamic comparator topologies are combined to minimize the offset voltage. The proposed dynamic comparator has worst case delay of 0.219 ns, power dissipation of 156.3 μW and offset voltage of 0.184 mV with 1σ deviation of 7.65 mV. The proposed dynamic comparator has been simulated in 0.18 μm CMOS technology with supply voltages of ± 0.75 V using Cadence virtuoso analog design environment. [ABSTRACT FROM AUTHOR]

Static or leakage power is the dominating component of total power dissipation in deep nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm to 54% at 65 nm technology due to continued device and voltage scaling. Static random access memory (SRAM) is a type of RAM in which data is not written permanently and it does not need to be refreshed periodically. Different techniques have been applied to SRAM cell to reduce leakage power without affecting its performance. A novel 10T SRAM architecture is proposed in this paper which operates in three modes (active, park, standby or hold). The main objective of the proposed architecture is to provide better stability and reduced delay in active mode, reduced leakage current in standby mode and retaining the logic state in park mode. Design metrics such as static and dynamic power, delay, power delay product, energy, energy delay product, rise and fall time, slew rate and static noise margin are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that the proposed SRAM is much better than conventional and other SRAM cells designed using hybrid techniques. [ABSTRACT FROM AUTHOR]

Given the continuing miniaturization of underlying transistors, electronic functional units (circuits/systems) become increasingly susceptible to high-energy radiation, encountered in applications like space. Hence, redundancy is employed as a radiation hardening by design strategy to cope with faults of functional units used in such applications and to maintain their correct operation. Triple modular redundancy (TMR), which is a subset of N-modular redundancy (NMR), that can mask any single fault or a faulty functional unit has been widely used. However, compared to a simplex implementation a TMR implementation requires two additional functional units and a majority voting logic therefore a TMR implementation's area and power overheads are greater by over 200 %. This is burdensome for resource-constrained applications like space where low power and energy efficiency are important considerations. This paper presents a new redundancy strategy involving approximate computing called RESAC for error-tolerant applications such as digital image/video/audio processing, which is used in space systems. We evaluated the feasibility of RESAC for an image processing case study and the results confirm the usefulness. For implementation using a 28-nm CMOS technology, RESAC achieves reductions in area, delay, and power by 22.3 %, 15.3 %, and 24.9 % compared to TMR. Nonetheless, RESAC can address any NMR. • A novel redundancy scheme utilizing approximate computing called RESAC is proposed. • RESAC is suitable for use in inherently error-tolerant applications like digital signal processing. • A comparison between TMR and RESAC is performed for a digital image processing application. • RESAC produces images of good quality comparable to those produced by TMR. • For implementation, RESAC achieves 22.3 % reduced area, 15.3 % reduced delay, and 24.9 % reduced power compared to TMR. [ABSTRACT FROM AUTHOR]

This paper describes a digital-mapping direct digital frequency synthesizer having a tuning and amplitude resolutions of 24 and 10 bits, respectively. This Si-CMOS-monolithic microwave-integrated circuit (MMIC) is the first solution supporting a sampling rate of 7 GS/s with frequency modulation, phase modulation (PM), and amplitude modulation (AM) in the digital domain. It includes a 14 bits pipelined ripple-carry phase adder and a 10-bits high-speed amplitude multiplier. The minimum frequency, phase, and amplitude steps are 417.2 Hz, 0.022°, and 1.17 mV, respectively. A proof-of-concept chip with an active area of 0.23 mm2 was fabricated in a 1P9M 65-nm CMOS process and characterized in low-profile quad flat package (LQFP). The worst case wideband/narrowband spurious-free dynamic range is 32/42 dBc. This system consumes 85.9 mW/(GS/s) from a 1.2-V power supply when the PM/AM are enabled, resulting in an figure of merit (FoM) of 469.6 GS/ $\text {s}\cdot {2}^{(\mathrm {SFDR}/6)}$ /W. The absolute single sideband phase noise at 100 KHz offset from the carrier was better than −125 dBc/Hz in all the evaluated frequencies. A latency of 12.86 ns was measured when operating at 7 GS/s. [ABSTRACT FROM AUTHOR]

Asynchronous quasi-delay-insensitive (QDI) implementation of approximate addition is described in this article. The objective is to provide an insight into the optimization in design metrics that can be achieved with approximate addition compared to accurate addition based on a QDI implementation by considering a practical digital image processing application. For the QDI implementation, some approximate adder architectures are considered which are deemed suitable for both ASIC and FPGA based implementations. The accurate and approximate adders considered are of size 32-bits. The delay-insensitive dual-rail code was used for data encoding, and four-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols were used separately for data communication. The implementations used a 32/28-nm complementary metal oxide semiconductor (CMOS) technology. The simulation results show that an approximate adder HOERAA achieves a 19.7% reduction in cycle time, a 12.5% reduction in area, and an 17.7% reduction in energy compared to the accurate adder for RTZ handshaking. For RTO handshaking, HOERAA achieves an 18.7% reduction in cycle time, a 12.4% reduction in area, and a 16.6% reduction in energy compared to the accurate adder. Another approximate adder HEAA achieves a 19.7% reduction in cycle time, a 12.9% reduction in area, and a 20.2% reduction in energy, compared to the accurate adder for RTZ handshaking. For RTO handshaking, HEAA achieves an 18.7% reduction in cycle time, a 12.9% reduction in area, and a 19.2% reduction in energy compared to the accurate adder. Nevertheless, the RTO handshaking is preferable to RTZ handshaking as the former facilitates slightly better optimizations in design metrics compared to the latter. The mean absolute error (MAE) and the root mean square error (RMSE), which are popular error metrics used in approximate computing, were calculated for the approximate adders and are given for a comparison. While the MAE of HOERAA and HEAA are comparable, HOERAA has 8.6% reduced RMSE compared to HEAA. Digital image processing results based on accurate and approximate additions are also given, to substantiate the usefulness of approximate addition.

This paper presents a power-efficient CMOS frequency divider (FD) with wide-band programmable division ratio and quadrature outputs for high-speed data transmission applications. The proposed FD consists of a power-efficient programmable divider (PD), a complementary volt-age-to-time converter based duty-cycle correction circuit, and a compact quadrature divider (QD). In the chain of PD, a sense-amplifier based dynamic flip-flop is proposed for 2/3 divider cell to achieve high-speed operation with significantly reduced power consumption. In addition, a simple but effective QD based on two pseudo-differential voltage-controlled tri-state inverters, is beneficial for generating precise quadrature output signals. Measurement results in 40-nm CMOS process show that the proposed FD achieves a wide division range from 16 to 254 and operates up to 14.8 GHz while consuming the power of 540.6 μW at 1.1-V supply, and occupying the active area of 0.00267 mm (114.6 μm × 23.3 μm). [ABSTRACT FROM AUTHOR]

This paper presents a high speed CMOS hybrid comparator with reduced delay time and improved energy efficiency. The proposed hybrid comparator includes two stages with three stacked transistors which are suitable for low-voltage operation. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, while enhancing the positive feedback to reduce the discharging time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain the transconductance, thus reducing the latching time with negligible static power, while needing no additional clock signal. Therefore, the delay time and energy per conversion are both significantly reduced in the proposed hybrid comparator. Measurement results in 40-nm CMOS process show that the proposed hybrid comparator operates up to 6 GHz with 61.08-ps delay time. The power consumption is 345.9 $$\upmu $$ W at 1.1-V supply, while the occupied die area is 64.5 $$\upmu $$ m $$^2$$ (7.5 $$\upmu $$ m $$\times $$ 8.6 $$\upmu $$ m). [ABSTRACT FROM AUTHOR]

Averaging of accumulated data is a standard technique applied to processing data with low signal-to-noise ratios (SNR), such as image signals captured in ultra-high-speed imaging. The authors propose an architecture layout of an ultra-high-speed image sensor capable of on-chip signal accumulation. The very high frame rate is enabled by employing an image sensor structure with a multi-folded CCD in each pixel, which serves as an in situ image signal storage. The signal accumulation function is achieved by direct connection of the first and the last storage elements of the in situ storage CCD. It has been thought that the multi-folding is achievable only by driving electrodes with complicated and impractical layouts. Simple configurations of the driving electrodes to overcome the difficulty are presented for two-phase and four-phase transfer CCD systems. The in situ storage image sensor with the signal accumulation function is named Image Signal Accumulation Sensor (ISAS).

Mid-wavelength infrared (MWIR) thermography is an emerging technology with promising applications such as industrial monitoring, medicine and automotive, but its use in high-speed cameras is not yet widespread due to the lack of inexpensive sensor integration solutions and their common reliance on bulky cooling mechanisms. This work fills the gap by presenting a monolithic uncooled high-speed imager based on vapor-phase deposition lead selenide (VPD PbSe) photoconductors and a fully digital and configurable CMOS read-out integrated circuit (ROIC) to operate the MWIR imager. This ROIC features cancellation of PbSe dark current, compensation of its output capacitance and correction of the fixed pattern noise (FPN) caused by process non-uniformities in CMOS fabrication and detector deposition. The low-cost 80 × 80 imager has been integrated using 0.35 µm 2P4M standard CMOS technology and PbSe detector post-processing with 135 µm pixel pitch and 68% fill factor values. Experimental opto-electrical performance exhibits 10 bit real-time FPN compensation and DR calibration over the entire focal plane operating at 2 kfps, sub-0.5 LSB inter-pixel crosstalk, sub-µW pixel power consumption, and an overall figure of merit of 55 mK × ms. [ABSTRACT FROM PUBLISHER]

A $V$ -band 90-nm CMOS divide-by-10 injection-locked frequency divider (ILFD) is proposed using current-reused topology in this letter. The proposed circuit is composed of a divide-by-5 ILFD and a source injection current-mode logic (SICML) divide-by-2 frequency divider. The cascoded topology of SICML and ILFD is employed to reduce dc power consumption and increase frequency division ratio. With an input power of 0 dBm, the measured maximum locking range (LR) is 5 GHz from 60.3 to 65.3 GHz. Compared with the reported CMOS microwave and millimeter-wave ILFDs, the proposed ILFD features wide LR, good sensitivity, and a high division ratio of up to ten. [ABSTRACT FROM PUBLISHER]

A gate array has a great advantage in that the extra cost required for customizing VLSI masks is low and the lead time needed to obtain an ASIC is short. Hence, it is widely and generally used in the ASIC industry as a major semicustomized VLSI design methodology. This paper presents high-density RAM/ROM macros using memory-oriented CMOS gate-array base cells. The metatile methodology along with a hierarchical verification technique is used for macro design; all the interconnection wires needed to generate a RAM/ROM macro are installed in each physical leaf cell by way of preparation. The macro size is configurable regarding both word count and bit width. Moreover, back annotations after generating a macro are not necessary because there are no unknown factors such as parasitic resistance and/or capacitance. To reduce the power consumption of RAM/ROM macros, six narrow-channel MOSFETs (two pMOSs and four nMOSs) are prepared in the base cell, resulting in a new 10-transistor-type base cell. Using one single base cell, we can implement an SRAM cell (up to two ports), a 4-bit ROM cell, or a 2-input logic gate. When designing the ROM cell, we adopt a double-rail bitline scheme to shorten the bitline delay. Another high-speed technique is to use a new current-mirror sense amplifier. Owing to the high sensitivity (47 mV) of this amplifier, we have successfully reduced the required read bitline signal from 300 to 100 mVpp. With regards to layout techniques, we propose a new high-density address decoder using a subdecoder and complex logic gates. In addition, some verification techniques using phantom base cells are devised. These techniques are confirmed with a gate-array RAM/ROM macro test chip fabricated with a 0.6- \mu \textm low cost, CMOS process. With a two-port SRAM with 256 cells/bitline, the address access time under typical conditions of 3.3 V and 25 °C is 7.125 ns and the power-supply current at a 40-MHz operation is 3.8 mA for an I/O-data width of 1 bit. [ABSTRACT FROM AUTHOR]

Many of the current wireline networks are digitalized. In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and application data are transferred with a synchronous transfer module (STM). This paper presents an STM-16 frame termination VLSI fabricated with a 0.3- \mu m quintuple-metal CMOS/SIMOX process. To reduce power consumption, we employ a multi- V_{\rm DD} architecture using 2- and 1-V power supplies. Also, fully depleted silicon on insulator (FD-SOI) devices are used to obtain a higher operating speed and to reduce dynamic power dissipation. To install another powerline in every standard cell without increasing the cell size, a stacked multiple powerlines scheme is proposed. In addition, some dedicated standard cells are developed to convert the logical high level without degrading the signal integrity. With regards to hard macros, 2-V MUX/DEMUX macros achieve a high operating speed of 2.5 Gb/s, while a dual-port SRAM macro can operate at a low supply voltage of 1 V. Moreover, 2-V 50- \Omega $ -terminated input/output buffers using a new direct-drive amplifier operate without dedicated power supplies. With our STM-16 frame termination VLSI, the power consumption during the standby is 34 mW, and that for 2.5-Gb/s operation is 1.2 W at 25 °C. [ABSTRACT FROM AUTHOR]

A 9 bit 11 GS/s DAC is presented that achieves an SFDR of more than 50 dB across Nyquist and IM3 below -50 dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. Despite requiring two current-steering DACs for the interleaved architecture, the relative low demands on performance of these sub-DACs imply that they can be implemented in an area and power efficient way. Together with a quad-switching architecture to decrease demands on the power supply and bias generation and employing the multiplexer switches in triode, the total core area is only 0.04 mm 2 while consuming 110 mW from a single 1.0 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-cost 45-GHz on–off keying (OOK) transceiver system in 90-nm CMOS for high-speed short-range wireless communications. The system includes a transmitter (Tx), a receiver (Rx), and two on-board substrate integrated waveguide fed Yagi–Uda antennas. The Tx provides about 7 dBm of output power and better than 50-dB on/off isolation while consuming 61.6 mW of dc power. The Rx performs noncoherent demodulation with a power consumption of 53.6 mW. The on-board antennas are integrated with the Tx and Rx using carefully designed broadband wire-bond interconnections, resulting in a low-cost system integration. The proposed transceiver achieves error-free operation (bit error rate <\10^-12) of 4-Gb/s data rate over a distance of 55 cm, which results in a bit energy efficiency per distance (BEEPD) of 0.52 pJ/bit/cm. To our best knowledge, this work shows the highest on/off isolation among the OOK Txs, the longest transmission distance, and the best BEEPD among the OOK transceivers reported to date in the millimeter-wave frequency band. [ABSTRACT FROM PUBLISHER]

Abstract: A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4LSBs and −0.9/0.8 LSBs, respectively. At 660MS/s sampling rate, the ADC consumes 7.6mW from a 1.2V supply. The proposed SAR ADC׳s SNDR and SFDR are 49.5dB and 64.2dB, respectively. [Copyright &y& Elsevier]

In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of ‘weak 0’ existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both ‘good 1’ and ’good 0’. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 µm technology while the prior circuit can only operate under 250 MHz at the same time. [ABSTRACT FROM PUBLISHER]

We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high-k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros. [ABSTRACT FROM PUBLISHER]

To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including high-speed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness. [ABSTRACT FROM PUBLISHER]

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs. [ABSTRACT FROM AUTHOR]

A 40 nm CMOS digital-to-analog converter (DAC) based multimode transmitter (MMTX) is presented. The transmitter can be operated in either narrow- or wideband applications. It has a maximum 2.2 GHz signal bandwidth and exhibits an in-band IM3 of less than -58 dBc. The MMTX consists of a current-steering DAC with digital sinc equalization and rolloff compensation. By implementing high-speed, feed-forward pipelined digital logic and a distributed decoder, the DAC sampling rate extends to 5 GHz. A distributed regulator approach ensures preservation of the achieved wideband linearity in noisy embedded SoC environments. The MMTX can deliver up to +11 dBm of output power and exhibits 20 dB of analog power backoff with 1 dB steps and a precision better than \pm0.1 dB. The MMTX consumes only 375 mW and occupies 1.65 mm^2. [ABSTRACT FROM PUBLISHER]

We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5–10 typically and 30–190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20–80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 \mu\ m high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed. [ABSTRACT FROM AUTHOR]

The use of multiple power supplies with different output voltages has a great advantage in that it makes it possible to realize high performance ULSIs with low power dissipation. This paper presents a high-speed low-power SRAM that employs three power supplies (1, 2, and 3.3 V). A 1-V power supply is mainly used in the SRAM core to save standby and/or active power, while a 2-V supply is used in critical components to realize high performance. The voltage applicable to each MOSFET is up to 2.2 V because of the use of a 5-nm ultrathin gate oxide, and so the 3.3-V power supply is used only for LV-TTL level I/O buffers. Secure write operation for 1-V six-transistor memory cells is guaranteed by using a new switched powerline impedance scheme. To reduce dynamic write power dissipation, a segmented bitline scheme is adopted and long global bitlines are assigned to the 4th (topmost) metal layer. The data stored in memory cells are read out via virtual-GND lines by sensing the change in current volume. The practical use of parasitic bipolar action in SOI MOSFETs is being actively considered as a way of obtaining a large read current from memory cells. In addition, a 1-V double-rail bidirectional intradatabus is developed for transferring multibit high-speed data between the SRAM core and I/O buffers. A 32K-word\,\times\,9-bit SRAM chip, fabricated with the 0.2-\mum-gate CMOS/SIMOX process, has achieved a 7.5-ns address access time for 65-pF external loads. The power dissipation during standby is less than 0.3 mW and the values for 100-MHz operation are 5.8~mW (write) and 11.0 mW (read), excluding that of the 3.3-V I/O buffers. [ABSTRACT FROM PUBLISHER]

The article proposes a technique that exploits a transformer based shunt-double series peaking method with interleaving active feedback to realize a 20-Gb/s optical receiver in a 0.13υm complementary metal oxide semiconductor (CMOS) process which enhances the bandwidth with much less sacrifice of the chip area. The CMOS process realized the 20-Gb/s current mode optical receiver and the source degeneration and the interleaving active feedback techniques are utilized. It demonstrates superior performance than high speed CMOS optical receiver.

Averaging of accumulated data is a standard technique applied to processing data with low signal-to-noise ratios (SNR), such as image signals captured in ultra-high-speed imaging. The authors propose an architecture layout of an ultra-high-speed image sensor capable of on-chip signal accumulation. The very high frame rate is enabled by employing an image sensor structure with a multi-folded CCD in each pixel, which serves as an in situ image signal storage. The signal accumulation function is achieved by direct connection of the first and the last storage elements of the in situ storage CCD. It has been thought that the multi-folding is achievable only by driving electrodes with complicated and impractical layouts. Simple configurations of the driving electrodes to overcome the difficulty are presented for two-phase and four-phase transfer CCD systems. The in situ storage image sensor with the signal accumulation function is named Image Signal Accumulation Sensor (ISAS). [ABSTRACT FROM AUTHOR]