A low power and high speed approximate adder for image processing applications.

Low power is an essential requirement for suitable multimedia devices, image compression techniques utilizing several signal processing architectures and algorithms. In numerous multimedia applications, human beings are able to congregate practical information from somewhat erroneous outputs. Therefore, exact outputs are not necessary to produce. In digital signal processing system, adders play a vital role as an arithmetic module in fixing the power and area utilization of the system. The trade-off parameters such as area, time and power utilization and also the fault tolerance environment of few applications have been employed as a base for the adverse development and use of approximate adders. In this paper, various types of existing adders and approximate adders are analyzed based on the area, delay and power consumption. Also, an approximate, high speed and power efficient adder is proposed, which yields better performance than that of the existing adders. It can be used in various image processing applications and data mining, where the accurate outputs are not needed. The existing and proposed approximate adders are simulated by using Xilinx ISE for time and area utilization. Power simulation has been done by using Microwind Software. [ABSTRACT FROM AUTHOR]