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Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process.
- Source :
-
IEEE Transactions on Electron Devices . Nov2013, Vol. 60 Issue 11, p3625-3631. 7p. - Publication Year :
- 2013
-
Abstract
- To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including high-speed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 60
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 91553882
- Full Text :
- https://doi.org/10.1109/TED.2013.2279408