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The demand for miniaturized point‐of‐care chemical/biochemical sensors has driven the development of field‐effect transistors (FETs) based pH sensors over the last 50 years. This paper aims to review the fabrication technologies, device structures, sensing film materials, and modeling techniques utilized for FET‐based pH sensors. We present the governing principles of potentiometric sensors, with major focus on the working principles of ion‐sensitive FETs (ISFETs). We extensively review different sensing film materials deposited by various techniques, which is critical to the sensing performance of ISFETs. The popular fabrication technologies have been presented, with special emphasis on state‐of‐the‐art silicon‐on‐insulator based technology, which can achieve high sensitivity by utilizing the dual‐gate effect. Furthermore, recent advancements in nano‐ISFETs has been elucidated. We also discuss the adoption of unmodified complementary metal‐oxide semiconductor (CMOS) ISFETs using standard CMOS processes, which has enabled the fabrication of integrated ISFET arrays, which are especially suited for ion‐imaging applications. Moreover, recent developments in extended‐gate FETs has been discussed, which have gained lot of attention due to their design flexibility and ease of fabrication, which is desirable for wearable sensing applications. In addition, recently there have been efforts to utilize nonsilicon channel materials for pH‐sensing application to obtain superior performance and various channel materials have been reviewed. Finally, we have extensively reviewed the ISFET device modeling and simulation techniques using various computer‐aided design tools, which aid in sensor design and characterization. [ABSTRACT FROM AUTHOR]

Abstract The demand for miniaturized point‐of‐care chemical/biochemical sensors has driven the development of field‐effect transistors (FETs) based pH sensors over the last 50 years. This paper aims to review the fabrication technologies, device structures, sensing film materials, and modeling techniques utilized for FET‐based pH sensors. We present the governing principles of potentiometric sensors, with major focus on the working principles of ion‐sensitive FETs (ISFETs). We extensively review different sensing film materials deposited by various techniques, which is critical to the sensing performance of ISFETs. The popular fabrication technologies have been presented, with special emphasis on state‐of‐the‐art silicon‐on‐insulator based technology, which can achieve high sensitivity by utilizing the dual‐gate effect. Furthermore, recent advancements in nano‐ISFETs has been elucidated. We also discuss the adoption of unmodified complementary metal‐oxide semiconductor (CMOS) ISFETs using standard CMOS processes, which has enabled the fabrication of integrated ISFET arrays, which are especially suited for ion‐imaging applications. Moreover, recent developments in extended‐gate FETs has been discussed, which have gained lot of attention due to their design flexibility and ease of fabrication, which is desirable for wearable sensing applications. In addition, recently there have been efforts to utilize nonsilicon channel materials for pH‐sensing application to obtain superior performance and various channel materials have been reviewed. Finally, we have extensively reviewed the ISFET device modeling and simulation techniques using various computer‐aided design tools, which aid in sensor design and characterization.

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanosheet stacked channels provided superior process integration robustness compared to Nanowire-On-Fin stacked channels. For the Nanowire-On-Fin option, using an SOI substrate as the starting material (compared to Si bulk or DSOI) also strongly reduced process variation failure rates.

High Q-factor inductors are critical in designing high performance RF/microwave circuits on SOI technology. Substrate losses is a key limiting factor when designing inductors with high Q-factors. In this context, we report a substrate engineering method that enables improvement of quality factors of already fabricated inductors on SOI. A novel femtosecond laser milling process is utilized for the fabrication of locally suspended membranes of inductors with handler silicon completely etched. Such flexible membranes suspended freely on the BOX show up to 92 % improvement in Q-factor for single turn inductor. The improvement in Q-factor is reported on large sized inductors due to reduced parallel capacitance which allows enhanced operation of inductors at high frequencies. A compact model extraction methodology has been developed to model inductor membranes. These membranes have been utilized for the improvement of noise performance of LNA working in the 4.9 - 5.9 GHz range. A 0.1 dB improvement in noise figure has been reported by taking an existing design and suspending the input side inductors of the LNA circuit. The substrate engineering method reported in this work is not only applicable to inductors but also to active circuits, making it a powerful tool for enhancement of RF devices.

This article presents a 148-GHz coupled loop fundamental oscillator with a quad-feed octagonal slot antenna. The proposed loop configuration with a multi-feed antenna leads to each oscillator experiencing multiple injected signals. An analysis is performed to explain the dynamics of the coupled loop oscillator in the presence of multiple signal-injection paths. It is shown that the proposed oscillator configuration will only operate with $- \pi /2$ phase between the adjacent oscillators. This phase difference is necessary for the quad-feed antenna to combine and radiate the output power from the four single-ended oscillators in the loop. The output from each oscillator is ac coupled to the following oscillator stage using a phase compensating capacitor, whose value is selected to enhance the oscillation frequency of the coupled loop. The use of buffer stages is avoided in favor of a passive power feed network for extraction of the output power from each oscillator. The proposed oscillator is fabricated in a 22-nm FDSOI process and has a 0.5-mm2 chip area. The measured peak effective isotropic radiated power (EIRP) of the oscillator is 9.7 dBm with a corresponding dc-EIRP efficiency of 34.3% when operating from a 0.8-V supply. To the authors’ knowledge, this dc-EIRP efficiency is the highest among reported oscillators to date operating between 100 and 200 GHz. [ABSTRACT FROM AUTHOR]

Thinned CMOS chips transfer-bonded onto a compliant host substrate remain to date the technology of choice for applications requiring both mechanical flexibility and high frequency operation. However, the use of poorly thermally conductive host substrates raises the problem of thermal management of flexible electronics, a topic poorly addressed in literature. In this letter, we report the analysis of flexible SOI-CMOS chips ultimately-thinned-and-transfer-bonded (UTTB) onto polyimide and copper substrates. While the temperature remains limited to ~68°C on the native silicon substrate or after transfer onto a copper host substrate, infrared thermography reveals temperature peaks of up to 118°C on polyimide. The impact of self-heating in flexible SOI-CMOS is correlated with electrical performance for the three types of substrates. Beyond the property of mechanical flexibility it provides, a copper substrate is shown to slightly strengthen electrostatic integrity while maintaining a thermal landscape close to that of silicon.

In this brief, designs of two millimeter wave (mmWave) reconfigurable multi band low noise amplifiers (LNA) are presented targeted for fifth generation (5G) communications. A reconfigurable tunable load based on electrical and magnetic tuning is proposed to cover three mmWave frequency bands for 5G, i.e., 24 GHz, 28 GHz and 39 GHz. Two LNA structures are designed and fabricated using 45nm CMOS SOI technology. The first toplogy (LNA1) is composed of a single input wideband matching circuit to cover frequency operations from 24 GHz to 40 GHz. On the other hand, second topology (LNA2) uses three separate narrowband match inputs, one for each frequency band, with combined output. Design methodology of passive and active devices is presented towards compact integration of LNAs for systems such as, phased arrays. Ground plane and its impact on the performance parameters is also discussed in this brief. Measurement results show a wideband noise figure (NF) ranging from 3.8 dB to 4.9 dB and gain of 8.5 dB to 12.5 dB for LNA1 at different bands. Similarly, LNA2 exhibits NF of 4.5 dB to 5.5 dB and gain of 9.5 dB to 15.5 dB across all bands. Total area (including pads) of LNA1 and LNA2 are 0.316 $mm^{2}$ and 0.695 $mm^{2}$ , respectively. [ABSTRACT FROM AUTHOR]

Process and parametric variation negatively impact the performance and yield of analog and digital circuits in advanced nodes. To alleviate this effect, we propose a technique to electrically adjust the threshold voltage of CMOS transistors in a post-fabrication setting in a non-volatile manner. This technique, which relies on self-heating assisted trapping of charge in high-k gate dielectric (e.g. HfOx) used in advanced CMOS nodes, does not require any extra fabrication step. In this letter, we use charge trapping for wideband non-volatile frequency tuning of a ring oscillator. We have demonstrated that the frequency of the ring oscillator can shift from 2075MHz to 1746MHz, when a supply voltage of 0.8V is used. This work serves as a foundation for non-volatile tuning, reconfiguration, and obfuscation of chips and IP blocks. The chip was fabricated in GlobalFoundries 22nm Fully-Depleted Silicon-on-Insulator (FDSOI) CMOS process. [ABSTRACT FROM AUTHOR]

Increased parasitic components in silicon-based nanometer (nm) scale active devices have various performance trade-offs between optimizing the key parameters, for example, maximum frequency of oscillation ( f max , gate resistance and capacitance, etc. A common-source cascode device is commonly used in amplifier designs at RF/millimeter-wave (mmWave) frequencies. In addition to intrinsic parasitic components, extrinsic components due to wiring and layout effects, are also critical for performance and accurate modelling of the devices. In this work, a comparison of two different layout techniques for cascode devices is presented to optimize the extrinsic parasitic elements, such as gate resistance. A multi-gate or multi-port layout technique is proposed for optimizing the gate resistance ( r g ). Extracted values from measurement results show reduction of 10% in r g of multi-gate layout technique compared to a conventional gate-above-device layout for cascode devices. However, conventional layout exhibits smaller gate-to-source and gate-to-drain capacitances which leads to better performance in terms of speed, i.e. f max . An LNA is designed at 40 GHz frequency using proposed multi-gate cascode device. LNA achieves a measured peak gain of 10.2 dB and noise figure of 4.2 dB at 40 GHz. All the structures are designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technology. [ABSTRACT FROM AUTHOR]

We report on ultraviolet (UV) sensors employing high voltage PIN lateral photodiode strings integrated into the production RF SOI (silicon on isolator) CMOS platform. The sensors were optimized for applications that require measurements of short wavelength ultraviolet (UVC) radiation under strong visible and near-infrared lights, such as UV used for sterilization purposes, e.g., COVID-19 disinfection. Responsivity above 0.1 A/W in the UVC range was achieved, and improved blindness to visible and infrared (IR) light demonstrated by implementing back-end dielectric layers transparent to the UV, in combination with differential sensing circuits with polysilicon UV filters. Degradation of the developed sensors under short wavelength UV was investigated and design and operation regimes allowing decreased degradation were discussed. Compared with other embedded solutions, the current design is implemented in a mass-production CMOS SOI technology, without additional masks, and has high sensitivity in UVC.

For the silicon photonic links to meet the target bit error rate (BER), the laser source must output enough optical power to overcome the optical channel loss and limited receiver sensitivity. Combined with poor wall-plug efficiency, this optical power requirement makes the electrical power consumed by the laser source a significant portion of the link energy cost. This article proposes a laser-forwarded coherent link that greatly reduces the required laser optical power by averaging optical path loss between the main and forwarded paths and by improving the receiver sensitivity using a homodyne coherent detector. The link performance analysis reveals that the laser forwarded link improves the laser power budget by ≈6–8 dB compared with a conventional intensity-modulation/direct detection link using typical photonic link components. To demonstrate the laser forwarded link, a microring resonator phase modulator, a balanced detector, and a 3-dB coupler are integrated with CMOS circuits in a GFUS 45-nm SOI process. The transmit driver and the receiver consume 40 and 450 fJ/bit, respectively. Aided by ≈8-dB boost from laser forwarding and the coherent detection gain, the receiver achieves −15.6-dBm optical modulation amplitude sensitivity. The link operates at 10 Gb/s with BER < 10−9 and electrical energy efficiency of 2.3 pJ/bit. [ABSTRACT FROM AUTHOR]

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

This paper presents the analysis and design of wideband I/Q CMOS modulators and transmitters. Non-idealities and performance limitations of Cartesian transmitter and modulator systems are discussed, and circuit design techniques and analyses are shown. A DC-60 GHz I/Q modulator/transmitter chip in 45-nm SOI CMOS is presented as a critical building block for next-generation multi-standard and high-capacity wireless backhaul links. The modulator consists of a wideband quadrature signal generator, wideband buffers, and two current-combined DC-100 GHz low-noise double-balanced mixers driven in quadrature. The 1.4 mm2 modulator chip achieves 60 dB of dynamic range in a 1-GHz bandwidth, with an OP1dB of ~ −10 dBm, thus enabling spectrally efficient high-order modulation schemes such as 256-QAM. The I/Q modulator achieves 200 Gb/s in 16-QAM (50 Gbaud/s) while consuming 200 mW, resulting in record 1-pJ/bit modulation efficiency. In addition to backhaul links, the modulator is an attractive and cost-effective alternative to short-range optical links for data center interconnects (DCI) and for chip-to-chip communications. [ABSTRACT FROM AUTHOR]

This paper presents a high-sensitivity, fully differential (FD) optical receiver (RX) for high-density system-on-chip applications. The high digital activity prominent in such applications creates common-mode and power-supply noise, which degrades the optical RX sensitivity. To suppress these noise sources and enhance the RX sensitivity, an optical RX is proposed that realizes FD operation by using a new resonant split-microring photodetector. The complete RX is implemented in a 45-nm SOI CMOS with no process changes. When aptly biased, the detector outputs FD photocurrent with <±0.3% splitting error. It has 0.52-A/W responsivity and a bandwidth of 5.0 GHz. The RX circuit is optimized to achieve BER < 10−12 at 12 Gb/s with an optical modulation amplitude (OMA) sensitivity of −18.2 dBm while consuming 7 mW. Compared with a conventional single-ended RX on the same test-chip, the proposed RX improves sensitivity from 13 to 7.9 $\mu \text{A}_{\mathrm {pp}}$ without reducing the bandwidth or significantly impacting the RX energy efficiency. [ABSTRACT FROM AUTHOR]

Abstract We report on total ionizing dose effects on the X-ray SOI pixel sensor, XRPIX. XRPIX has been developed as an imaging spectrometer for X-ray astronomical use in space. Front- and back-illuminated (FI and BI) devices were irradiated with hard X-rays from an X-ray tube operated at 30 kV with a Molybdenum target. We found that the degradation rate of the readout noise of the BI device was approximately three times slower than that of the FI device as a function of radiation exposure. Those of both type of devices, however, were virtually identical when the readout noise was evaluated as a function of the absorbed dose at the buried oxide layer, D BOX. The pedestal and analog-to-digital conversion gain also displayed similar tendencies. These results demonstrate that BI type devices have a higher radiation tolerance as a focal plane sensor of an X-ray mirror and the radiation tolerance of XRPIX devices is governed by D BOX. The readout noise was stable up to about 1 krad in D BOX , increased by about 10% at 10 krad in D BOX , and continued to increase under further irradiation. If we employ an X-ray mirror with a half-power diameter of 10 arcsec and a focal length of 10 m, 10 krad in D BOX , a reasonable threshold of radiation tolerance in this experiment, is equivalent to more than three years in orbit, typically required of space-borne sensors. Highlights • Total ionizing dose effects on the SOI pixel sensor, XRPIX, were studied. • Front-and back-illuminated (FI and BI) devices were irradiated with hard X-rays. • BI type devices have a higher radiation tolerance. • XRPIX's radiation tolerance is governed by the absorbed dose at the BOX layer. • XRPIX has a lifetime in orbit long enough for application as a space-borne sensor. [ABSTRACT FROM AUTHOR]

This paper presents a four channel phased array transmitter at 15 GHz aimed for the upcoming 5G wireless systems. The circuit is designed and fabricated using 45 nm  CMOS silicon on insulator technology. The design is programmable with exhaustive digital controls available for parameters such as bias voltage, resonance frequency, and gain. The phase shift required for the phased array is provided at RF using an IQ vector modulator (IQVM) topology, which provides both amplitude and phase control. Based on the measurement results, the IQVM provides 360° of phase shift and 15 dB of gain variation. Both phase and amplitude information are encoded in a 10 bit control word. The mean angular separation provided by the IQVM is 3° at optimum amplitude levels. Active area occupied is 2.88 square millimeter. Total DC power consumed by one transmit channel from 1 and 2.6 V supply is 268 mW. The maximum RF output power from one transmit channel is 1dBm. Measured EVM for a 256 QAM modulated signal is as low as 2.0%. All results include the impact of printed circuit board traces and pad parasitics. Based on the achieved results, the proposed architecture is well suited for the next generation of the wireless systems. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

A ${D}$ -band I/Q RF-DAC featuring two 6-bit DAC elements driven in quadrature, each with its own on-die antenna, and a total effective isotropic radiated power (EIRP) of 13.2 dBm, is demonstrated in a 45-nm SOI-CMOS technology. The carrier signal is first amplified by the 30-dB gain LO path and is directly modulated by the 12 baseband bit streams, without linear upconversion or power amplification. QPSK, 8-PSK, 16-QAM, 32-QAM, and 64-QAM single-carrier (SC) and OFDM constellations are formed in free space and measured above the die at data rates up to 12 Gb/s and at distances over 15 cm. The large-signal bandwidth—from the carrier input pad to the output of the transmitter above the antennas—is 130–142 GHz and was obtained by sweeping the frequency of the ${D}$ -band external carrier, modulating it on die at 0.4 Gb/s using 16-QAM format, and measuring the error vector magnitude (EVM) with an instrumentation receiver. The highest data rate of 12 Gb/s was measured for QPSK SC modulation with a corresponding EVM of −12.2 dB. Lower maximum data rates of 7 Gb/s with −14.3-dB EVM and 3.6 Gb/s with −19-dB EVM were observed for 16-QAM and 64-QAM formats, respectively. Spectral shaping and OFDM transmission were also demonstrated at up to 2.5 Gb/s. The prototype consumes a total of 1.25 W, with an energy efficiency of 104 pJ/b. [ABSTRACT FROM AUTHOR]

The design considerations and circuit topologies of a family of ultralow-power fundamental-frequency and second-harmonic 60-GHz radar sensors are described. The single-chip sensor architecture features four low-noise-matched receivers, either a fundamental-frequency 60-GHz voltage-controlled oscillator (VCO) or 30-GHz VCO + doubler, and a static divide-by-8192 chain which is turned OFF 95% of the time to save DC power. On-die measurements show a power consumption of 42 mW from a single 1.2-V supply, 10% frequency tuning range, −104 to −108 dBc/Hz phase noise at 10-MHz offset, 10-dB conversion gain per receiver, and −7-dBm transmitter output power at the antenna pads. Several 45-nm SOI-CMOS sensor dies were flip-chip mounted on a $7\times 7$ mm2 flexible interposer which also includes four receive- and two transmit antennas. Doppler and direction of arrival tests were conducted over distances of several tens of centimeters. [ABSTRACT FROM PUBLISHER]

Low power consumption has become one of the major requirements for most microelectronic devices and systems. Increasing power dissipation may lead to decreasing system efficiency and lifetime. The BULK metal oxide semiconductor field-effect transistor (MOSFET) has relatively high power dissipation and low frequency response due to its internal capacitances. Although the silicon-on-insulator (SOI) MOSFET was introduced to resolve these limitations, other challenges were introduced including the kink effect in the current-voltage characteristics. The selective buried oxide (SELBOX) MOSFET was then suggested to resolve the problem of the kink effect. The authors have previously investigated and reported the characteristics of the SELBOX structure in terms of kink effect, frequency, thermal and static power characteristics. In this paper, we continue our investigation by presenting the dynamic power characteristics of the SELBOX structure and compare that with the BULK and SOI structures. The simulated fabrication of the three devices was conducted using Silvaco TCAD tools in 90 nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that the average dynamic power dissipation of the CMOS BULK, SOI and SELBOX are compatible at high frequencies with approximately 54.5 µW. At low frequencies, the SOI and SELBOX showed comparable dynamic power dissipation but with lower values than the BULK structure. The difference in power dissipation between the SELBOX and BULK is in the order of nano watts. This power difference becomes significant at the chip level. For instance, at 1 MHz, SOI and SELBOX exhibit an average dynamic power consumption of 0.0026 µW less than that of the BULK structure. This value cannot be ignored when a chip operates using thousands or millions of SOI or SELBOX MOSFETs.

This paper presents Gb/s-speed circuit building blocks in 32-nm CMOS SOI, for a > 20-Gb/s Cartesian direct-modulation W -band transmitter. Transmitter systems non-idealities and performance limitations are discussed, and circuit design techniques and analyses are presented. The transmitter employs two 2-b high-speed RF digital-to-analog converters driven in quadrature, 20-dB gain W -band LO drivers, and 30-Gb/s high-speed digital retimers and deserializers, and is capable of supporting BPSK/PAM4/QPSK/16-QAM modulation schemes, at a saturated output power P\mathrm{ sat} of +4 dBm. A maximum data rate of 20 Gb/s was achieved when operating in QPSK mode, 4 Gb/s in 16-QAM mode, and 12 Gb/s in both BPSK and PAM4 modes. The chip occupies 1.40.8 mm2 and consumes 110 mW in BPSK/PAM4 modes and 220 mW in QPSK and 16-QAM modes, resulting in the state-of-the-art 9-, 11-, and 55-pJ/b peak efficiencies, respectively. A mixer-first wideband W -band receiver that includes a passive mixer and a wideband transimpedance amplifier is also presented. Measurements of the receiver chip demonstrated its capability to downconvert and amplify highly complex modulated waveforms (> 256-QAM), and at high data rates, up to 60 Gb/s in 64-QAM, which proves the feasibility of building high dynamic-range mm-wave receivers with bandwidth greater than 30 GHz. The receiver chip was also built in 32-nm CMOS SOI, occupying a core area of 0.180.1 mm2 [ABSTRACT FROM AUTHOR]

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors. [ABSTRACT FROM AUTHOR]

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (V BR ) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (V t1 ) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior. [ABSTRACT FROM AUTHOR]

Common quasi-static electrostatic micro actuators have significant limitations in deflection due to electrode separation and unstable drive regions. These actuators suffer from an operational instability, the so-called pull-in effect that limits the actuators’ travel range to one third of the electrode separation. High driving voltages and large electrode gaps are required to achieve large displacements. In our work, we present a novel electrostatic actuator class, which allows high deflections with nanometric electrode separation. The approach presented utilizes a bimorph like effective lever to transform electrostatic forces into deflection. It permits to make use of high electrostatic forces generated in small gaps and thus gives access to large actuator deflections. We demonstrate that quasi-static deflections as large as four times the gap size are possible. [ABSTRACT FROM AUTHOR]

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 μA-0.1 μA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)-0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. [ABSTRACT FROM AUTHOR]

We systematically studied Ge CMOS devices and logic circuits fabricated on a GeOI substrate, with the novel recessed channel and source/drain structures. Various channel lengths ( L\mathrm {ch} ) from 500 to 30 nm and channel thicknesses ( T\mathrm {ch} ) from 90 to 10 nm are implemented into the Ge CMOS devices and comprehensive geometry dependence analysis is carried out in terms of both L\mathrm {ch} and T\mathrm {ch} . With shrinking T\mathrm {ch} , the gate electrostatics are enhanced significantly but the on-state performance is found to be deteriorated simultaneously. It is also confirmed that Ge nMOSFETs are more sensitive to T\mathrm {ch} than pMOSFETs due to the phosphorus diffusion inside Ge. CMOS circuits, such as inverters, NANDs, NORs, and ring oscillators, are further investigated. [ABSTRACT FROM PUBLISHER]

We are developing advanced pixel sensors using silicon-on-insulator (SOI) technology. A SOI wafer is used; top silicon is used for electric circuit and bottom silicon is used as a sensor. Target applications are high-energy physics, X-ray astronomy, material science, non-destructive inspection, medical application and so on. We have developed two integration-type pixel sensors, FPIXb and INTPIX7. These sensors were processed on single SOI wafers with various substrates in n- or p-type and double SOI wafers. The development status of double SOI sensors and some up-to-date test results of n-type and p-type SOI sensors are shown. [ABSTRACT FROM AUTHOR]

We propose and demonstrate experimentally a band-modulation device with extremely sharp switching capability. The Z 3 -FET (Zero gate, Zero swing and Zero impact ionization) has no top gate, is processed with FDSOI CMOS technology, and makes use of two adjacent buried ground planes acting as back gates. The buried gates emulate respectively N + and P + regions in the undoped body, forming a virtual thyristor-like NPNP structure with feedback operation. Vertical output I A – V A and transfer I A – V G characteristics over more than 8 decades of current are measured with relatively low gate and drain bias (<3 V). [ABSTRACT FROM AUTHOR]

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high- k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS. [ABSTRACT FROM AUTHOR]

In this paper, we present the design and characterization of a low-power low-cost infra-red emitter based on a tungsten micro-hotplate fabricated in a commercial 1- \mu \textm silicon on insulator-CMOS technology. The device has a 250- \mu \textm diameter resistive heater inside a 600- \mu \textm diameter thin dielectric membrane. We first present electro-thermal and optical device characterization, long term stability measurements, and then demonstrate its application as a gas sensor for a domestic boiler. The emitter has a dc power consumption of only 70 mW, a total emission of 0.8 mW across the 2.5–15- \mu \textm wavelength range, a 50% frequency modulation depth of 70 Hz, and excellent reproducibility from device-to-device. We also compare two larger emitters (heater size of 600 and 1800~\mu \textm ) made in the same technology that have a much higher infra-red emission, but at the detriment of higher power consumption. Finally, we demonstrate that carbon nanotubes can be used to significantly enhance the thermo-optical transduction efficiency of the emitter. [ABSTRACT FROM PUBLISHER]

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

Most of the variables measured in scientific investigations or engineering applications depend, by varying degrees, on temperature. This necessitates the simultaneous measurement of temperature along with the variable of interest in order to perform high fidelity temperature compensated measurements. Silicon diode based temperature sensors (or silicon thermodiodes) have the advantages of being low cost, having an absolute temperature measurement capability as well as providing the option of on-chip integration with electronic circuits and a wide temperature measurement range. Leveraging these advantages, engineers and scientists have used silicon thermodiodes in numerous and diverse applications. This paper identifies the common temperature measuring techniques, and focuses on the use and advantages offered by silicon diodes operated as temperature sensors in different drive modes. Finally it explores the published literature for summarizing the application areas where such sensors have been utilized successfully in recent years. [ABSTRACT FROM AUTHOR]

This paper presents an experimentally verified 3D FEM model to understand heat transfer mechanisms in membrane based thermal conductivity sensors developed using SOI CMOS MEMS technology. It aims to provide a structured methodology to design micro thermal conductivity sensors for gas detection. The reported model takes in to account heat transfer by conduction and convection in conjunction with device geometry and is based on a sensor fabricated at a commercial CMOS foundry using a 1 μm process that measures only 1x1 mm 2 . [ABSTRACT FROM AUTHOR]