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Analysis and Design of Wideband I/Q CMOS 100–200 Gb/s Modulators.
- Source :
- IEEE Journal of Solid-State Circuits; Sep2019, Vol. 54 Issue 9, p2361-2374, 14p
- Publication Year :
- 2019
-
Abstract
- This paper presents the analysis and design of wideband I/Q CMOS modulators and transmitters. Non-idealities and performance limitations of Cartesian transmitter and modulator systems are discussed, and circuit design techniques and analyses are shown. A DC-60 GHz I/Q modulator/transmitter chip in 45-nm SOI CMOS is presented as a critical building block for next-generation multi-standard and high-capacity wireless backhaul links. The modulator consists of a wideband quadrature signal generator, wideband buffers, and two current-combined DC-100 GHz low-noise double-balanced mixers driven in quadrature. The 1.4 mm2 modulator chip achieves 60 dB of dynamic range in a 1-GHz bandwidth, with an OP1dB of ~ −10 dBm, thus enabling spectrally efficient high-order modulation schemes such as 256-QAM. The I/Q modulator achieves 200 Gb/s in 16-QAM (50 Gbaud/s) while consuming 200 mW, resulting in record 1-pJ/bit modulation efficiency. In addition to backhaul links, the modulator is an attractive and cost-effective alternative to short-range optical links for data center interconnects (DCI) and for chip-to-chip communications. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189200
- Volume :
- 54
- Issue :
- 9
- Database :
- Complementary Index
- Journal :
- IEEE Journal of Solid-State Circuits
- Publication Type :
- Academic Journal
- Accession number :
- 138276016
- Full Text :
- https://doi.org/10.1109/JSSC.2019.2923081