Search

Your search keyword '"Ravikumar Ramachandran"' showing total 7 results
Start Over Author "Ravikumar Ramachandran" Topic cmos
7 results on '"Ravikumar Ramachandran"'

1. High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

Author

E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, and Dureseti Chidambarrao

Subjects
Engineering, Subthreshold conduction, business.industry, Processor design, Copper interconnect, Soi finfet, Hardware_PERFORMANCEANDRELIABILITY, Thread (computing), Planar, CMOS, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, business, Dram
Abstract

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

Published
2014

2. 10nm FINFET technology for low power and high performance applications

Author

Philip J. Oldiges, Hemanth Jagannathan, Kangguo Cheng, Christopher Prindle, C.-C. Yeh, R. Divakaruni, S. Kanakasabaphthy, Derrick Liu, Sean D. Burns, P. Montanini, T. Gow, Huiming Bu, Abhijeet Paul, Terry A. Spooner, Richard G. Southwick, Jin Cho, M. Celik, Mukesh Khare, Donald F. Canaperi, Young-Kwan Park, H. Mallela, Ravikumar Ramachandran, Bomsoo Kim, Dinesh Gupta, Balasubramanian S. Pranatharthi Haran, R. Kambhampati, M. Weybright, W. Yang, Vamsi Paruchuri, Tae-Chan Kim, R. Sampson, K. Kim, D. Chanemougame, John Iacoponi, Jay W. Strane, Ruilong Xie, D.I. Bae, Injo Ok, Matthew E. Colburn, T. Hook, Kang-ill Seo, Lars W. Liebmann, V. Sardesai, Hoon Kim, Neeraj Tripathi, H. Shang, M. Mottura, Reinaldo A. Vega, B. Hamieh, D. McHerron, Theodorus E. Standaert, Ju-Hwan Jung, S. Nam, E. Alptekin, Soon-Cheon Seo, Dechao Guo, J. G. Hong, Gen Tsutsui, Andreas Scholze, J. Jenq, Xiao Sun, Walter Kleemeier, James H. Stathis, and Geum-Jong Bae

Subjects
Materials science, CMOS, Dopant, business.industry, Electronic engineering, Optoelectronics, Silicon on insulator, Static random-access memory, business, Lithography, Random dopant fluctuation, Communication channel, Power (physics)
Abstract

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

Published
2014

3. High performance bulk planar 20nm CMOS technology for low power mobile applications

Author

Eduard A. Cartier, X. Chen, Pierre Malinge, L. Kang, T. Watanabe, Michael P. Belyansky, L. Economikos, O. Menut, Vijay Narayanan, C. Reddy, R. Divakaruni, Y.H. Park, Ravi Prakash Srivastava, M. Pallachalil, R. Koshy, Dominic J. Schepis, P. Montanini, Keith Kwong Hon Wong, M. Eller, Park Sejun, A. Ogino, H. Mallela, U. Kwon, T. Shimizu, W. Cote, Jay W. Strane, Srikanth Samavedam, M. Chae, Anurag Mittal, R. Sampson, J. Meiring, R. Joy, Huiling Shang, S. Soss, X. Yang, Keith H. Tabakman, M. Oh, W. Lai, C. Tran, S. Jain, E. Josse, D. Codi, H.V. Meer, B.Y. Kim, Jung-Geun Kim, Jin Bum Kim, C. Goldberg, Henry K. Utomo, J. Ciavatti, Barry Linder, R. Vega, W. Neumueller, J. Muncy, Kyung-hwan Cho, Scott J. Bukofsky, Alvin G. Thomas, Dinesh Koli, Katherina Babich, Bomi Kim, S. Lian, E. Alptekin, Y. Liu, S. H. Rhee, X. Wu, R. Arndt, W.L. Tan, Frederic Lalanne, Nam-Sung Kim, Ravikumar Ramachandran, K.Y. Lee, M.H. Nam, Randy W. Mann, Il-Ryong Kim, Yujun Li, V. Sardesai, Siddarth A. Krishnan, C. Tian, D. Levedakis, Seung-Kwon Kim, Jedon Kim, M. Celik, F. Matsuoka, M. Weybright, J. Sudijono, M. Aminpur, B. Hamieh, Greg Northrop, and J.W. Lee

Subjects
Engineering, business.industry, Electrical engineering, Hardware_PERFORMANCEANDRELIABILITY, Planar, Strain engineering, CMOS, Logic gate, Hardware_INTEGRATEDCIRCUITS, Static random-access memory, business, Metal gate, Standby power, Leakage (electronics)
Abstract

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

Published
2012

4. A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology

Author

Lisa F. Edge, C. Ortolland, W. Lai, J. Muncy, R. Divakaruni, J.-B. Laloë, David L. Rath, R. Bingert, J. Cutler, Ruqiang Bao, Vijay Narayanan, M. Krishnan, X. Zhang, Vamsi Paruchuri, J. Y. Huang, Ravikumar Ramachandran, X. Chen, Michael A. Gribelyuk, Haihong Wang, Keith Kwong Hon Wong, Y. Zhang, D. S. Salvador, Unoh Kwon, Il-Ryong Kim, Michael P. Chudzik, L. Econimikos, Y. Liu, Siddarth A. Krishnan, and L. D. Thanh

Subjects
Engineering, business.industry, Gate dielectric, Electrical engineering, Time-dependent gate oxide breakdown, Hardware_PERFORMANCEANDRELIABILITY, CMOS, Gate oxide, Logic gate, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, Node (circuits), business, Metal gate, Hardware_LOGICDESIGN, High-κ dielectric
Abstract

Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm L gate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.

Published
2012

5. 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Author

W. Yan, Carl J. Radens, R. Divakaruni, John G. Massey, Christopher Parks, Yujun Li, Boyong He, S. Butt, Chang Ju Choi, Ravikumar Ramachandran, G. La Rosa, Emmanuel F. Crabbe, Michael P. Chudzik, Rajesh Rengarajan, Werner Robl, Haining Yang, Scott Halle, C. Ransom, and Kang-yoon Lee

Subjects
Dynamic random-access memory, Materials science, business.industry, Transistor, Electrical engineering, Electronic, Optical and Magnetic Materials, PMOS logic, law.invention, CMOS, law, MOSFET, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, Electrical and Electronic Engineering, business, NMOS logic, Dram, Leakage (electronics)
Abstract

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.

Published
2002

6. Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

Author

Dechao Guo, Myung-Hee Na, Y. Tsang, R. Mo, Huiming Bu, Karthik Ramani, Kathryn T. Schonenberg, Eduard A. Cartier, Naim Moumen, R. Knarr, Wei He, M. Hargrove, Ricardo A. Donaton, Siddarth A. Krishnan, Keith Kwong Hon Wong, James K. Schaeffer, Ravikumar Ramachandran, Eric C. Harley, X. Wang, E. Luckowski, Vijay Narayanan, K. Henson, Michael P. Chudzik, B. Zhang, W. Yan, D.-G. Park, Rashmi Jha, Martin M. Frank, Michael A. Gribelyuk, Unoh Kwon, Mukesh Khare, R. Arndt, Todd Bailey, Yue Liang, Troy L. Graves-Abe, C. DeWan, R. Carter, and Joseph F. Shepard

Subjects
Stress (mechanics), Materials science, CMOS, International Electron Devices Meeting, business.industry, Logic gate, Electrical engineering, Silicon on insulator, Optoelectronics, Field-effect transistor, business, Metal gate, Capacitance
Abstract

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinv's down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

Published
2008

7. High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

Author

S. Subbanna, Huilong Zhu, T. Shinohara, R.-V. Bentum, H. Kuroda, C. Penny, Jay W. Strane, D. McHerron, D. Harmon, D. Zamdmer, Q. Ye, Yoshiaki Toyoshima, Paul D. Agnello, S. Wu, G. Freeman, L. Tsou, Atsushi Azuma, Scott J. Bukofsky, Carl J. Radens, M. Angyal, M. Fukasawa, Effendi Leobandung, Byeong Y. Kim, M. Gerhardt, Y. Tan, L. Su, Tenko Yamashita, Anda Mocuta, I.C. Inouc, Takeshi Nogami, Scott D. Allen, R. Logan, K. Miyamoto, Shih-Fen Huang, Ravikumar Ramachandran, J. Pellerin, A. Ray, Siddhartha Panda, Christine Norris, H.V. Meer, H. Nayakama, Mizuki Ono, Keith Jenkins, J. Heaps-Nelson, Wenjuan Zhu, D. Ryan, Michael A. Gribelyuk, B. Dirahoui, M. Inohara, E. Nowak, I. Melville, S. Lane, T. Ivers, K. Ida, Scott Halle, Ishtiaq Ahsan, M.-F. Ng, Huicai Zhong, H. Harifuchi, S.-K. Ku, N. Kepler, F. Wirbeleit, Emmanuel F. Crabbe, H. Yan, T. Kawamura, Mahender Kumar, A. Nomura, L. K. Wang, F. Sugaya, H. Hichri, Gary B. Bronner, P. O'Neil, K. Miyashita, Michael P. Belyansky, J. Cheng, S.-H. Rhee, Lars W. Liebmann, D. Yoneyama, Dan Mocuta, K. McStay, G. Sudo, and Dureseti Chidambarrao

Subjects
Materials science, business.industry, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, Dielectric, Chip, Capacitance, Digital subscriber line, CMOS, Gate oxide, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Optoelectronics, Static random-access memory, business, Hardware_LOGICDESIGN
Abstract

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Published
2005

Catalog

Books, media, physical & digital resources
See catalog results