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A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology

Authors :
Lisa F. Edge
C. Ortolland
W. Lai
J. Muncy
R. Divakaruni
J.-B. Laloë
David L. Rath
R. Bingert
J. Cutler
Ruqiang Bao
Vijay Narayanan
M. Krishnan
X. Zhang
Vamsi Paruchuri
J. Y. Huang
Ravikumar Ramachandran
X. Chen
Michael A. Gribelyuk
Haihong Wang
Keith Kwong Hon Wong
Y. Zhang
D. S. Salvador
Unoh Kwon
Il-Ryong Kim
Michael P. Chudzik
L. Econimikos
Y. Liu
Siddarth A. Krishnan
L. D. Thanh
Source :
2012 Symposium on VLSI Technology (VLSIT).
Publication Year :
2012
Publisher :
IEEE, 2012.

Abstract

Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm L gate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.

Details

Database :
OpenAIRE
Journal :
2012 Symposium on VLSI Technology (VLSIT)
Accession number :
edsair.doi...........076a7abde5a67e6679f8b5e3f70e0314