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We present the experimental results on the impact of transistor width modulation and power supply voltage variation on the $\alpha $ -soft error rate (SER) in a 65-nm CMOS 6T static random access memory (SRAM) obtained from an accelerated test experiment using an Am- $241~\alpha $ -source. Five 6T cells with various combinations of transistor widths were tested and the results show that nMOS and pMOS widths play a different role on SER. We also found that the transistor width modulation effectiveness is highly dependent on the power supply voltage. In particular, the results show that at around nominal voltages, widening all pMOS while keeping all nMOS minimum sized, is the best way to improve SER. However, at lower voltages the results become completely different, and the best option for an overall SER improvement is to keep all transistors minimum sized.

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25 percent (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35 percent, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30 percent.

CMOS–MEMS microresonators have become excellent candidates for developing portable chemical VOC sensing systems thanks to their extremely large mass sensitivity, extraordinary miniaturization capabilities, and on-chip integration with CMOS circuitry to operate as a self-sustained oscillator. This paper presents two 4-anchored MEMS plate resonators, with a resonance frequency of 2.2 MHz and 380 kHz, fabricated together with the required circuitry using a commercial 0.35 μm CMOS technology and then coated with poly-4-vinylheduorocumyl alcohol (P4V) via inkjet deposition. Such P4V constitutes a functionalization layer for specific acetone detection as a key step in the development of an integrated device for non-invasive diabetes diagnosis through exhaled human breath. The coated sensor system has been proven to increase the acetone injection response by 6-times compared to the uncoated platform and shows a cross-sensitivity to butane of 1 : 11. Experimental data show an acetone sensitivity of −0.012 ppm Hz−1 in the best case that, together with a measured frequency Allan deviation of 0.32 ppm, provides an expected limit of detection as low as 20 ppb of acetone. Additionally, this work presents an alternative resonator design with folded flexure anchors that provide a drastic reduction of the sensor temperature sensitivity and mitigate the impact of a fluid flow inherent to the calibration system.

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This paper presents a transimpedance amplifier (TIA) fabricated using a commercial 0.35-&micro, m CMOS technology specifically oriented to drive and sense monolithically integrated CMOS-MEMS resonators up to 50 MHz with a tunable transimpedance gain ranging from 112 dB to 121 dB. The output voltage noise is as low as 225 nV/Hz1/2&mdash, input-referred current noise of 192 fA/Hz1/2&mdash, at 10 MHz, and the power consumption is kept below 1-mW. In addition, the TIA amplifier exhibits an open-loop gain independent of the parasitic input capacitance&mdash, mostly associated with the MEMS layout&mdash, representing an advantage in MEMS testing compared to other alternatives such as Pierce oscillator schemes. The work presented includes the characterization of three types of MEMS resonators that have been fabricated and experimentally characterized both in open-loop and self-sustained configurations using the integrated TIA amplifier. The experimental characterization includes an accurate extraction of the electromechanical parameters for the three fabricated structures that enables an accurate MEMS-CMOS circuitry co-design.

We present experimental results of soft errors produced by proton and neutron irradiation of minimum-size six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories produced with 65 nm CMOS technology using an 18 MeV proton beam and a neutron beam of 4.3–8.5 MeV. All experiments have been carried out at the National Center of Accelerators (CNA) in Seville, Spain. Similar soft error rate levels have been observed for both cell designs despite the larger area occupied by the 8T cells, although the trend for multiple events has been higher in 6T., This work has been supported by the Spanish Ministry of Economy and Competitiveness (MINECO/FEDER) under projects CICYT-TEC2011-25017 and TEC2014-52878-R.

We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistor (6T) and eight-transistor (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45× higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5× for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments.

For the first time, chaotic signal generation with a simple and straight clamped-clamped beam resonator has been experimentally measured. The submicrometric MHz resonator and the readout circuit have been fabricated and monolithically integrated using a commercial $0.35-\mu\mathrm{m}$ CMOS technology. Extensive homoclinic chaotic motion has been obtained from the bistable cc-beam resonator and validated by means of a positive Lyapunov exponent.

This paper presents the design, fabrication, and electrical characterization of an electrostatically actuated and capacitive sensed 2-MHz plate resonator structure that exhibits a predicted mass sensitivity of ~250 pg&middot, cm&minus, 2&middot, Hz&minus, 1. The resonator is embedded in a fully on-chip Pierce oscillator scheme, thus obtaining a quasi-digital output sensor with a short-term frequency stability of 1.2 Hz (0.63 ppm) in air conditions, corresponding to an equivalent mass noise floor as low as 300 pg&middot, 2. The monolithic CMOS-MEMS sensor device is fabricated using a commercial 0.35-&mu, m 2-poly-4-metal complementary metal-oxide-semiconductor (CMOS) process, thus featuring low cost, batch production, fast turnaround time, and an easy platform for prototyping distributed mass sensors with unprecedented mass resolution for this kind of devices.

We analyzed experimentally the noise characteristics of fully integrated CMOS-MEMS resonators to determine the overall thermomechanical noise and its impact on the limit of detection at the system level. Measurements from four MEMS resonator geometries designed for ultrasensitive detection operating between 2-MHz and 8-MHz monolithically integrated with a low-noise CMOS capacitive readout circuit were analyzed and used to determine the resolution achieved in terms of displacement and capacitance variation. The CMOS-MEMS system provides unprecedented detection resolution of 11 yF&middot, Hz&minus, 1/2 equivalent to a minimum detectable displacement (MDD) of 13 fm&middot, 1/2, enabling noise characterization that is experimentally demonstrated by thermomechanical noise detection and compared to theoretical model values.

The biasing requirements to obtain cross-well chaotic motion for in-plane electrostatically driven beam-shaped MEMS (micro-electromechanical systems) resonators are investigated for typical actuation/readout topologies. Practical applications such as signal chaotic generators require reasonable and wide enough range voltages (dc and ac) to assure a feasible control in current CMOS or nanotechnologies. We found that these conditions are only obtained when enabling cross-well motion operation instead of in-well operation. Moreover, in contrast to many works that take unfeasible design parameters, we provide for the first time the design rules and biasing ranges required for commercial CMOS technologies and nanotechnology when considering typical parameter values from various fabrication approaches.

We analyze the evolution of SRAM memory logic contents under irradiation by defining the memory state as the number of cells storing a given logic value (i.e. number of cells storing a logic-1). We find that the memory state evolution under irradiation follows an Ehrenfest urn model due to the constant effect of single event upsets, and that in large memories it can be associated to an Ornstein-Uhlenbeck process. Memory state transient analysis has been applied to determine the device Soft error rate for an SRAM fabricated in a 65 nm commercial CMOS process obtaining a very good correlation. Furthermore, our analysis shows that the technique is applicable to systems composed by various dissimilar memory components, providing–under certain circumstances–the specific Soft Error Rate of each component.

Eight-transistor (8T) cells were introduced to improve variability tolerance, cell stability and low-voltage operation in high-speed SRAM caches by decoupling the read and write design requirements. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM. Ionizing radiation effects are nowadays a major concern for reliability and dependability of emerging electronic SRAM devices, even for sea-level applications. In this paper we demonstrate from experimental results that the 8T-SRAM also exhibits an enhanced overall intrinsic tolerance to alpha particle radiation even though its critical charge values are smaller than conventional 6T cells. We have experimentally found that the soft error rate measured in accelerated experiments with alpha particles in SRAM devices implemented in a 65 nm CMOS is 56% better for 8T cells with respect to standard 6T-cells. Even more, we show that this value can be increased up to a 200% through transistor sizing optimization.

Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different VDD and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when VDD and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of VDD and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when VDD is lowered, and increases even more when RBB is applied at Low VDD. The test conditions to improve resistive bridge detection combining Low VDD and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of VDD. The values of Low VDD and RBB can be selected considering the tradeoff between fault coverage and test time penalization.

Experimental demonstration of bistability in simple, straight and non-axially-forced clamped-clamped microbeam resonators in the MHz range is reported for the first time. Experimental measurements have been also used to validate a nonlinear electromechanical model for microbeam resonators and its tuning procedure through the thermal effect. The model is used to obtain the design and biasing conditions to achieve bistability is such devices. The measured devices were fabricated and monolithically integrated with readout circuitry using a commercial 0.35μm CMOS technology resulting in a low-cost platform to investigate potential applications of bistability in MEMS devices.

We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write noise margin are evaluated from circuit simulations using a nanomechanical relay Verilog-A compact model. Comparisons are performed between a 65 nm CMOS 6T conventional SRAM cell and various hybrid memory cells constructed by replacing selected MOSFET transistors with cantilever relays. The impact on other important memory cell parameters such as area, timing performance and power consumption is also discussed.

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal VDD. A specific VWL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a VWL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65 nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of VWL with a small impact on read time.

We report and analyze the dependence of complex gates delay with the sensitization vector and its variation-that gets up to 40% in 65-nm CMOS technologies-and include its effect in the path delay estimation-that can be in the order of 16%. The gate delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. An STA tool based on a single-pass true path computation is used to determine the critical path list. Since it does not rely on a two-step process, it can be programmed to find efficiently the N true paths from a circuit. Results from various benchmark circuits synthesized for three commercial technologies (130, 90, and 65 nm) provide better results in number of paths reported and delay estimation for these paths compared to a commercial tool. The impact of delay variation with the sensitization vector for paths with complex gates reveals as a significant mechanism that must be considered as it is comparable to the impact of parameter variations or interconnect-induced delay.

Resistive bridges are a major class of defects in nanometer technologies that can escape test, posing a serious reliability risk for CMOS IC circuits. The increase of process parameter variations represents a challenge for resistive bridge detection using traditional test methods, and requires more efficient test methods to be developed. In this work, we show that resistive bridge detection improves by correlating the defect-induced extra circuit delay with the power supply voltage value and the reverse body bias (RBB) applied. A Timing Critical Resistance ( R crit t ) is defined as a metric to quantify the resistive bridge detection enhancement in the presence of process variations under a delay based test. We show that the smaller the supply voltage, the higher the resistive bridge detection which further enhances by applying RBB. Results are presented for a 65 nm CMOS technology.

We present a single event transient (SET) propagation model that can be used to quantify the propagation likelihood of a given noise waveform trough CMOS logic gates. This analysis is key to predict if an SET induced within a combinational block is capable of causing an SEU. The model predicts the output noise characteristics given the input noise waveform for each gate, and can be applied to any CMOS technology through a one-time library parameter extraction process. Pulse propagation is described through continuous analytical functions that convert an SET pulse height and width at the gate input to an SET pulse height and width at its output. The noise transfer curves have relatively simple analytical continuous expressions suitable for an easy adoption within CAD tools, thus allowing the investigation of pulse propagation through an entire logic block. Comparison between simulations and model show a very good agreement for a commercial 65 nm technology.

We analyze and compare the impact of radiation-induced transient effects based on evaluating the critical charge parameter for 6T and 8T SRAMs during hold, read and write operations. Results on a commercial 65 nm CMOS technology show that 6T and 8T cells offer quite similar robustness when they are in hold. However, the critical charge observed in other operation modes is reduced a 55% respect to the hold operation. For this reason, we provide a thorough analysis of the critical charge behavior in 6T and 8T SRAMs to determine the dependence of memory radiation robustness with memory state. Single event upsets and single event transients have been considered in the analysis, showing that 8T have better performance than 6T. The dependence of critical charge with memory state for high workload memories modifies the overall memory SER estimation indicating the significance of analyzing the memory robustness as a memory state function. In general, the SER estimation results show that the robustness behavior of 8T-based cells is better than robustness behavior of 6T-based cells.

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell-size increase. The other solution is based on multithreshold voltage selection showing a moderate immunity improvement at the cost of no impact on the cell area. The combination of both techniques is shown to be optimum when considering other design metrics like static noise margin, read/write stability, access time, and leakage. Results are demonstrated on 90- and 65-nm commercial technologies.

We present an accurate model to estimate the energy and delay of domino CMOS gates derived from a detailed description of internal capacitance switching and discharging currents. The delay dependence with the position of the switching transistor in the gate is accurately described with the advantage that it does not include additional empirical parameters, thus providing the propagation delay in terms of foundry-provided MOSFET parameters. Results show a very high accuracy with a relative error lower than a 3% with respect to HSPICE for a 0.18-/spl mu/m CMOS technology providing up to three orders of magnitude of speed improvement. The analytical nature of the model makes it suitable for circuit optimization and is the basis for a quick estimation of ULSI circuits power and delay when used in circuit simulation tools.

Silicon-on-insulator (SOI) is emerging as a strong technology candidate for low-power high-performance applications. In this work, based on experimental data, we review the fundamental aspects of leakage current in deep-submicron SOI CMOS technologies discussing the underlying physical mechanisms and their dependence with bias, temperature and operating frequency. These mechanisms and their evolution with technology scaling are compared to those of bulk CMOS. Subsequently, we evaluate the merits of parametric I-DDX testing techniques based on current monitoring when applied to these technologies. (C) 2003 Published by Elsevier Ltd.

We present a Built-In-Current-Sensor (BICS) based on monitoring a signature of the supply current peak of CMOS OpAmps using the oscillation-test-strategy. The BICS takes a weighted sample of the current through two OpAmp current branches and monitors a signature of the peak value under oscillation. Two current-based comparators and some digital circuitry are used to provide a pass/fail flag. Simulation results demonstrate a high defect coverage with a very small impact both on the OpAmp nominal operation and the area overhead.

We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays. Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays. Impact on important memory cell parameters such as various reliability metrics like static noise margin and write noise margin and power consumption are evaluated from circuit simulations using a Verilog-A compact model of the nanomechanical relay. We found that the use of relays involve a new challenge in the design of SRAM hybrid devices as the readability and writeability of the resulting cells manifests a strong dependence with the value of the contact resistance of the NEM relay, a parameter that can experience important variations with the continued operation of the device.

This paper presents experimental results of Soft errors produced by proton interaction in SRAM memories implemented with a 65nm CMOS technology using the 18 MeV proton facility at the National Center of Accelerators (CNA) in Seville.

A comparison of the merits and possibilities of considering the output voltage and the negative supply current as test observables when using the Oscillation-test technique is carried out. The method is applied to CMOS opamps considering an exhaustive analysis of catastrophic defects (opens, shorts), GOS and floating gates using HSPICE. We analyze deviations in both frequency and signal amplitude of each observable comparing their sensitivity to defects. Results show that the supply current peak value provides the highest defect coverage for a single opamp oscillator, while the oscillating frequency provides the highest fault coverage for a double opamp oscillator.

In this work experimental results on a built in current sensor for dynamic current testing, i/sub ddt/, based on integration concepts are presented. The experimental validation proposed in this work is done through a VLSI CMOS circuit implemented in a 0.7 micron technology. Different experiences have been developed analyzing the detectability of several kind of defects through this technique. The encouraging results obtained present this technique as an attractive complement to boolean and I/sub DDQ/ testing.

We present two versions of a radiation dosimeter, they are CMOS circuits built around a PMOSFET radiation sensor, compatible with standard technology. These dosimeters are intended to be used as built-in sensors in integrated circuits to signal misfunction danger due to radiation exposure, and so they have a binary output which changes its state when the total radiation dose exceeds a prefixed level. The first circuit is an improved version of a previously developed dosimeter which has less power consumption and sharper transfer characteristics. It has been built in ES2 1.0 µm technology and we present experimental results. The second circuit is under development, it is a clocked dosimeter which samples the dose only during a very short time at each clock period and then remains at rest, to further reduce the power consumption.

Experimental results from a 65nm CMOS commercial technology SRAM test chip reveal a high correlation between the word-line voltage margin (WVM)-defined as the difference between the memory nominal supply voltage and the lower mean voltage applied to the word-line capable of writing a cell — and the measured circuit alpha-SER. Additional experiments show that no other memory cell robustness-related parameters (like the minimum supply voltage during hold or read) exhibit such correlation. After an initial irradiation experiment on a reduced sample circuits, the WVM technique can be used to estimate the alpha-SER levels on each particular circuit without requiring additional irradiation experiments. The technique requires a specific memory design modification that does not degrade circuit performance while circuit area increase is negligible.

Bridge defects are an important manufacturing defect that may escape test. Even more, it has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods. Therefore, advances in test methodologies to deal with nanometer issues are required. In this work the feasibility of using Low VDD and body bias in a delay based test to detect resistive bridge defects in CMOS nanometer circuits is analyzed. The detection of bridge defects using a delay based test in nanometer circuits is strongly influenced by: (1) spatial correlation of the process parameters such as length, width and oxide thickness of the transistor, (2) random placement of dopants, and (3) the signal correlation due to reconvergent paths. Because of this, in this work a Statistical Timing Analysis Framework (STAF) is used to analyze the possibilities of detection of bridge defect using a delay based test. The STAF considers different values of VDD and body bias. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage that gives a more realistic measure of the degree of detection of the defect. This methodology is applied to some ISCAS benchmark circuits implemented in a 65nm CMOS technology. The obtained results show the feasibility of the proposed methodology.

This undergraduate textbook for electrical and computer engineering students is dedicated solely to digital CMOS electronics. It covers many of the topics of graduate level textbooks, but in an introductory style specifically crafted (and course tested) for undergraduates. Students will not need a prerequisite in analog electronics, allowing instructors flexibility in course scheduling. This book blends the academic and industrial experience of the authors to define a base of electronics instruction for the CMOS chip industry. CMOS Digital Integrated Circuits: A First Course teaches the fundamentals of modern CMOS technology by focusing on central themes and avoiding excessive details. Extensive examples, self-exercises, and end-of-chapter problems assist in teaching the current practices of industry and subjects taught by graduate courses in microelectronics. Computer engineering curriculums can remove the analog electronics prerequisite altogether when adopting this book. Key Features: CMOS technology written specifically for (and tested by) undergraduates; Equal treatment to both types of MOSFET transistors that make up computer circuits; Power properties of logic circuits; Physical and electrical properties of metals; Introduction of timing circuit electronics; Introduction of layout; Real-world examples and problem sets.

We present a new 8-transistor (8T) SRAM cell design that uses pMOS devices as cell pass transistors controlled by the write word-line signal. The main advantage of this schema is the composition of a balanced 8T SRAM cell having four nMOS and four pMOS transistor that enables a more compact layout and area reduction. An exhaustive analysis about the impact on key parameters such as leakage consumption, write and read stability margins, read delay time and single event upsets for the new cell is reported. A trade-off between cell area reduction and write noise margin improvement is observed, while the remaining parameters are not impacted.

Physical defects widely encountered in today’s CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.

We present the design and operation of a monitor circuit that captures the effect of ionizing particles on sensitive CMOS IC internal nodes. The circuit implements a Single Event Effects (SEE) detector and a quick sampling block that captures the SEE induced waveform shape currents during a certain time window. These values can be read externally through a dedicated decoding circuitry. The circuit has been designed and fabricated on a 130nm technology. Preliminary experimental results and detailed simulations are provided to demonstrate the feasibility of the system implemented.

Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed as a detection scheme for single event upsets in SRAM. In this paper, Power-Bus current transients in SRAM memories for Single Event Upset Detection have been analyzed in a 65nm CMOS technology. The different types of current roles which are applied during the simulation is discussed. The results show the important contribution of leakage currents in the response of the memory cell to an external event.

The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. In this work it is shown that this failure mechanism is very alive and relevant to modern technologies. The small nanometer technology capacitances and the increased leakage currents result in faster discharges of the floating high impedance node making fault detection more difficult. A test vector strategy is proposed to improve the detection of this fault for technologies with gate current leakage.

The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology [1–3]. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. This defect defies a guaranteed 100% detection. We will show that this mostly discarded failure mechanism is very relevant to modern ICs. Current leakage in nanoscale technologies influence significantly the behavior of this fault.

CMOS IC scaling has surpassed the 100nm barrier being now in the 65nm node with a rapid migration to the 35nm generation. In achieving the primary goals of technology scaling such as performance and density increase at a reduced cost per transistor, new side effects must be solved representing further challenges to the advance of the predicted roadmap. One of these challenges is related to the management of thermal-related effects such as hot-spots and overall junction temperature increase as they may have a significant impact on performance, power containment, circuit reliability, and even functionality. The adoption of adequate thermal management solutions requires a detailed analysis of the fundamental relationships governing the device and interconnect subsystem. Although much attention has been given to such analysis at the device and the logic inverter levels, less is known about such dependences in complex gates with transistor stacks. In this work we study the fundamental mechanisms underlying the temperature dependence of transistor stacks showing the key role of the stack dynamic threshold on the overall delay-temperature behavior at the gate level.

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12mm technology showing excellent results., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

In this work we present an analytical formulation to estimate quickly and accurately the impact of crosstalk induced delay in submicron CMOS ICs gates taking into account time skew. Crosstalk delay is computed from the additional charge injected from the aggressor gate on the victim gate during simultaneous switching. The model provides a very good agreement with HSPICE simulations for a 0.18 /spl mu/m technology.

We present a novel technique to accurately describe the leakage power in CMOS nanometer Integrated Circuits (ICs) considering process variations. The model predicts a leakage power increment due to process variations with high accuracy. It is shown that leakage increases considerably as channel length variations become larger due to technology scaling. The present work also describes accurately the dependence of leakage dispersion with process variations. The model developed shows that, even if channel length variations are kept small the leakage dispersion is considerably large. Finally, the concept of “Hot Gates” (HGs) is introduced, showing that HGs will be an important reliability factor in near future nanometer technologies.

A chaotic IC is proposed and fabricated using a 0.35 mum CMOS technology. The circuit iterates an N-shaped transfer function that can be modified using two external voltages, and is implemented using a three neurons network. The main advantages of the proposed circuit are based on its simplicity, small area (47 times 57 mum2), and its MOS-only implementation requiring no more than 15 MOS transistors. Measurements show the suitability of the proposed system to reproduce a chaotic signal and to be used as a random number generator.

The performance increase of VLSI circuits is leading to increase power dissipation and operation temperature, consequently management of thermally related issues is rapidly becoming one of the most challenging efforts in high performance IC design. Within die temperature gradients on silicon can occur due to different activity maps and in high performance ICs differences as high as 50 °C can be achieved during normal operation. Clock network constitutes one of the most critical elements in synchronous circuits and has a significant impact on speed, area and power dissipation. Due to the well-known impact of temperature on delay, the effect of non-uniform thermal maps on the clock skew can acquire a significant relevance. In this work we analyze the impact of within die thermal gradients on the clock skew considering the dependence on temperature on both active devices and interconnects.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses a ring-oscillator composed of complex gates instead of inverters to optimize their linearity. Simulation results from a 0.18$\mu$m CMOS technology show that the non-linearity error of the sensor can be reduced when an adequate set of standard logic gates is selected., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

This chapter contains sections titled: Introduction Materials Science of IC Metals Metal Failure Modes Oxide Failure Modes Conclusion Acknowledgments Bibliography Exercises

This chapter contains sections titled: Introduction The CMOS Inverter NAND Gates NOR Gates CMOS Transmission Gates Summary Bibliography Exercises

We propose and evaluate a non-intrusive built-in monitor oriented to transient current based testing of digital CMOS VLSI circuits. The monitor measures the transient current idd(t) by sensing the voltage drop at an inductance coupled to the magnetic field produced by the power supply transient current. Designed in 120nm CMOS technology, the sensor proposed has two blocks. The transducer circuit senses the transient current and provides a voltage waveform while a second module amplifies the voltage waveform and computes the transient current waveform Idd(t) to produce the charge waveform. Simulation results, using an elaborated CUT model, demonstrate the performance of the transceiver element.