Search

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG = 50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NISi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff = 100 nA/µm) was obtained for Ni31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS. [ABSTRACT FROM AUTHOR]

Abstract: A new carbon-based thermal stability improvement technique is proposed for nickel silicide. Carbon implantation is well known to improve the thermal stability of Ni-based silicides, but its process window is small. An experiment has been performed to identify and introduce new process steps which improve the thermal stability and which can be integrated into a CMOS technology platform without a significant cost increase. No yield issues have been observed up to 700°C 30min post-silicidation thermal budget even for the narrowest silicided silicon lines. NiPtSi encroachment, which is one of the main yield killers for Sub-65nm technologies, has not been seen. The device scalability is not affected and a similar performance has been achieved with an additional post-silicidation thermal budget. Through in-depth understanding of this approach, new integration schemes like for instance a gate-last process flow can be envisioned. [Copyright &y& Elsevier]

Abstract: A study of the implementation of Ni fully silicided (FUSI) gates to scaled devices is presented, addressing the issue of phase control at short gate lengths. A linewidth effect for Ni FUSI gates is found for non-optimized processes targeting NiSi, with formation of NiSi at long gate lengths and Ni-rich silicides at short gate lengths. This is attributed to Ni diffusion from areas surrounding the gates, resulting in a larger reacted Ni–Si ratio at short gate lengths. The linewidth dependence of the Ni FUSI phase results in an undesirable kink in the V t roll-off characteristics, due to the difference in effective work function between the Ni silicide phases, which is particularly large for HfSiON dielectrics. An optimized 2-step RTP silicidation process is shown to eliminate this problem allowing the formation of NiSi gates uniformly at all gate lengths. The application and scalability of Ni-rich silicides to PMOS devices is also demonstrated, as well as a scheme for CMOS integration of dual WF phase controlled FUSI (NiSi for NMOS and Ni-rich silicides for PMOS), using an etch back step to reduce the poly-Si height on PMOS electrodes before full silicidation. [Copyright &y& Elsevier]