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In this paper we present semiconductor nanostructures and devices for future nanoelectronics applications. New device architectures for advanced CMOS as well as novel concepts for a beyond CMOS scenario are presented and discussed. We study SOI Schottky-barrier MOSFETs and show methods for improving the device performance using dopant segregation during silicidation as well as ultrathin body SOI and ultrathin gate oxides. Furthermore, electronic transport in GaN and InN nanowire structures is discussed. In addition, novel device concepts are also introduced and the electronic transport in such structures is studied. In particular, nanoscale resonant tunneling diodes with improved peak-to valley ratio and a band-to-band tunneling transistor based on a nanowire/ nanotube that allows for subthreshold swing smaller than 60mV/dec are presented. [ABSTRACT FROM AUTHOR]

This paper describes low-dimensional nanowire quantum effects that occur in small trigate SOI MOSFETs. 2D numerical simulation is used to calculate the electron concentration profile as a function of gate voltage in devices with different cross sections. The smaller the section, the higher the threshold voltage. A dynamic increase of threshold voltage with electron concentration is observed. Inter-subband scattering causes oscillations of the transconductance when measured as a function of the gate voltage. These oscillations are visible at low temperature (< 30K) in samples with a 45 × 82nm cross section and at room temperature in devices with a 11nm × 48nm cross section. [ABSTRACT FROM AUTHOR]

We present 3-D analytical, scalable models for the threshold voltage roll-off, the subthreshold swing and the DIBL of undoped cylindrical Gate All Around (GAA) MOSFETs. The models are based on an analytical solution of the 3-D Poisson equation. Device geometry dependences are inherent to the models. Excellent agreement has been obtained with 3-D numerical simulations and experimental results. [ABSTRACT FROM AUTHOR]

Conduction band modification due to shear stress is investigated. Mobility in single- and double-gate SOI FETs is modeled for silicon thin body orientation (001) and (110) under general stress conditions. Decrease of conductivity mass induced by uniaxial [110] tensile stress leads to mobility enhancement in the stress direction in ultra-thin body SOI MOSFETs. [ABSTRACT FROM AUTHOR]

The paper reviews achievements and perspectives of building silicon-base resonant tunneling devices in respect to the material and architecture issues, with especial emphasis on the SOI technology. [ABSTRACT FROM AUTHOR]

The procedure for all-quantum 3D simulation of a nanometer scale silicon-on-insulator MOSFET is proposed. It is based on the Büttiker- Landauer approach realized via a self-consistent solution of the Schrödinger and Poisson equations. The stabilization of the numerical solution of the Schrödinger equation is achieved by a finite wave-guide mode presentation of a wave function. We also propose a method to avoid the need for numerical solution of Schrödinger equation for most of the particles (waves) moving from contacts CHECK but those which surmount the selfconsistent barrier and contribute to current. This approach brings greater speed of the simulation program. [ABSTRACT FROM AUTHOR]

We have studied the electron transport properties of two sets of Silicon on Insulator (SOI) nanodevices: i) quantum-well based devices where carriers are quantized in one dimension (1D) and ii) quantum-wire based devices, where carriers are quantized in two dimensions (2D). In the first group, namely quantum-well based devices, the electron mobility dependence on the silicon thickness, Tw in double-gate SOI devices was compared with that in Single-Gate SOI structures. Thus, we determined the existence of a range of silicon layer thicknesses in which electron mobility in DGSOI inversion layers is significantly improved as compared to bulksilicon or SGSOI inversion layers, due to the volume inversion effect. We have also shown that electron mobility is greatly improved in strained Si/SiGe-OI devices, in comparison with unstrained SOI devices. We can conclude that strained-Si/SiGe-on-Insulator inversion layers efficiently combine the improved mobility of strained-Si/SiGe devices with the advantages offered by SOI devices. With regard to quantum-wire based devices, we have analyzed the phonon-limited mobility in silicon quantum wires by means of a one-particle Monte Carlo simulator. It has been observed that an increase of the phonon scattering produces a noticeable reduction of the electron mobility observed when the device dimensions are reduced. Therefore, we have observed that the transition from 2D to 1D electron gas produces a degradation of the electron transport properties. [ABSTRACT FROM AUTHOR]

We have studied, using 3D statistical simulation, the variability in UTB SOI MOSFETs with sub 10nm dimensions introduced by random discrete dopants in the source/drain region, body thickness variation and line edge roughness. We have shown that the random dopants in the source/drain regions are the main source of variability in the studied devices. The results of the physical drift-diffusion simulation with quantum corrections are captured into statistical BSIMSOI compact model which are then used for statistical SRAM simulation. We have shown that SRAMs based on 10 nm UTB SOI transistor have less variability and better yield compared to SRAM based on 35 nm conventional (bulk) MOSFETs. However the scaling of the UTB SOI MOSFETs below 7.5 nm will cause significant yield and reliability problems in the corresponding UTB SOI SRAMs. [ABSTRACT FROM AUTHOR]

Charge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id - Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices. [ABSTRACT FROM AUTHOR]

Two types of mechanical stress, induced by compressive etch stop layer (c-ESL) and/or shallow trench isolation (STI), are examined in advanced p-channel partially depleted SOI MOSFETs. Systematic measurements show that c-ESL significantly enhances the performance of PMOS devices without degrading the short-channel effects. The mechanical stress induced by c-ESL is inhomogeneous through the Si film, decreasing from the top to the bottom interface. We demonstrate that the combination of c-ESL and STI stress is a complex 3-D mechanism, which depends on the layout parameters: channel width (from 0.1 to 1 µm), channel length (down to 23 nm) and source/drain active surface. [ABSTRACT FROM AUTHOR]

The paper analyzes the influence of the Si substrate on the AC characteristics of silicon-on-insulator (SOI) MOSFETs through 2D Atlas simulations and measurements. It is shown that the presence of the Si substrate underneath the buried oxide (BOX) results in two transitions in the frequency response of the output conductance, caused by the variation of the potential at substrate-BOX interface. A first-order small-signal model is proposed to support the obtained results. It is demonstrated that the appearance of "substrate-related" transitions, their position and amplitude depend strongly on the substrate doping, space-charge conditions at substrate-BOX interface, temperature and moreover become more pronounced with device downscaling. [ABSTRACT FROM AUTHOR]

This paper presents a review into the experimental studies of the effective channel mobility and intrinsic gate leakage current in triple-gate FinFET structures with doped- and undoped-channels and different gate stacks. The characteristics of narrow-fin devices are studied as compared to those of quasi-planar (very-wide fin) devices, and as a function of the fin width. Special features in the behavior of narrow FinFETs are analyzed. [ABSTRACT FROM AUTHOR]

The changes in the low-frequency noise of SOI MOSFETs accompanying their nanoscaling are considered. The behaviour of the 1/f noise in the course of downscaling as well as the influence of the additional noise sources appearing in the nanoscaled devices on their noise characteristics are explained. It is shown that the drastic changes in the noise performance of the devices can take place as a result of their nanocsaling. [ABSTRACT FROM AUTHOR]

Our UK consortium has recently reported advanced RF platform technology, which includes SiGe Heterojunction Bipolar Transistors (HBT) on Silicon-On-Insulator (SOI). The study in this paper is the continuation of the consortium work, focused on fabricating SiGeC HBTs and on the impact of C (up to 1.6?) on device performance. The devices with low C content (0.45?) exhibit excellent performance and gain up to 500. The results indicate that C content to be used in these devices should be less than 1?. [ABSTRACT FROM AUTHOR]

Random doping fluctuation effects are studied in multiple-gate SOI MOSFETs (MuGFETs) using numerical simulation. The presence of a single doping impurity atom increases threshold voltage. Electrical parameters vary with the physical location of the impurity atom. [ABSTRACT FROM AUTHOR]

An increase in threshold voltage is observed in ultra-thin body MuGFET (multi-gate FET) devices. The threshold increase is due to of lack of carriers at the classical threshold definition. A sufficient amount of carrier build-up requires additional gate voltage (0.12V in our experiment). [ABSTRACT FROM AUTHOR]

The electronic and optical phenomena, as well as possible device-oriented application in Ge/Si and Ge/SiO2 nanodots that have been synthesized by molecular-beam growth are the scope of this article. We focus on the fundamental aspects and device applications of the small size dots whose electronic states resemble those of an atom even at room temperature. [ABSTRACT FROM AUTHOR]

Recent research and development of silicon single-electron transistors are reviewed. The fabrication process of extremely small silicon dot in the channel of MOS transistors has been advanced, and the dot size is now as small as 2 nm. Consequently, the single-electron transistors operate at room temperature and the peak-to-valley current ratio of the Coulomb blockade oscillations reaches as high as 480 at room temperature. The attempts to integrate the single-electron transistors and to develop new circuit applications are also described. [ABSTRACT FROM AUTHOR]

Scaling of MOSFET physical dimensions is approaching the nanoscale regime, which causes increase of short-channel effects such that the electrical performance of classical MOSFET structure is becoming seriously degraded. The limits of silicon scaling have been the major challenge for technologists for the past years. With the 90 nm generation in production and despite many roadblocks, the latest International Roadmap for Semiconductors 2005 expects that CMOS can be scaled down to 16 nm, by introducing new transistor architectures and materials. In this paper, we propose fabrication of a non-classical device architecture namely the "Quadruple-Gate MOSFET" which is based on definition of narrow, suspended silicon fins defined by electron-beam lithography into the topsilicon film of a Silicon-on-Insulator (SOI) wafer. [ABSTRACT FROM AUTHOR]

This paper reviews progress in vacancy engineering using a silicon implant into SOI substrates and considers the prospects for vacancy engineering using fluorine implantation. Vacancy engineering using a silicon implant comprises a high energy silicon implant into an SOI substrate, to separate the excess vacancies in the SOI layer and the excess interstitials below the buried oxide. Results on vacancy-engineering show that a properly optimized high energy silicon implant is able to suppress boron transient enhanced diffusion. Results are also presented on the behaviour of fluorine in bulk silicon and it is shown that a high energy fluorine implant not only completely suppresses boron transient enhanced diffusion but also significantly reduces boron thermal diffusion. The suppression of boron thermal diffusion is due to the formation of vacancyfluorine clusters that form at approximately half the range of the fluorine implant. Finally, fluorine implantation is applied to SOI wafers, with the aim of separating the vacancy-fluorine clusters in the active layer from interstitial dislocation loops below the buried oxide layer. These results show a high energy fluorine implant into SOI substrates is also effective in suppressing boron diffusion. [ABSTRACT FROM AUTHOR]

Bulk silicon devices are unlikely to be feasible for the planar 22 nm technological node due to commensurate degradation of carrier mobility. New types of substrate are therefore needed for further scaling in CMOS microelectronics. We consider here semiconductor heterostructure on insulator (HOI) which are compatible with current silicon planar CMOS technology. Specfically, we investigate effects associated with interface mediated endotaxial (IME) growth of thin semiconductor film at Si/SiO2 bonded interface which are experimentally observed and investigated for the first time. The semiconductor material stack was obtained by hydrogen transfer of one layer material (silicon) and a second one (germanium or indium antimonide) placed on amorphous silicon dioxide film. Firstly, thin film dual layer Si-Ge heterostructure properties were considered. Si-Ge HOI structures were obtained using Ge ion implantation into silicon dioxide followed by Ge segregation to the interface between the directly bonded silicon and silicon dioxide wafers. The method is also compatible with A3B5 thin film formation, as shown for an InSb film. Thermodynamic, kinetic and lattice mismatch parameter influences on IME process are considered. [ABSTRACT FROM AUTHOR]

The combination of ultra-thin body (UTB), undoped silicon-oninsulator films to control short channel effects and high permittivity (κ) gate dielectric with metal gate to control gate leakage current, can provide a highly scaleable technology to address challenges towards the end of the road map. This paper sets out the basic issues and physics associated with both hi- κ/metal gate and UTB from a device perspective, and establishes the advantages associated with merging the two approaches. A review of the state-of the art devices is undertaken also which serves to emphasize the great potential and progress of this technology. [ABSTRACT FROM AUTHOR]

In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and manufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances. [ABSTRACT FROM AUTHOR]

A review of recently explored new materials and architectures for SOI nanodevices is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The electrical properties in multi-gate Si, SiGe, Ge and GaAs MOSFETs and Nanowires realized with various channel orientations are also addressed. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined. [ABSTRACT FROM AUTHOR]