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The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as C n = 2 × C n − 1 , the variable capacitor C n of ADC1 can be updated to be closest to the sum of C n − 1 of ADC1 and C n − 1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the C n of ADC1 can be connected with two of the C n − 1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update C n . This process is iterated, until C n is in agreement with the sum of two of C n − 1 . Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively. [ABSTRACT FROM AUTHOR]

Featured Application: The proposed technique can be applied to minimize capacitor mismatch error in pipeline analog-to-digital converters. This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. Although the calibration method is employed in a 1.5-bit stage architecture, which uses a gain-of-two switched-capacitor amplifier, it is applicable to different bit-per-stage architectures. The ADC linearity significantly improves after calibration, and this is verified through simulations and measurements. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

Capacitive DACs (C-DACs) are widely used as stand-alone DACs or in an ADC as auxiliary DACs. An important performance metric of a C-DAC is its energy consumption and the linearity between the digital input and the analog output. In multi-bit C-DACs, the mismatch between the capacitors can degrade linearity, which can be important in high-resolution applications. In this work, we analyze the power consumption and linearity performance of a class of C-DACs called split-array C-DACs. We show that the simple element rotation technique, which is widely used to suppress the mismatch error of DACs, cannot be used with the power-efficient three-level switching scheme to effectively suppress the mismatch error. Then, we propose a switching scheme which can be used with the power efficient three-level switching and can suppress the in-band mismatch error effectively. [ABSTRACT FROM AUTHOR]

An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of 103.5 μ W , leading to a Figure of Merit of 8.93 fJ/Conversion-step. [ABSTRACT FROM AUTHOR]

This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that reduce the RA gain error due to their finite open-loop gain, the proposed DACLS ring amplifier no longer requires an extra level-shifting capacitor ($C_{\mathrm {LS}}$) at the RA output, such that the RA bandwidth can be improved. Furthermore, instead of a single-level shift in the prior arts, the DACLS ring amplifier provides an option for multiple level shifts and thereby accomplishes a greater RA gain error reduction. In addition, a customized bypass-window scheme is applied, which can skip some power-wasting digital-to-analog converter (DAC) switchings by window detection and thus reduces the power consumption of the ADC. To reduce the bit-cycling time of the SAR conversion, a delay-reduced (DR) SAR logic is introduced to increase the ADC speed. The ADC chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.013 mm2. At 130-MS/s and the Nyquist-rate input frequency, the measured SNDR is 72.5 dB, while the power consumption is only 0.82 mW. Without any calibration, the proposed ADC achieves a Walden and a Schreier figure-of-merit (FoM) of 1.8 fJ/conversion step and 181.5 dB, respectively. Compared to the prior-art ADCs with an input bandwidth ≥ 40 MHz and a SNDR > 68 dB, this work shows the best FoMs. [ABSTRACT FROM AUTHOR]

In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude. [ABSTRACT FROM AUTHOR]

This article presents an energy-efficient noise-shaping successive-approximation register (SAR) capacitance-to-digital converter (CDC) for high-resolution capacitive sensor applications. Based on a 12-bit SAR architecture, quantization noise is shaped by the first-order FIR-IIR loop filter. The proposed loop filter comprises dynamic amplifiers (DAs), and it is designed to be insensitive to DA gains’ variations. Under process, voltage, and temperature (PVT) variations, the loop filter is stable and retains in-band noise suppression ability without the gain calibration. The CDC is implemented in a differential configuration for a single-sensor measurement with an energy-efficient capacitive digital-to-analog converter (CDAC) switching method. It does not require any replica or dual capacitor sensor for differential operation. In the proposed CDC, a dynamic comparator with a common-mode (CM) rejection is proposed to compensate for the instability because the parasitic capacitance causes CM voltage deviation of the CDAC and loop instability. The proposed CDC is fabricated in a 180-nm CMOS technology with an active area of 0.25 mm2. It dissipates 63.3 $\mu \text{W}$ at a sampling frequency of 320 kHz. Given that all circuits operate dynamically, the sampling frequency is scalable from 3.2 to 320 kHz. The prototype CDC achieves an 88.9-dB signal-to-noise ratio (SNR) and a figure-of-merit of 139 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

A 12-bit 20-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented by using the digital place-and-route (DPR) tools. The macrocells for the capacitive digital-to-analog converter, the bootstrapped switch, and the dynamic comparator are presented. The custom standard cells for the dynamic SAR logic are also presented. By using the macrocells and the custom standard ones, the layout of this SAR ADC is completed by using the DPR tools. Several techniques are presented to improve the parasitic capacitances, the current density of the metal interconnections, and the nonideal effects caused by the DPR tools. This SAR ADC is fabricated in 40-nm CMOS technology and its active area is 0.0067 mm2. To compare with the full-custom method, the proposed DPR flow has speeded up by a factor of 288 to complete the interconnection wires. Its power dissipation is 363 $\mu \text{W}$ at 20 MS/s and the calculated Walden FoM is 23 fJ/c. step at Nyquist frequency. [ABSTRACT FROM AUTHOR]

This article presents a second-order noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital-predicted mismatch error shaping (MES). The loop filter is composed of an active amplifier and two cascaded passive integrators to provide a theoretical 30-dB in-band noise attenuation. The amplifier achieves $18\times $ gain in a power-efficient way thanks to its inverter-based topology and duty-cycled operation. The capacitor mismatch in the digital-to-analog converter (DAC) array is mitigated by first-order MES. A two-level digital prediction scheme is adopted with MES to avoid input range loss. Fabricated in 65-nm CMOS technology, the prototype achieves 80-dB peak signal-to-noise-and-distortion-ratio (SNDR) and 98-dB peak spurious-free-dynamic-range (SFDR) in a 31.25-kHz bandwidth with $16\times $ oversampling ratio (OSR), leading to a Schreier figure-of-merit (FoM) of 176.3 dB and a Walden FoM of 14.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This article presents a detailed analysis of the impact of the tank feedline on tuning range (TR) and phase noise (PN) in millimeter-wave LC voltage-controlled oscillators (VCOs). A robust extended TR design, with low PN and small die area, is later proposed, analyzed, and experimentally validated. A new interconnect approach for the coarse tuning capacitor bank is used to significantly reduce the LC tank routing capacitance and resistance, thus improving the TR and PN of the VCO. As a proof of concept, a 26.8-GHz VCO with a 5-bit digitally switched-capacitor bank [capacitor digital-to-analog converter (C-DAC)] is implemented using a folded feedline routing structure in a digital 45-nm CMOS silicon-on-insulator (SOI) technology. Compared to a conventional layout structure, the proposed interconnect technique yields a wider TR and lower losses while significantly improving the linearity of the C-DAC. The fabricated VCO yields a TR of 33%, covering the extended 5G frequency band with a sufficient margin from 22.4 to 31.2 GHz, with a minimum overlap of 40%. Moreover, it achieves a PN of −105.5 and −97.2 dBc/Hz at a 1-MHz offset at the low and high bands, respectively, while dissipating 6 mW from a 1.0-V supply, corresponding to an average FOMT of −192.6 dBc/Hz. [ABSTRACT FROM AUTHOR]

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62- $\mu \text{W}$ power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/−1 and 4.78/−3.31 LSB, respectively. [ABSTRACT FROM AUTHOR]

This manuscript introduces a low-power mixed-signal foreground calibration algorithm of a pipeline analog-to-digital converter (ADC) using a digitally controlled reconfigurable switched-capacitor multiplying digital-to-analog converter (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain toward its ideal value to achieve the ideal ADC output linearity. In this brief, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital back-end unit response. The proposed method has been simulated using a 0.18- $\mu \text{m}$ CMOS process. An 11-bit pipeline ADC with a 1.5-bit stage followed by a ten bit linear back-end ADC (BE-ADC) has been used to calibrate the non-linearity of the said 1.5-bit stage. Using a low amplifier gain value of 28 dB, the signal-to-noise-and-distortion ratio (SNDR) of the ADC improves from 46.21-dB pre-calibration to 65.13-dB post-calibration. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage 12-times frequency multiplier composed of an invented harmonic generator (HG) and a modified cascode buffer. The reliable output frequency band is guaranteed from 16 GHz to 28 GHz (54.5% frequency range). The whole band is divided to 256 subsidiary frequency bands by applying 8-bit digitally controlled capacitor banks of LC (inductor and capacitor)-tuned output. The invented HG architecture is based on a double-balanced mixer, but the bottom and top differential pairs are appropriately biased to generate the required turn-on time,τ, for obtaining the more dominant desired 12th harmonic. In addition, to reduce power consumption and conversion gain variation for the target frequency band, a negative-gm differential pair is added to the HG core in parallel to enhance the equivalent parasitic resistance, which is directly proportional to the HG gain. Newly created automatic constant amplitude control is able to keep the HG amplitude output constant as well as keep it from oscillating. Further desired harmonic amplification and unwanted suppression can be achieved by the proposed cascode buffer. The proposed 12-times multiplier is fabricated on a 65-nm CMOS (complementary metal-oxide-semiconductor) process and successfully tested. Chip die size is 0.4 mm2, and power consumption is only 4 mW. [ABSTRACT FROM AUTHOR]

In order to achieve high resolution in Successive Approximation Register (SAR) Analog to Digital Converter (ADC), a novel noncoupling capacitor split capacitor array structure is proposed, which solves the coupling capacitor mismatch problem in the traditional split capacitor array structure. This paper analyzes the structure and its capacitor array mismatch. Based on the structure and analysis, a 12-bit SAR ADC is designed and implemented in GSMC 0.11  μ m CMOS process. The measured results show that the Signal to Noise Ratio (SNR) is 72.61 dB and Effective Number Of Bits (ENOB) is 11.77 bit, which prove the advantages of this structure in the design of high resolution SAR ADC. [ABSTRACT FROM AUTHOR]

This article presents a 23–28-GHz digital-controlled phase-invariant and ultralow gain error variable gain amplifier (VGA) for 5G applications. The mechanisms of gain control and phase variation in CMOS VGA based on single-level transistor structure are analyzed in detail. According to the analysis, an active cross-coupling neutralization (ACCN) technique is proposed. The ACCN technique not only compensates for phase variation, but also makes phase compensation insensitive to the process, supply voltage, and temperature (PVT) variations. For achieving ultralow gain error, an asymmetric capacitive gain resolution improvement (ACGRI) technique is adopted, which realizes a fine gain step with low control circuit complexity. Further to reduce gain error, greatly improving the accuracy and robustness against PVT of gain control is necessary. With regard to this, a current-type digital-to-analog converter (DAC) is also integrated onto the chip. The proposed VGA is demonstrated in 65-nm CMOS technology with a core chip area of 0.14 mm2. Under 5-b digital gain control conditions, the presented VGA achieves a measured linear gain tunability range of 6.2 dB with a 0.2-dB fine tuning step. The measured root mean square (rms) phase error is less than 0.92° across 24–28 GHz with a minimum value of 0.63° at 27.8 GHz. The rms gain error is less than 0.13 dB, with a minimum value of only 0.03 dB at 25 GHz. At the maximum gain state, the proposed CS VGA exhibits a peak gain of 29.4 dB with 3-dB bandwidth of 23.5–27.5 GHz and the minimum noise figure is 4.8 dB at 26 GHz. Besides, the measured OP1dB and OP3dB are 6.3 and 9.6 dBm, respectively. The influence of VT variations on the phase compensation and gain tuning is also measured, and the proposed VGA exhibits strong robustness. [ABSTRACT FROM AUTHOR]

We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7- and 47.2-dB SNDRs in 6- and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively. [ABSTRACT FROM AUTHOR]

A 16-GS/s single 1.2-V supply direct RF-sampling capacitive D/A converter for soft radio base-station applications is implemented in a 16-nm FinFET technology. Due to co-integration with a wideband on-chip matching network, the D/A converter (DAC) is capable of signal synthesis between 600 MHz and 8 GHz, with a measured peak RF output power of +5.6 dBm. The linearity required by cellular base-station applications is achieved by employing several analog-domain linearization techniques, yielding a two-tone intermodulation distortion of better than −70 dBc up to the first Nyquist frequency. When transmitting a true multiband signal covering an instantaneous bandwidth of 1 GHz, an adjacent channel leakage ratio (ACLR) of better than −69 dBc is achieved. Digital segment mismatch correction is shown to improve the linearity of a segmented DAC in deep digital backoff operation. A full-rate digital pre-distortion (DPD) method with efficient model identification is experimentally demonstrated. Using DPD, the design achieves an spurious free dynamic range (SFDR) of better than 72 dBc over the entire 0.6–6-GHz frequency range. [ABSTRACT FROM AUTHOR]

A low-power 113-dB SNR, −93-dB total harmonic distortion (THD)+N, digital input $\Delta \Sigma $ -based filter-less Class-D amplifier for wireless headphone applications is presented. This performance is achieved by the following architecture improvements: 1) variable-frequency- $\Delta \Sigma $ Class-D with digital feed-forward and switching-frequency reduction, 2) common-mode-stabilized power stage, 3) current digital-to-analog converter direct drive, and 4) rotational first-order dynamic-element-matching techniques. It operates on a single 1.8-V power supply with no external passive components except for a supply decoupling capacitor. The Class-D headphone amplifier achieves 82-mW non-clipping output power with 93% efficiency at a 16- $\Omega $ and 33- $\mu \text{H}$ load condition. The complete system was fabricated in a 40-nm CMOS process and occupies 1.33-mm2 die area. [ABSTRACT FROM AUTHOR]

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4 $\times $ passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 $\mu \text{W}$ power from a 1.1-V supply and occupies 0.061 mm2 area. [ABSTRACT FROM AUTHOR]

This study proposes a capacitor switching scheme that reduces both the energy consumption and area through multiple reference voltages of a capacitive digital to analog converter (CDAC), a component of successive approximation register (SAR) analog to digital converter (ADC). With a 10-bit SAR-ADC, if the reference voltage is used as 3-bit with a 6-bit capacitor array, the energy and area (number of capacitors) are reduced by 99.97 % and 93.75 %, respectively. Furthermore, we propose a switching algorithm that minimizes energy consumption, which is proven analytically. [ABSTRACT FROM AUTHOR]

An 8-bit 10-GHz 8 $\times $ time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range (SFDR) by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts. [ABSTRACT FROM AUTHOR]

This article presents a compact $2\times $ time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC’s architecture is based on parallel charge redistribution and separates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm2 in 16-nm CMOS and supports up to 0.32- $\textrm {V}_{\textrm {pp}}$ signal swing across its differential 100- ${\Omega }$ load. It achieves an SFDR $\geq 37$ dB and an IM $3\leq -45.6$ dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply. [ABSTRACT FROM AUTHOR]

The authors present a dither‐less background digital bit weights calibration method for split‐capacitor digital‐to‐analog converter (CDAC) successive approximation register (SAR) analog‐to‐digital converters (ADCs) to improve non‐linearities caused by capacitor mismatch and bridge‐capacitor inaccuracy errors in a split‐CDAC. By using a digital pseudo‐random number (PN) generator and paired comparators with opposite offsets, a dither‐less background calibration quickly reaches the target signal‐to‐noise‐and‐distortion ratio (SNDR) within 5 × 104 samples for various process uncertainties. The simulated performance using a behavioural 6‐bit + 6‐bit ADC with 1‐bit redundancy for various random offset and capacitor mismatches shows that the SNDR increases from 45.7 to 65.7 dB after the calibration. [ABSTRACT FROM AUTHOR]

A single-channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) is presented, which features its speed expanding with conversion mode. The reconfigurable capacitor digital to analog converter (CDAC) is proposed to achieve multiple conversion modes without wasting capacitance. In 1-b/cycle conversion mode, the proposed ADC can achieve the sampling rate of 60-Ms/s and 9-b resolution. Based on the 2-b/cycle conversion mode, the proposed ADC can double the sampling rate and be reconfigured as a 120-MS/s, 8-b converter. Besides, the detection skip algorithm and charge sharing technology are involved to remove the precharge operation time and reduce the switching energy consumption. Moreover, the control logic is optimized to minimize the chip area and matches the reconfigurable characteristics well. A prototype ADC is fabricated in the 180-nm standard CMOS process, which achieves the 54.1-/46.7-dB signal-to-noise-plus-distortion ratio (SNDR) at 60-/120-MHz sampling frequency with the power consumption of 1.9/3.5 mW. The prototype ADC achieves a peak figure of merit (FoM) of 77-fJ/Conv.step at 2-b/cycle conversion mode. The ADC core occupies an active area of only 0.12 mm2. [ABSTRACT FROM AUTHOR]

This paper proposes a three-level buck converter utilizing a Digital-to-Analog Converter (DAC)-based flying capacitor voltage control technique, which controls the voltage on a flying capacitor with a differential difference amplifier and common mode feedback circuit for stable operation. Employment of the DAC-based flying capacitor voltage control circuit allows the proposed circuit to compensate for the inductor voltage error as the load current varies. The proposed three-level buck converter was implemented with a CMOS 180 nm standard process. The measurement results demonstrate the wide range of the input and output voltage from 2.7 V to 3.6 V and 0.7 V to 2.4 V, respectively. The proposed three-level buck converter achieved the peak power efficiency of 91% and output ripple voltage of 32.5 mV at the switching frequency of 2 MHz and load current range of 10 mA to 400 mA. [ABSTRACT FROM AUTHOR]

A 5-bit active digital step attenuator (DSA), which simultaneously achieves low amplitude and phase variations, is proposed for wideband phased-array applications. The input and output impedances for each attenuation unit under the reference state and the attenuation state can remain basically the same. Therefore, the amplitude and phase errors caused by a load impedance mismatch between each unit can be alleviated. Implemented in 130-nm silicon–germanium (SiGe) BiCMOS technology platform, the proposed DSA provides a maximum attenuation range of 15.5 dB with 0.5-dB steps. It exhibits an insertion loss (IL) less than 13 dB and input/output return losses less than −10 dB from 31 to 41 GHz. In addition, with the help of minimized amplitude and phase variations, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.2 dB and an rms phase error less than 2.5° at 33–41 GHz, which are the lowest such errors ever reported. The chip core area of the DSA is 0.22 mm2 (0.5 mm $\times0.44$ mm). It shows a suitable performance for 5G applications. [ABSTRACT FROM AUTHOR]

A highly energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the merge-and-split technique, which eliminates the need of the extra reference voltage (Vcm). The switching procedure is performed on the simple binary weighted capacitor arrays without any capacitor-splitting. Compared with the conventional scheme, the proposed switching scheme can achieve 98.45% saving in switching energy and 75% capacitors-area reduction. Besides, because two capacitor arrays are switched symmetrically, the common-mode voltage of capacitive digital-to-analog converter (CDAC) keeps constant until the LSB cycle. The proposed switching scheme is verified in a 0.6-V 10-bit 200-kS/s SAR ADC in 40 nm CMOS technology. [ABSTRACT FROM AUTHOR]

In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB. [ABSTRACT FROM AUTHOR]

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This work introduces a second-order voltage-controlled oscillator (VCO)-based continuous-time delta–sigma modulator (CTDSM) that incorporates a distributed-input VCO as the second-stage integrator and quantizer. The distributed-input VCO topology virtually eliminates the VCO’s voltage-to-frequency (V-F) parasitic pole. One of the key ideas of this article is to demonstrate the use of a capacitive- $\pi $ network in the modulator’s loop filter to break the constraint between the size of the modulator’s inner capacitive digital-to-analog converter (DAC) and the factor by which the front-end Gm-C integrator is impedance scaled. This, in turn, helps to significantly reduce both analog and digital powers. The prototype chip has been fabricated in a 40-nm CMOS process. Despite not using any DAC calibration or explicit dynamic element matching (DEM) circuits, the worst case spurious-free dynamic range (SFDR) is −82 dBc across the signal bandwidth. The fabricated CTDSM achieves a 71.8-dB signal-to-noise-and-distortion ratio (SNDR) and a 74.5-dB dynamic range (DR) in a 10-MHz bandwidth at 655 MS/s, yielding an SNDR-based Walden figure of merit (FoM) of 45.6 fJ/step, an SNDR-based Schreier FoM of 167.2 dB, and a DR-based Schreier FoM of 169.9 dB. [ABSTRACT FROM AUTHOR]

This work proposed a binary-weighted Digital-to-Analog Converter (DAC), which is designed to be used in Asynchronous successive approximation register (SAR) based Analog-todigital converters (ADCs) specifically and in other relevant operations. The design has yielded an improved slew rate, and it is less prone to noise as the size of capacitors is taken in accordance with KT/C noise calculation. For achieving all mentioned goals, and to restrict the size of DAC, within suitable dimensions charge scaling DACs are used. One more advantage of this design is its accuracy, further it does not require op-Amps for its operation. Results of statistical simulation and mathematical consideration are published which depicts the supremacy of the design. A highresolution DAC designed for this specific purpose has to have special consideration for the effect of local mismatch, parasitic and matching of the capacitors, for that, the common-centroid approach has been followed. This design has displayed a high resolution with small unit capacitances and that too without expensive factory calibration. [ABSTRACT FROM AUTHOR]

High speed data converter architectures such as pipelined analog-to-digital-converters (ADCs) typically consist of large capacitor arrays that are highly susceptible to systematic errors. Although significant efforts have been made in the literature to compensate linear and parabolic errors, the rotated parabolic components are less explored. These rotated parabolic components are responsible for spurious harmonics at the output of the converter, thereby degrading the linearity. In this article, we have investigated the origin of these rotated components, their impact on conversion linearity and discussed strategies to mitigate them. A placement technique along with one track routing solution, is proposed for complete compensation of the systematic errors. An algorithm is also provided to extend this technique to higher resolutions. The proposed technique is verified on the model of pipelined ADC, as well as current steering DAC. The incorporation of such technique results in near ideal linearity performance. [ABSTRACT FROM AUTHOR]

A search algorithm is presented for a switching scheme with a small number of unit capacitors for a digital-to-analog converter (DAC) used in a successive approximation register (SAR) analog-to-digital converter (ADC). The iterative algorithm is intended to build a binary tree for switching a charge-sharing DAC using a minimum possible number of capacitors. The resulting scheme does not increase the number of clock cycles for the binary search. The relationship between ADC resolution and the number of capacitors proves to be linear, in contrast to an exponential relationship usual for the capacitor arrays. Compared to a previously reported low-power and compact scheme, in a 10-bit case, a 76% reduction in capacitor count is achieved. The simulation results in a 65-nm CMOS technology with a sampling rate of 100 kS/s are presented. [ABSTRACT FROM AUTHOR]

This paper presents an augmented design method for the dc/dc modular multilevel converter considering the control (e.g., the phase difference between arms ac voltages) and hardware aspects (e.g., type and number of submodules (SMs)) of the converter simultaneously. The proposed augmented design determines the number of SMs and their types (e.g., half- or full-bridge) in each arm and phase difference between arms ac voltages that minimize the total converter losses. Computationally-efficient analytical and semi-analytical methods are proposed to estimate the conduction and switching losses. To verify the effectiveness of the proposed method, the losses obtained from the proposed analytical and semi-analytical methods are compared with the results of the detailed converter switching model implemented in the Simulink environment. The performance of the converter designed by the augmented approach is compared with the conventional topology in terms of total losses and the number of SMs. The comparative study showed that the proposed design method yields a converter with lower total losses and number of SMs. Moreover, the proposed design method extends the operation regime of the converter, especially when the dc links voltage levels are close; this extension is not possible in the conventional modular dc/dc converter. [ABSTRACT FROM AUTHOR]

This article presents a Gm-C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional–integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 $\mu \text{W}$ with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment. [ABSTRACT FROM AUTHOR]

Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

An energy-efficient switching scheme with low common-mode voltage variation and simple capacitor array for successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitor-splitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed scheme achieves 98.45% saving in switching energy and 75% saving in total capacitors area compared with the conventional switching scheme. Furthermore, the voltage variation on positive and negative sides of capacitive digital-to-analog converter (CDAC) is equal in magnitude and opposite in direction until the last bit cycle, therefore the dynamic common-mode voltage variation range of CDAC is only 0.5LSB. Employing the proposed switching scheme, a 10-bit 200-kS/s 0.6-V SAR ADC is designed in 40-nm CMOS technology. Post-layout simulation results indicate that a SNDR of 57.1 dB can be achieved with the Nyquist input at 200-kS/s. The figure-of-merit of the proposed ADC is 1.37fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single—time-varying—transconductance and integration capacitor. The transconductance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating principle is shown step by step, including its complete transfer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22-nm FDSOI, has an active area of 0.09 mm 2. Its bandwidth can be accurately tuned from 0.06 to 3.4 MHz. The filter consumes 92 $\mu \text{W}$ from a 700-mV supply. This low power consumption is combined with a high selectivity: $\text{f}_{-60\,\text {dB}}/\text{f}_{-3\,\text {dB}}\,\,=$ 3.8. The filter has 31.5-dB gain and 12-nV/ $\sqrt {\text {Hz}}$ input-referred noise for a 0.43-MHz bandwidth. The OIP3 is 28 dBm, independent of the frequency offset. The output-referred 1-dB-compression point is 3.7 dBm, and the in-band gain compresses by 1 dB for an −3.7-dBm out-of-band input signal while still providing >60 dB of filtering. [ABSTRACT FROM AUTHOR]

This article presents the theoretical analysis of passive charge sharing-based segmented successive-approximation-register (SAR) analog-to-digital converter (ADC), where the precise reference source in a capacitive digital-to-analog converter (CDAC) is replaced by a capacitor that is $\beta $ times larger than its bit capacitor and precharged to the reference level, known as a reference charge reservoir (RCR). A segmented SAR-ADC uses a coarse SAR-ADC to compute some most significant bits (MSBs). Four methods, namely aligned switching (AS) with bitwise RCRs, AS with a subsample-wise RCR, detect-and-skip aligned switching (DAS-AS) with bitwise RCRs, and DAS-AS with a subsample-wise RCR are introduced for setting fine MSBs. Closed-form analytic expressions of the reference error due to the finite reference capacitance are derived and validated by behavioral modeling and circuit simulation of an 11-bit 50 MS/s segmented SAR ADC in 65-nm CMOS technology. The error expressions can be used to select one of the four methods for setting the fine MSBs and to determine $\beta $ for the required linearity or for implementing digital circuitry for precise error correction. [ABSTRACT FROM AUTHOR]

This paper presents a high-precision, successive-approximation-register (SAR) analog-to-digital converter (ADC) with maximum input range of ±10 V for industry applications, where the wide-range input signal is sampled directly on part of the capacitive digital-to-analog converter (CDAC) via high-voltage (HV) sampling switches. An inherent 2-b coarse ADC is designed to avoid charge leakage under large input signal, which is reused for nonlinearity compensation from the sampling switch's resistance, while the nonlinearity due to clock feedthrough is compensated by a binary capacitor array. A capacitance reduction structure is used in the CDAC with redundant bits to save the CDAC's area. Fabricated in a 180-nm CMOS process with HV option, the ADC achieves 102-dB SNDR and 120-dB SFDR under 1.5 MSPS throughput. The overall power consumption without BGR and reference buffer is 34.4 mW under ±11-V bipolar HV supplies for sampling network and 1.8-V supply for the core circuits, corresponding to a FoMs of 175.4 dB, respectively. The entire chip occupies 7.2-mm2 area. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]