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The goal of this paper is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based HEMTs. To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several WG = 2 mm p-type GaN HEMTs with different LGD or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed-up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 kHz to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on RON compared to off-state stress. Third, by comparing the results on identical devices having shorter LGD, we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer) we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.

The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage (Vth) for MoS2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS2 inverter arrays with an optimized inverter switching threshold voltage (VM) of 1.5 V and a DC voltage gain of 27 at a supply voltage (VDD) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS2 film.

This paper reports a MEMS disk resonator gyroscope (DRG) with superior overall performance in terms of bias instability, measurement range, and size. Specifically, a fully filled electrodes MEMS DRG is proposed to improve sensing capacitance to 23.66 pF and drive capacitance to 6.14 pF. The DRG is fabricated using a wafer-level vacuum-package process and is controlled and sensed by a configurable ASIC, enabling a small footprint. The DRG achieves an angle random walk (ARW) of 0.05/h and bias instability of 0.42/h within a full scale of 300/s, making it a very promising solution for angular measurement in high-end industrial applications.

Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs' output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only 60 μm by 1900 μm which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

In this paper, an evaluation of machine learning classifiers to be applied in wafer defect detection is described. The objective is to establish the best machine learning classifier for Wafer Defect Detection application. k-Nearest Neighbours (k-NN), Logistic Regression, Stochastic Gradient Descent, and Support Vector Machine were evaluated with 3 defects categories and one non-defect category. The key metrics for the evaluation are classification accuracy, classification precision and classification recall. 855 images were used to train, test and validate the classifier. Each image went through the embedding process by InceptionV3 algorithms before the evaluated classifier classifies the images.

In semiconductor foundries, wafer map defect analysis is crucial to prevent yield excursion. However, traditional manual inspection can hardly meet the high throughput demand. Deep learning based automatic defect detection shows promising efforts to achieve high accuracy and efficiency, yet the current approaches’ performance is limited by the imbalanced dataset and lack of interpretability. In this paper, we propose a Variational Autoencoder Enhanced Deep Learning Model (VAEDLM) for wafer defect imbalanced classification. It is light-weighted and effective in wafer defect pattern recognition on imbalanced dataset. It used variational autoencoder and decoder to generate similar wafer defect maps and a refined deep convolutional neural network for feature learning. We demonstrate the method using an authentic wafer map dataset, WM-811K. The performance is not only significantly improved after data augmentation, but it also beats the state-of-the art methods, reaching 99.19% accuracy, 99.10% recall, 99.23% precision, 99.96% AUC and 99.16% for F1-score. It clearly demonstrates the method’s efficacy to deal with the imbalanced defect pattern. Our study using saliency map and t-SNE further leads to enhanced interpretability.

While two-dimensional (2D) hexagonal boron nitride (h-BN) is emerging as an atomically thin and dangling bond-free insulating layer for next-generation electronics and optoelectronics, its practical implementation into miniaturized integrated circuits has been significantly limited due to difficulties in large-scale growth directly on epitaxial semiconductor wafers. Herein, the realization of a wafer-scale h-BN van der Waals heterostructure with a 2 in. AlGaN/GaN high-electron mobility transistor (HEMT) wafer using metal-organic chemical vapor deposition is presented. The combination of state-of-the-art microscopic and spectroscopic analyses and theoretical calculations reveals that the heterointerface between ∼2.5 nm-thick h-BN and AlGaN layers is atomically sharp and exhibits a very weak van der Waals interaction without formation of a ternary or quaternary alloy that can induce undesired degradation of device performance. The fabricated AlGaN/GaN HEMT with h-BN shows very promising performance including a cutoff frequency (fT) and maximum oscillation frequency (fMAX) as high as 28 and 88 GHz, respectively, enabled by an effective passivation of surface defects on the HEMT wafer to deliver accurate information with minimized power loss. These findings pave the way for practical implementation of 2D materials integrated with conventional microelectronic devices and the realization of future all-2D electronics.

The semiconductor, β-Ga2O3 is attractive for applications in high power electronic devices with low conduction loss due to its ultra-wide bandgap (∼4.9 eV) and large Baliga's figure of merit. However, the thermal conductivity of β-Ga2O3 is much lower than that of other wide/ultra-wide bandgap semiconductors, such as SiC and GaN, which results in the deterioration of β-Ga2O3-based device performance and reliability due to self-heating. To overcome this problem, a scalable thermal management strategy was proposed by heterogeneously integrating wafer-scale single-crystalline β-Ga2O3 thin films on a highly thermally conductive SiC substrate. Characterization of the transferred β-Ga2O3 thin film indicated a uniform thickness to within ±2.01%, a smooth surface with a roughness of 0.2 nm, and good crystalline quality with an X-ray rocking curves (XRC) full width at half maximum of 80 arcsec. Transient thermoreflectance measurements were employed to investigate the thermal properties. The thermal performance of the fabricated β-Ga2O3/SiC heterostructure was effectively improved in comparison with that of the β-Ga2O3 bulk wafer, and the effective thermal boundary resistance could be further reduced to 7.5 m2K/GW by a post-annealing process. Schottky barrier diodes (SBDs) were fabricated on both a β-Ga2O3/SiC heterostructured material and a β-Ga2O3 bulk wafer. Infrared thermal imaging revealed the temperature increase of the SBDs on β-Ga2O3/SiC to be one quarter that on the β-Ga2O3 bulk wafer with the same applied power, which suggests that the combination of the β-Ga2O3 thin film and SiC substrate with high thermal conductivity promotes heat dissipation in β-Ga2O3-based devices.

Defect patterns on semiconductor wafer maps point to different manufacturing problems. Consequently, they have become key factors in identifying and resolving the root causes of yield improvement. Perhaps not surprisingly, the probability of having multiple defect patterns on a wafer map has increased in tandem with advances in manufacturing technology. Prior research on defect patterns has focused primarily on image classification methods which are neither good at mixed-type defect pattern classification nor able to provide locational information for further analysis. This study develops a framework that integrates a Mask R-CNN-based instance segmentation model with copy-paste and rotational data augmentation. The proposed method is able to precisely classify and locate defect patterns on a wafer map given limited training data, tasks which can help companies identify the manufacturing root causes of defects in a timely manner when ramping up their production for yield enhancement. Our experiments were performed using real-world WM-811K data. Using COCO pre-trained weights and only 1,056 items of original training data, the model reached an accuracy of 97.7% on single-type classification. Mixed-type classification hamming loss, exact match and accuracy were 0.155, 69% and 82%, respectively.

Adding ferromagnetism into semiconductors attracts much attentions due to its potential usage of magnetic spins in novel devices, such as spin field-effect transistors. However, it remains challenging to stabilize their ferromagnetism above room temperature. Here we introduce an atomic chemical-solution strategy to grow wafer-size NiO thin films with controllable thickness down to sub-nanometer scale (0.92 nm) for the first time. Surface lattice defects break the magnetic symmetry of NiO and produce surface ferromagnetic behaviors. Our sub-nanometric NiO thin film exhibits the highest reported room-temperature ferromagnetic behavior with a saturation magnetization of 157 emu/cc and coercivity of 418 Oe. Attributed to wafer size, the easily-transferred NiO thin film is further verified in a magnetoresistance device. Our work provides a sub-nanometric platform to produce wafer-size ferromagnetic NiO thin films as atomic layer magnetic units in future transparent magnetoelectric devices.

Transition metal dichalcogenides (TMDs) are materials that can exhibit intriguing optical properties like a change of the bandgap from indirect to direct when being thinned down to a monolayer. Well-resolved narrow excitonic resonances can be observed for such monolayers although only for materials of sufficient crystalline quality and so far mostly available in the form of micrometer-sized flakes. A further significant improvement of optical and electrical properties can be achieved by transferring the TMD on hexagonal boron nitride (hBN). To exploit the full potential of TMDs in future applications, epitaxial techniques have to be developed that not only allow the growth of large-scale, high-quality TMD monolayers but also allow the growth to be performed directly on large-scale epitaxial hBN. In this work, we address this problem and demonstrate that MoSe2 of high optical quality can be directly grown on epitaxial hBN on an entire 2 in. wafer. We developed a combined growth theme for which hBN is first synthesized at high temperature by metal organic vapor phase epitaxy (MOVPE) and as a second step MoSe2 is deposited on top by molecular beam epitaxy (MBE) at much lower temperatures. We show that this structure exhibits excellent optical properties, manifested by narrow excitonic lines in the photoluminescence spectra. Moreover, the material is homogeneous on the area of the whole 2 in. wafer with only ±0.14 meV deviation of excitonic energy. Our mixed growth technique may guide the way for future large-scale production of high quality TMD/hBN heterostructures.

This paper presents an all-SiC fiber-optic Fabry-Perot (FP) pressure sensor based on the hydrophilic direct bonding technology for the applications in the harsh environment. The operating principle, fabrication, interface characteristics, and pressure response test of the proposed all-SiC pressure sensor are discussed. The FP cavity is formed by hermetically direct bonding of two-layer SiC wafers, including a thinned SiC diaphragm and a SiC wafer with an etched cavity. White light interference is used for the detection and demodulation of the sensor pressure signals. Experimental results demonstrate the sensing capabilities for the pressure range up to 800 kPa. The all-SiC structure without any intermediate layer can avoid the sensor failure caused by the thermal expansion coefficient mismatch and therefore has a great potential for pressure measurement in high temperature environments.

Conductive atomic force microscopy (C-AFM) was employed to perform conductivity measurements on a facet-specific Cu2O cube, octahedron, and rhombic dodecahedron and intrinsic Si {100}, {111}, and {110} wafers. Similar I–V curves to those recorded previously using a nanomanipulator were obtained with the exception of high conductivity for the Si {110} wafer. Next, I–V curves of different Cu2O–Si heterostructures were evaluated. Among the nine possible arrangements, Cu2O octahedron/Si {100} wafer and Cu2O octahedron/Si {110} wafer combinations show good current rectification behaviors. Under white light illumination, Cu2O cube/Si {110} wafer and Cu2O rhombic dodecahedron/Si {111} wafer combinations exhibit the largest degrees of photocurrent, so such interfacial plane-controlled semiconductor heterojunctions with light sensitivity can be applied to make photodetectors. Adjusted band diagrams are presented highlighting different interfacial band bending situations to facilitate or inhibit current flow for different Cu2O–Si junctions. More importantly, the observation of clear current-rectifying effects produced at the semiconductor heterojunctions with properly selected contacting faces or planes implies that novel field-effect transistors (FETs) can be fabricated using this design strategy, which should integrate well with current chip manufacturing processes., The Cu2O octahedron/Si {100} wafer combination gives a large current-rectifying effect. The Cu2O rhombic dodecahedron/Si {111} wafer combination shows a notable photocurrent response.

Complementary metal-oxide-semiconductor (CMOS) image sensors have widely been used in internet of thinking (IoT) devices such as smartphones, smart watch and personal computer tablets [1] . The consumer market strongly requires higher sensitivity and higher speed image data processing to realize high functional CMOS image sensors such as three dimensionally stacked back-side-illuminated CMOS image sensors (3D-CIS) [2] . However, there are some serious technological issues in the fabrication of advanced CMOS image sensors as shown in Fig. 1 .

Rare earth (RE) doped oxides have demonstrated great potential for photonic applications and have also appeared as promising candidates for quantum memory devices and microwave to optical transducers. Here, we investigate the potential of Chemical Vapor Deposited (CVD) europium-doped Y2O3thin films on silicon as a new platform for integrated quantum devices. We aim at improving the optical properties of such thin films by carefully controlling the RE ion's environment. In particular, we study the effect of annealing post treatments and demonstrate that a significant source of broadening of the optical transition arises from interfacial reactions with the silicon substrate. We thus propose to encapsulate RE ions between undoped high-quality thick layers in order to limit the impact of interfacial reactions on their properties during thermal annealing. Using this approach, we succeeded in measuring a narrow inhomogeneous linewidth of 18 GHz and an ultra-narrow homogeneous linewidth of 5 MHz inferred from spectral hole width. These results are promising towards the use of these engineered RE doped thin films for the development of a scalable nanostructured spin-photon interface. In addition, our strategy could be applied to a large variety of oxide films for a broad range of applications. Paper published in Materials Advances.

The growth control of a molybdenum disulfide (MoS2) thin film, including the number of layers, growth rate, and electrical property modulation, remains a challenge. In this study, we synthesized MoS2 thin films using the metal-organic chemical vapor deposition (MOCVD) method with a 2 inch wafer scale and achieved high thickness uniformity according to the positions on the substrate. In addition, we successfully controlled the number of MoS2 layers to range from one to five, with a growth rate of 10 min per layer. The layer-dependent optical and electrical properties were characterized by photoluminescence, Raman spectroscopy, differential reflectance spectroscopy, and field effect transistors. To guide the growth of MoS2, we summarized the relation between the growth aspects and the precursor control in the form of a growth map. Reference to this growth map enabled control of the growth rate, domain density, and domain size according to the application purposes. Finally, we confirmed the electrical performance of MOCVD-grown MoS2 with five layers under a high-κ dielectric environment, which exhibited an on/off current ratio of 10∼6 and a maximum field effect mobility of 8.6 cm2 V-1 s-1.

We introduce a new innovative damage-free neutral beam etching (NBE) technique to transfer a honeycomb resist pattern to silicon (Si) wafer (thickness of 180 µm). Front-surface texturing of Si helps to reduce surface reflection and increase light absorption for solar cell applications. NBE was performed with Cl2 and Cl2/ SF6 gases chemistries, and the influence of the etching time on the etching profiles, surface reflection and potential short-circuit densities (p-JSC) was studied. The Si etching rate with pure Cl2 was ~ 5 nm/min and resulted in anisotropic etch profiles and a minimum surface reflection of 15% at 1000 nm, which is too high for practical use. With the introduction of 5% of SF6, the etching rate increased to 30 nm/min, the etching became isotropic (anisotropy of ~ 1), and sloped sidewalls appeared. NBE with Cl2 (95%)/SF6 (5%) produced a sample with an average surface reflection of 3.7% over the wavelength range 300–1000 nm without any antireflection coating. The minimum surface reflection in this case was ~ 1% at 1030 nm and p-JSC was 40.63 mA/cm2. This type of surface pattern is well suited for low-consumption-material (thin), high-efficiency Si solar cells.

In this article, we report a wafer-level packaged Pirani vacuum gauge using the proprietary InvenSense CMOS MEMS technology. The micro Pirani vacuum gauge features three serpentine-shaped molybdenum thermistors on the suspended silicon-on-insulator (SOI) bridges, while the wiring gap of each serpentine-shaped silicon microbridge is 1.6 ${ {\mu }}\text{m}$ . For the vacuum range of $5\times 10^{-{4}}$ –760 Torr, the CMOS MEMS Pirani gauge configured with a constant temperature interface circuit achieves a sensitivity of 0.414 V/Torr in a very fine vacuum regime, while its heating power is less than 21.3 mW. Moreover, the measured output of the micro Pirani gauge shows good agreement with a semi-empirical model, while the model predicts that the proposed Pirani gauge can measure a vacuum pressure as low as $2.6\times 10^{-{4}}$ Torr. The performance achieved by this Pirani vacuum gauge combined with its high level of integration makes it a promising Internet of Things (IoT) sensing node for vacuum monitoring in the industry.

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer‐scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3‐μm bowing was observed using the 725‐μm‐thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4 × 107 cm−2. For lattice‐matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725‐μm‐thick Si substrate can be used for the large‐scale integration of GaAs on Si with less bowing and low TDD.

A novel fan-out wafer-level packaging (FOWLP) technology with double-sided redistribution layers (RDLs) and tall copper vertical interconnects is described. The design of a dual-polarized magnetoelectric (ME) dipole antenna based on this new packaging technology is presented. It is shown that the antenna with a size of $10\times10$ mm2 achieves good impedance matching and a stable radiation pattern over a wide bandwidth from 25 to 43 GHz, which can cover most of the millimeter-wave (mmWave) bands of the fifth-generation (5G) mobile networks in different countries. The measurement results demonstrate that the antenna is well suited for FOWLP technology and can be used for phased-array modules in 5G wireless communication systems.

Different deep convolution neural network (DCNN) models have been proposed for wafer map pattern identification and classification tasks in previous studies. However, factors such as the effect of input image resolution on the classification performance of the proposed models and class imbalance in the training set after splitting the data into training and test sets have not been considered in the previous studies. This study proposes a DCNN model with residual blocks, called Opt-ResDCNN model, for wafer map defect pattern identification and classification by considering 26 * 26 input image resolutions and class imbalance issues during the model training. The proposed model is compared with the previously published defect pattern recognition and classification models in terms of accuracy, precision, recall, and F1 score for 26 * 26 input image size. Using a publicly available wafer map dataset (WM-811K), the proposed method can obtain an average accuracy, precision, recall, and F1 score results of 99.672%, 99.664%, 99.695%, 99.692%, respectively for the 26 * 26 input image resolution.

β-phase gallium oxide (Ga2O3) is an emerging ultrawide bandgap (UWBG) semiconductor (EG ∼ 4.8 eV), which promises generational improvements in the performance and manufacturing cost over today's commercial wide bandgap power electronics based on GaN and SiC. However, overheating has been identified as a major bottleneck to the performance and commercialization of Ga2O3 device technologies. In this work, a novel Ga2O3/4H-SiC composite wafer with high heat transfer performance and an epi-ready surface finish has been developed using a fusion-bonding method. By taking advantage of low-temperature metalorganic vapor phase epitaxy, a Ga2O3 epitaxial layer was successfully grown on the composite wafer while maintaining the structural integrity of the composite wafer without causing interface damage. An atomically smooth homoepitaxial film with a room-temperature Hall mobility of ∼94 cm2/Vs and a volume charge of ∼3 × 1017 cm-3 was achieved at a growth temperature of 600 °C. Phonon transport across the Ga2O3/4H-SiC interface has been studied using frequency-domain thermoreflectance and a differential steady-state thermoreflectance approach. Scanning transmission electron microscopy analysis suggests that phonon transport across the Ga2O3/4H-SiC interface is dominated by the thickness of the SiNx bonding layer and an unintentionally formed SiOx interlayer. Extrinsic effects that impact the thermal conductivity of the 6.5 μm thick Ga2O3 layer were studied via time-domain thermoreflectance. Thermal simulation was performed to estimate the improvement of the thermal performance of a hypothetical single-finger Ga2O3 metal-semiconductor field-effect transistor fabricated on the composite substrate. This novel power transistor topology resulted in a ∼4.3× reduction in the junction-to-package device thermal resistance. Furthermore, an even more pronounced cooling effect is demonstrated when the composite wafer is implemented into the device design of practical multifinger devices. These innovations in device-level thermal management give promise to the full exploitation of the promising benefits of the UWBG material, which will lead to significant improvements in the power density and efficiency of power electronics over current state-of-the-art commercial devices.

Funding Information: This work was financially supported by NanoLund, Myfab, the Swedish Research Council, the Swedish Energy Agency, and the Knut and Alice Wallenberg Foundation. Publisher Copyright: © 2021 The Authors. Published by American Chemical Society. Nanowire solar cells have the potential to reach the same efficiencies as the world-record III-V solar cells while using a fraction of the material. For solar energy harvesting, large-area nanowire solar cells have to be processed. In this work, we demonstrate the synthesis of epitaxial InP nanowire arrays on a 2 inch wafer. We define five array areas with different nanowire diameters on the same wafer. We use a photoluminescence mapper to characterize the sample optically and compare it to a homogeneously exposed reference wafer. Both steady-state and time-resolved photoluminescence maps are used to study the material's quality. From a mapping of reflectance spectra, we simultaneously extract the diameter and length of the nanowires over the full wafer. The extracted knowledge of large-scale nanowire synthesis will be crucial for the upscaling of nanowire-based solar cells, and the demonstrated wafer-scale characterization methods will be central for quality control during manufacturing.

Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. The main method for reducing the trench width is to design large trench angle. However large trench angle for better characteristics causes some challenges. And process window always becomes narrow to get excellent characteristic. For quality control of trench angle, we found that the wafer warpage was related to the trench angle at two process steps. We confirmed these mechanisms by simulation and experiment. Furthermore, we examined which process step was appropriate for monitoring the trench angle by wafer warpage. Finally, we acquired four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation.

A space-divided plasma-enhanced atomic layer deposition (PE-ALD) system in which disk and wafer rotate at the same time was developed. In the space-divided PE-ALD system, the disk and the wafer are each independently rotated and deposited. It has the advantage that high productivity and dispersion can be improved by controlling the rotation speed of the disk and wafer. Also, it can be applied to various processes by changing the design of the upper lid slightly. In this study, a study on the deposition characteristics of SiO2 thin films was conducted using the developed spatially divided PE-ALD system. The effect of the rotation speed of the disk and wafer on the deposition rate and the uniformity characteristics of the SiO2 thin film was confirmed, and a study on the correlation with the wet etch rate was conducted.

Impact of total ionizing dose (TID) on the within-wafer variability of radiation-hardened (RH) silicon-on-insulator (SOI) wafers is investigated in this article. The within-wafer variability is measured by the front gate and back gate $I$ – $V$ characteristics of the transistors in 32 dies evenly distributed on wafer locations. The experimental results show the complex dependence of the within-wafer variability on TID: the within-wafer variability of RH SOI wafer is first weakened by TID irradiation and then rebounds. The evolution of net trapped charge induced by TID in buried oxide (BOX) is affected by positively charged silicon nanoclusters introduced by silicon ion implantation, which is responsible for the above complex dependence. Moreover, radiation hardness assurance method relying on sample testing of limited wafer locations is discussed, which can give the reasonable estimation of the within-wafer variability on TID irradiated devices.

It is demonstrated that reflection of a continuous-wave single-frequency laser radiation from a thick flat-parallel glass wafer can be used for precise remote measurement of temperature. Such measurement relies on the low-finesse Fabry-Perot nature of the dielectric wafer, whose optical thickness depends on temperature due to two characteristics of the dielectric material: the linear expansion coefficient and the thermo-optic coefficient. For the used glass wafer with a refractive index of 1.5183 and a thickness of 15.75 mm, the temperature distance between adjacent interference peaks was 1.4825°C, which made it possible to measure the temperature with a mean accuracy of 0.005°C. Performance aspects of the proposed temperature sensor and its practical applicability are analyzed.

Close integration of transducer arrays with supporting electronic circuits is essential in achieving efficient and compact ultrasound systems. An integral part of hybrid integration of 2D CMUT array to CMOS electronics is the introduction of through-glass-via (TGV) interconnects in glass substrates as an integral part of the 2D CMUT array fabrication. Micro-cracks around via locations, via discontinuity, and poor coplanarity between the vias and glass substrate are some of the challenges with laser-drilled, paste-filled copper-through-glass-via (Cu-TGV) interconnects. This study provides a detailed fabrication process for making $32\times 32$ -element 2D CMUT arrays on a composite glass substrate incorporating silicon-through-glass vias (Si-TGV) as interconnects using sacrificial release approach. On one column of a fabricated 2D CMUT array, we measured a mean resonant frequency of 5.6 MHz in air and an average device capacitance of 1.5 pF. With the introduction of a buried top electrode in the device structure, we achieved a collapse voltage of 93 V, which is considerably lower than the collapse voltage measured in our previously demonstrated 2D CMUT arrays with top electrode on top of the nitride plate. The fabricated array is flip-chip bonded on a custom-designed driving integrated circuit to demonstrate the complete system operation. We measured a peak-to-peak pressure of 1.82 MPa at 3.4 MHz, and 5 mm from the array surface in a 0.33 mm focal spot size. [2021-0101]

Different combinations of metal thin films were investigated as metal interconnect for miniaturized microelectromechanical system (MEMS) encapsulation with stable electrical properties and sealing capability. The candidates of metal as the adhesion layer include Cr, Ti, and Ta. Metals Pt and Pd are the selection for the diffusion barrier layer. Comparison results of adhesion tests, stress measurements, and aging tests show that the interconnect of Ti-Pd-Au has the best stability in MEMS devices. After the screening process, the analyses of scanning acoustic tomography (SAT), scanning electron microscope (SEM), and pull test verify that the symmetric and ultrathin Ti-Pd-Au structure can be bonded well for the sealing process. Furthermore, the plasma treatment was conducted to reduce the thermal budget of encapsulation. The reliability tests present the bonding scheme with plasma treatment can withstand rapid temperature variation and high moisture for a long duration. All the results show that the interconnect of Ti-Pd-Au simultaneously used in the sealable encapsulation has a great potential for advanced miniaturized MEMS packaging.

The Co@NCNTs/Si pillars with channels is assemble to a suitable pure water gathering device, which is applied in seawater desalination and sewage purification to produce pure water by utilizing solar energy. High-efficiency utilization of solar energy to generate water vapor is popular, recyclable, and environmentally friendly for seawater desalination and sewage purification, helping to alleviate the global water shortage crisis. Here, we report an efficient and simple method to prepare a three-dimensional (3D) evaporator for steam generation by harnessing the power of the sun. This evaporation is composed of one-dimensional (1D) cobalt embedded and nitrogen doped carbon nanotubes (Co@NCNTs) and 3D silicon pillars array structure (Si pillars). The Co@NCNTs/Si pillars shows a wide light absorption range provided by carbon nanotubes and a long light absorption path because of the silicon pillars. The surface temperature of the sample rises rapidly in 1.5 min and exceed 80 °C under solar illumination of one sun. The water evaporation can be high as 1.21 kg m−2 h−1 under one sun irradiation (1 kW/m2) with the energy efficiency up to 82.4%. This scalable Co@NCNTs/Si pillars can prepare pure water from seawater and sewage, where the removal rate of ions in seawater and pollutants in sewage is similar to 100%. Based on our research, this multistage three-dimensional structure is a simple and efficient novel photothermal material for extensive seawater desalination and sewage purification.

In the next-generation computing framework, synaptic devices modulated using analogue weight storage are expected with capability of performing neuromorphic computing tasks. Recently, 2D transition metal dichalcogenides (TMDCs) based solid-state devices have demonstrated excellent electrical performance showing great potential in nanoscale synaptic electronics. In this letter, artificial synaptic transistors are proposed and fabricated on the atomic layer deposited 2D MoS2 thin film with an integrated high-k dielectric gate stack. The synapse cells can simulate fundamental synaptic functions similar to those of biological synapses, such as long-term potentiation and depression. Moreover, the ultralow power consumption shows that the proposed synapse is more efficient than most three-terminal synaptic transistors. We also emulate a multi-synapse network to demonstrate intrinsic heterogeneity in biological brain. The experimental results have validated the feasibility of synaptic devices based on 2D TMDCs and have contributed a promising approach to the development of the next-generation brain-like neuromorphic systems.

This paper analyzes the commonly used wafer-level S-parameter calibration methods LRRM, multiline TRL and LRM+ for the sensitivity to the thermal variation of electrical characteristics of planar calibration standards. We demonstrate that the calibration error of lumped-standard based methods can be significantly reduced by taking into account the variation of Load standard resistance over the temperature. The obtained results proved that for the evaluated commercially available calibration standards and for a given frequency range, the overall calibration error due to the temperature variation is in order of magnitude of repeatability of the manual system calibration. The proposed method can be successfully applied for different calibration substrates, temperature and frequency ranges, as well as to the in-situ calibration element.

A novel electron beam detector made on Si wafers by the advanced CMOS FinFET processes has been proposed in this study. Through electron beam (e-Beam) charging of on-wafer sensing pads, electron dosage can be registered on the detector for follow-up read-out. Without external power or battery connections, this detector has successfully delivered on-chip dosage, intensity, and energy after e-Beam exposure.

In this letter, the redistribution layer-first embedded fan-out wafer-level packaging (RDL-first FO-WLP) for 2-D ultrasonic transducer arrays with individual electrical connection is proposed. This process provides the capability of manufacturing thin film circuit with multilayer RDLs and allows signals of elements in arrays being fanned-out to a region larger than the array size. An anisotropic conductive film (ACF) with low curing temperature is employed to provide the electrical and mechanical connection between RDLs and ultrasonic transducer arrays. The thin film circuit with multilayer RDLs and ultrasonic transducer arrays were respectively fabricated and the curing temperature of ACF is close to half of the Curie temperature of the array. This process avoids ultrasonic transducer arrays losing their piezoelectric property, for ultrasonic transducer arrays are not suffering from the high curing temperature of the passivation layers and of the bonding process.

This article focuses on the material properties of two III-V semiconductors, AlGaAs and GaInAsP, and their usage as middle cell absorber materials in a wafer-bonded III-V//Si triple-junction solar cell. To this end single-junction solar cells were grown epitaxially lattice matched on GaAs wafers using metalorganic vapor phase epitaxy. By optimizing the growth temperature and the V/III ratio we could increase the open-circuit voltage at a target absorber band gap of 1.50 eV by up to 100 mV. In the future these results will be implemented into two-terminal III-V//Si triple-junction solar cells to increase the conversion efficiency beyond 35% under the AM1.5g solar spectrum.

Thispaper introduces a novel, inherently simple, and all-silicon wafer-level fabrication and hermetic packaging method developed for MEMS devices. The proposed method uses two separate SOI wafers to form highly-doped through-silicon vias (TSVs) and suspended MEMS structures, respectively. These SOI wafers are then bonded by Au-Si eutectic bonding at 400 °C, achieving hermetic sealing and signal transfer without requiring any complex via or trench refill process steps. The package vacuum is measured using encapsulated MEMS resonators to be as low as 15 mTorr with the help of successfully activated thin-film getters. The combined fabrication and packaging yield is around %89 and chips still maintain a package pressure below 100 mTorr after more than 6 years. The packages show an extremely high strong bonding strength (>40 MPa) and are proved to remain hermetic after temperature cycling (25 °C-85 °C) and harsh temperature shock (5 min@300 °C) tests. The all-silicon MEMS resonators fabricated and packaged using the proposed method project up to a $2.3\times $ enhancement in the bias instability and $\sim 4\times $ in the temperature sensitivity of frequency output compared to an identical MEMS resonator fabricated using the silicon-on-glass (SOG) technology.

The rapid growth of the advanced consumer 5G wireless mobile phones has propelled the demands of fabricating surface acoustic wave (SAW) filters with smaller size and high performance. Three-dimension wafer-level package (3-D WLP) for SAW filter is a promising solution to replace conventional surface mounted technology and chip-scale packaging. In this article, a new WLP for SAW filter with a size of 1.3 mm $\times1.1$ mm $\times0.35$ mm is developed using thin dry film capping. The new 3-D WLP significantly reduces the overall thickness which is particularly meaningful for low-profile smartphones and tablets. A number of key processes were developed. To improve the quality, finite element modeling (FEM) is used to simulate the mechanical stress to optimize cavity structure. Reliability tests were performed and the results indicated that there were no significant frequency response changes occurred and low insertion loss (IL) in pass band was less than 0.2 dB after pro-conditional level 3 test, unbiased highly accelerated stress (uHAST) test, and temperature cycling (TC) test on SAW filter packages. It can be concluded that 3-D WLP for SAW filter achieves miniaturization, good electrical performance, and reliability.

Integrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$4520\;{\mathrm{cm}}^2{\mathrm{V}}^{ - 1}{\mathrm{s}}^{ - 1}$$\end{document}4520cm2V−1s−1. Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing., The existing integration approaches for 2D materials often degrade material properties and are not compatible with industrial processing. Here, the authors devise an adhesive wafer bonding strategy to transfer and stack monolayers, suitable for back end of the line integration of 2D materials.

Advancements in technology have made deep learning a hot research area, and we see its applications in various fields. Its widespread use in silicon wafer defect recognition is replacing traditional machine learning and image processing methods of defect monitoring. This article presents a review of the deep learning methods employed for wafer map defect recognition. A systematic literature review (SLR) has been conducted to determine how the semiconductor industry is leveraged by deep learning research advancements for wafer defects recognition and analysis. Forty-four articles from well-known databases have been selected for this review. The articles’ detailed study identified the prominent deep learning algorithms and network architectures for wafer map defect classification, clustering, feature extraction, and data synthesis. The identified learning algorithms are grouped as supervised learning, unsupervised learning, and hybrid learning. The network architectures include different forms of Convolutional Neural Network (CNN), Generative Adversarial Network (GAN), and Auto-encoder (AE). Various issues of multi-class and multi-label defects have been addressed, solving data unavailability, class imbalance, instance labeling, and unknown defects. For future directions, it is recommended to invest more efforts in the accuracy of the data generation procedures and the defect pattern recognition frameworks for defect monitoring in real industrial environments.

Silicon wafer as a direct material is one of the vital parts of a semiconductor product. Wastages on manufacturing plants that pulls the yield down should be addressed innovatively and accurately. This paper focused on the phenomenon of broken wafers at wafer taping process during wafer preparation. Using a wafer taper machine, silicon wafers are covered by an industrial tape as preparation for the next process. During processing and wafers are placed on wafer boat, unexpected phenomenon of broken wafers due to unwanted falling was encountered. Findings was due to the unintentional dragging of the machine’s robot arm after wafer processing. The problem is resolved through simulation and experiments using statistical analysis. As a result, an optimized machine parameter setting was defined to eliminate the said rejection. Statistical analysis was of a big help in resolving the said phenomenon and improved the process yield of the manufacturing.

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

The rise of various Wafer technologies has been developed based on industries and applications requirement. Highest quality of material characterization is complex and requires specialized process equipment and manufacturing procedures to meet defined design standards. The paper presents distinctive glass wafer-level fabrication technology that will enhance its properties with respect to pattern recognition system (PRS) at back-end manufacturing for industrial applications. Feasibility of colored glass wafer has been built into proposed conception to manufacture wafer-level packaging. The idea from transparent to colored glass wafer came from manufacturing key challenges that cutting sequence during pattern recognition cannot be distinguished. The proposed solution will mitigate high risk of misaligned cut at wafer sawing and its potential attachment on leadframe during die attach. glass wafer dice, transparent in nature, intermittently encountered multiple PRS assist during Wafer sawing and die attach as it hardly recognizes its cutting positions. Since dependent of machine capability limitations, misaligned cut is inevitable and usually happen occasionally. Addressing its unrecognizable characteristic, proposed colored glass wafer and with visible outline and saw lane fabrication was conceptualized instead of seeking ideal and high equipment model that can differentiate its opaque feature. The colored glass wafer and with visible outline and saw lane naturally creates segmentation visibly and will not be parameter dependent during manufacturing.

Wafer test is carried out after integrated circuits (IC) fabrication to screen out bad dies. In addition, the results can be used to identify problems in the fabrication process and improve manufacturing yield. However, the wafer test itself may induce defects to otherwise good dies. Test-induced defects not only hurt overall manufacturing yield but also create problems for yield learning, so the source problems in testing should be identified quickly. In the wafer acceptance test process, dies are probed in a predetermined order, so test-induced defects, also known as site-dependent faults, exhibit specific patterns that can be effectively captured in test paths. In this paper, we analyze characteristics of test-induced defect patterns and define features that can be used by machine learning algorithms for the automatic detection of test-induced defects. Therefore, defective dies caused by the wafer test can be retested for yield improvement. Test data from six real products are used to validate the proposed method. Several machine learning algorithms have been applied, and experimental results show that our method is effective to distinguish between test-induced and fabrication-induced defects. On average, the prediction accuracy is higher than 97%.

Summary The extension of graphitic carbon nitride (g-CN) materials into optoelectronic applications beyond photocatalysis has long been anticipated due to their non-metallic composition, moderate electronic band gap, and excellent stability. However, large-scale synthesis of uniform two-dimensional (2D) g-CN films with high crystallinity and tunable thickness remains the bottleneck for their future applications in optoelectronic devices. Here, a vapor-phase transport-assisted condensation method has been developed for the wafer-scale synthesis of uniform 2D g-CN films with tunable thickness. First-principle calculations indicate the direct condensation from melem to heptazine-based carbon nitride enables the formation of high-quality g-CN films. A facile water-assisted transfer strategy is developed for subsequent fabrication on arbitrary substrate. A free-standing flexible photodetector array with strain-insensitive responsibility is demonstrated with the g-CN films as imaging pixels. This study provides a convenient route to wafer-scale growth of high-quality 2D g-CN films and paves the way to the g-CN-based electronic and optoelectronic devices.