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System-on-Chip (SoC) designs are increasingly difficult to test using traditional scan access methods without incurring inefficient test time, high planning effort, and physical design/timing closure challenges. The number of cores keeps growing while chip pin counts available for scan remain constant or decline, limiting the ability to drive cores concurrently. With increasingly commonplace tiling and abutment, the scan distribution hardware must be placed inside the cores, making balanced pipelining when broadcasting to identical cores difficult. optimizing test time requires analyzing all the cores and subsequently changing the test hardware in the cores. Internal shift speed constraints may limit the ability to shift data in and out of the chip at high rates. Differences in pattern counts or scan chain lengths between cores tested in parallel can result in padding and increased test time. SSN is a bus-based scan data distribution architecture designed to address all these challenges. It enables simultaneous testing of any number of cores even with few chip I/Os. It facilitates short test time by enabling high-speed data distribution, by efficiently handling imbalances between cores, and by supporting testing of any number of identical cores with a constant cost. It provides a plug-and-play interface in each core that is well suited for abutted tiles, and simplifies scan timing closure. This paper also compares the test cost and implementation productivity of SSN with those of Intel’s Structural Test Fabric.

This paper proposes an innovative design methodology for layout-friendly decompressor used in EDT compression architecture. A segmented decompressor architecture is proposed, in which each segment drives a subset of scan chains. The EDT input channel injectors are carefully selected to maximize the encoding capacity for all scan chains. Experimental results with several large industrial designs demonstrate that using the proposed technology, the routing congestion introduced by EDT decompressor is reduced significantly with negligible impact on test coverage and improved pattern count.

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

Modular test and hierarchical test of core-based System-on-Chip (SoC) are two widely used SoC test methodologies. In this paper, the hybrid test methodology that incorporates these two together is studied by using an industrial real case. Thorough experimental results are demonstrated to compare various scenarios of the hybrid hierarchical and modular tests for SoC designs. Based on the experimental results, using channel sharing based modular test technology at a group of cores combined with hierarchical test to map the patterns of core groups to the top level would result in the most efficient total test time.

This paper presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work seamlessly with existing sequential linear decompressors. Experimental results obtained for industrial designs demonstrate the effectiveness of the proposed method at reducing TDV in high compression configurations.

This paper proposes an innovative test compression technology for system-on-chip (SoC) designs to share scan input channels across multiple cores which use EDT [1] compression. A new DFT compression architecture is proposed to separate control and data channels such that the control channels can be individually accessible, whereas data channels can be shared among a group of cores. The paper illustrates the benefits of the proposed technology in both the enhancement of compression ratios and the flexibility of test compression planning in a core-based SoC design flow. Experimental results with a few large industrial SoCs demonstrate that using the proposed technology the compression can be improved up to 1.87X.

This paper introduces a novel Test Access Mechanism (TAM) for chips with multiple isolated identical cores through which all the cores can be tested in parallel and at the same time accurate failure diagnosis can be achieved while requiring similar test resources (tester memory and tester channels) as for a single core. The proposed pipelined architecture relies on forming nonlinear equations on a very limited number of output pins that compress the outputs from the identical cores and solve them off-chip to reproduce the failure information of each core. A very nice feature of the proposed scheme is that the number of observation pins required to achieve a desirable level of diagnostic resolution does not scale with the number of identical cores and can practically be kept constant.

This paper presents a clock control architecture for designs with multiple clock domains, and a novel mix of existing ATPG techniques as well as novel ATPG enhancements. The combination of the ATPG techniques and the clock control hardware lowers the number of test patterns in a fully automated flow, while maintaining the high coverage that is required nowadays by production test. Experimental results are shown for two industrial designs.

This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restrictions originated from the on-chip clock generators into account in order to avoid generating clock sequences that cannot be produced by hardware. Experimental results on industrial designs show test pattern reduction and/or ATPG run time reduction when compared with the test generation method that enumerates valid clock sequences explicitly and restricts the test generation within enumerated test sequences.

Before on-chip scan compression, it was possible to use different EDA tool vendors to do scan insertion, pattern generation, and diagnosis. On-chip scan compression changed that use model since each tool vendor supplied a different type of scan compression logic and had tool-specific ways to pass necessary information from scan insertion to pattern generation and from pattern generation to diagnosis. OCI (Open Compression Interface) is a standardization of how the necessary data is passed from test logic insertion to pattern generation to diagnosis such that different vendors can be used for each step independent of the on-chip scan compression logic used. This document discusses the need for OCI and gives a conceptual overview of the OCI standard.

Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.