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Erratum to 'Test Time Reduction in EDT Bandwidth Management for SoC Designs' [Nov 13 1776-1786]
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:167-167
- Publication Year :
- 2014
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2014.
-
Abstract
- Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.
Details
- ISSN :
- 19374151, 02780070, and 17761786
- Volume :
- 33
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Accession number :
- edsair.doi...........ab64563c1023c39946287c77f8c26d05