Search

This Letter proposes a low-cost, single event double-upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C-element (MCE) to turn off the storage cell, a three-input MCE to block the soft error from the storage cell and a weak keeper to prevent high impedance state. The storage cell in the proposed latch has better reliability than the conventional triple path dual-interlocked storage cell (TPDICE). Most up-to-date single event double-upset (SEDU) tolerant latches are carried out with too large cost penalties. The proposed one saves up to 93.32% area-power-delay product (APDP) compared with one up-to-date SEDU tolerant latch and even saves 36.36% APDP compared with only single event upset (SEU) tolerant latch in the referential. Simulation results have verified SEU and SEDU tolerance of the proposed latch.

This paper proposes a novel soft-error-tolerant ultralow-leakage 12T bitcell. Compared with all the other considered bitcells, the proposed cell saves 90.76% leakage power and 18.43% write access time on average. Simulation results verify the basic functions and single event upset (SEU) tolerance of the proposed. Hence, it is an excellent choice for highly reliable ultralow-leakage applications like the Internet of Things (IoT).

This paper presents a novel highly reliable dual port 12T static random access memory (SRAM) bitcell. Compared with the state-of-the-art soft-error-tolerant bitcells and the traditional 6T, the proposed 12T exhibits much larger read noise margin (RSNM), and also saves 85.4% read access time on average, making it much suitable for high-speed highly reliable applications.